irq-xtensa-pic.c 2.6 KB

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  1. /*
  2. * Xtensa built-in interrupt controller
  3. *
  4. * Copyright (C) 2002 - 2013 Tensilica, Inc.
  5. * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. *
  11. * Chris Zankel <chris@zankel.net>
  12. * Kevin Chea
  13. */
  14. #include <linux/bits.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irqdomain.h>
  17. #include <linux/irq.h>
  18. #include <linux/irqchip.h>
  19. #include <linux/irqchip/xtensa-pic.h>
  20. #include <linux/of.h>
  21. /*
  22. * Device Tree IRQ specifier translation function which works with one or
  23. * two cell bindings. First cell value maps directly to the hwirq number.
  24. * Second cell if present specifies whether hwirq number is external (1) or
  25. * internal (0).
  26. */
  27. static int xtensa_pic_irq_domain_xlate(struct irq_domain *d,
  28. struct device_node *ctrlr,
  29. const u32 *intspec, unsigned int intsize,
  30. unsigned long *out_hwirq, unsigned int *out_type)
  31. {
  32. return xtensa_irq_domain_xlate(intspec, intsize,
  33. intspec[0], intspec[0],
  34. out_hwirq, out_type);
  35. }
  36. static const struct irq_domain_ops xtensa_irq_domain_ops = {
  37. .xlate = xtensa_pic_irq_domain_xlate,
  38. .map = xtensa_irq_map,
  39. };
  40. static void xtensa_irq_mask(struct irq_data *d)
  41. {
  42. u32 irq_mask;
  43. irq_mask = xtensa_get_sr(intenable);
  44. irq_mask &= ~BIT(d->hwirq);
  45. xtensa_set_sr(irq_mask, intenable);
  46. }
  47. static void xtensa_irq_unmask(struct irq_data *d)
  48. {
  49. u32 irq_mask;
  50. irq_mask = xtensa_get_sr(intenable);
  51. irq_mask |= BIT(d->hwirq);
  52. xtensa_set_sr(irq_mask, intenable);
  53. }
  54. static void xtensa_irq_ack(struct irq_data *d)
  55. {
  56. xtensa_set_sr(BIT(d->hwirq), intclear);
  57. }
  58. static int xtensa_irq_retrigger(struct irq_data *d)
  59. {
  60. unsigned int mask = BIT(d->hwirq);
  61. if (WARN_ON(mask & ~XCHAL_INTTYPE_MASK_SOFTWARE))
  62. return 0;
  63. xtensa_set_sr(mask, intset);
  64. return 1;
  65. }
  66. static struct irq_chip xtensa_irq_chip = {
  67. .name = "xtensa",
  68. .irq_mask = xtensa_irq_mask,
  69. .irq_unmask = xtensa_irq_unmask,
  70. .irq_ack = xtensa_irq_ack,
  71. .irq_retrigger = xtensa_irq_retrigger,
  72. };
  73. int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent)
  74. {
  75. struct irq_domain *root_domain =
  76. irq_domain_create_legacy(NULL, NR_IRQS - 1, 1, 0,
  77. &xtensa_irq_domain_ops, &xtensa_irq_chip);
  78. irq_set_default_domain(root_domain);
  79. return 0;
  80. }
  81. static int __init xtensa_pic_init(struct device_node *np,
  82. struct device_node *interrupt_parent)
  83. {
  84. struct irq_domain *root_domain =
  85. irq_domain_create_linear(of_fwnode_handle(np), NR_IRQS, &xtensa_irq_domain_ops,
  86. &xtensa_irq_chip);
  87. irq_set_default_domain(root_domain);
  88. return 0;
  89. }
  90. IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init);