imx6ul_tsc.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. //
  3. // Freescale i.MX6UL touchscreen controller driver
  4. //
  5. // Copyright (C) 2015 Freescale Semiconductor, Inc.
  6. #include <linux/errno.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/gpio/consumer.h>
  11. #include <linux/input.h>
  12. #include <linux/slab.h>
  13. #include <linux/completion.h>
  14. #include <linux/delay.h>
  15. #include <linux/of.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/log2.h>
  21. /* ADC configuration registers field define */
  22. #define ADC_AIEN BIT(7)
  23. #define ADC_ADCH_MASK GENMASK(4, 0)
  24. #define ADC_CONV_DISABLE 0x1F
  25. #define ADC_AVGE BIT(5)
  26. #define ADC_CAL BIT(7)
  27. #define ADC_CALF BIT(1)
  28. #define ADC_CONV_MODE_MASK GENMASK(3, 2)
  29. #define ADC_12BIT_MODE 0x2
  30. #define ADC_IPG_CLK 0x00
  31. #define ADC_INPUT_CLK_MASK GENMASK(1, 0)
  32. #define ADC_CLK_DIV_8 0x03
  33. #define ADC_CLK_DIV_MASK GENMASK(6, 5)
  34. #define ADC_SAMPLE_MODE BIT(4)
  35. #define ADC_HARDWARE_TRIGGER BIT(13)
  36. #define ADC_AVGS_MASK GENMASK(15, 14)
  37. #define SELECT_CHANNEL_4 0x04
  38. #define SELECT_CHANNEL_1 0x01
  39. /* ADC registers */
  40. #define REG_ADC_HC0 0x00
  41. #define REG_ADC_HC1 0x04
  42. #define REG_ADC_HC2 0x08
  43. #define REG_ADC_HC3 0x0C
  44. #define REG_ADC_HC4 0x10
  45. #define REG_ADC_HS 0x14
  46. #define REG_ADC_R0 0x18
  47. #define REG_ADC_CFG 0x2C
  48. #define REG_ADC_GC 0x30
  49. #define REG_ADC_GS 0x34
  50. #define ADC_TIMEOUT msecs_to_jiffies(100)
  51. /* TSC registers */
  52. #define REG_TSC_BASIC_SETTING 0x00
  53. #define REG_TSC_PRE_CHARGE_TIME 0x10
  54. #define REG_TSC_FLOW_CONTROL 0x20
  55. #define REG_TSC_MEASURE_VALUE 0x30
  56. #define REG_TSC_INT_EN 0x40
  57. #define REG_TSC_INT_SIG_EN 0x50
  58. #define REG_TSC_INT_STATUS 0x60
  59. #define REG_TSC_DEBUG_MODE 0x70
  60. #define REG_TSC_DEBUG_MODE2 0x80
  61. /* TSC_MEASURE_VALUE register field define */
  62. #define X_VALUE_MASK GENMASK(27, 16)
  63. #define Y_VALUE_MASK GENMASK(11, 0)
  64. /* TSC configuration registers field define */
  65. #define MEASURE_DELAY_TIME_MASK GENMASK(31, 8)
  66. #define DETECT_5_WIRE_MODE BIT(4)
  67. #define AUTO_MEASURE BIT(0)
  68. #define MEASURE_SIGNAL BIT(0)
  69. #define DETECT_SIGNAL BIT(4)
  70. #define VALID_SIGNAL BIT(8)
  71. #define MEASURE_INT_EN BIT(0)
  72. #define MEASURE_SIG_EN BIT(0)
  73. #define VALID_SIG_EN BIT(8)
  74. #define DE_GLITCH_MASK GENMASK(30, 29)
  75. #define DE_GLITCH_DEF 0x02
  76. #define START_SENSE BIT(12)
  77. #define TSC_DISABLE BIT(16)
  78. #define DETECT_MODE 0x2
  79. #define STATE_MACHINE_MASK GENMASK(22, 20)
  80. struct imx6ul_tsc {
  81. struct device *dev;
  82. struct input_dev *input;
  83. void __iomem *tsc_regs;
  84. void __iomem *adc_regs;
  85. struct clk *tsc_clk;
  86. struct clk *adc_clk;
  87. struct gpio_desc *xnur_gpio;
  88. u32 measure_delay_time;
  89. u32 pre_charge_time;
  90. bool average_enable;
  91. u32 average_select;
  92. u32 de_glitch;
  93. struct completion completion;
  94. };
  95. /*
  96. * TSC module need ADC to get the measure value. So
  97. * before config TSC, we should initialize ADC module.
  98. */
  99. static int imx6ul_adc_init(struct imx6ul_tsc *tsc)
  100. {
  101. u32 adc_hc = 0;
  102. u32 adc_gc;
  103. u32 adc_gs;
  104. u32 adc_cfg;
  105. unsigned long timeout;
  106. reinit_completion(&tsc->completion);
  107. adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
  108. adc_cfg &= ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK);
  109. adc_cfg |= FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) |
  110. FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK);
  111. adc_cfg &= ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE);
  112. adc_cfg |= FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8);
  113. if (tsc->average_enable) {
  114. adc_cfg &= ~ADC_AVGS_MASK;
  115. adc_cfg |= FIELD_PREP(ADC_AVGS_MASK, tsc->average_select);
  116. }
  117. adc_cfg &= ~ADC_HARDWARE_TRIGGER;
  118. writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
  119. /* enable calibration interrupt */
  120. adc_hc |= ADC_AIEN;
  121. adc_hc |= FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE);
  122. writel(adc_hc, tsc->adc_regs + REG_ADC_HC0);
  123. /* start ADC calibration */
  124. adc_gc = readl(tsc->adc_regs + REG_ADC_GC);
  125. adc_gc |= ADC_CAL;
  126. if (tsc->average_enable)
  127. adc_gc |= ADC_AVGE;
  128. writel(adc_gc, tsc->adc_regs + REG_ADC_GC);
  129. timeout = wait_for_completion_timeout
  130. (&tsc->completion, ADC_TIMEOUT);
  131. if (timeout == 0) {
  132. dev_err(tsc->dev, "Timeout for adc calibration\n");
  133. return -ETIMEDOUT;
  134. }
  135. adc_gs = readl(tsc->adc_regs + REG_ADC_GS);
  136. if (adc_gs & ADC_CALF) {
  137. dev_err(tsc->dev, "ADC calibration failed\n");
  138. return -EINVAL;
  139. }
  140. /* TSC need the ADC work in hardware trigger */
  141. adc_cfg = readl(tsc->adc_regs + REG_ADC_CFG);
  142. adc_cfg |= ADC_HARDWARE_TRIGGER;
  143. writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG);
  144. return 0;
  145. }
  146. /*
  147. * This is a TSC workaround. Currently TSC misconnect two
  148. * ADC channels, this function remap channel configure for
  149. * hardware trigger.
  150. */
  151. static void imx6ul_tsc_channel_config(struct imx6ul_tsc *tsc)
  152. {
  153. u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4;
  154. adc_hc0 = FIELD_PREP(ADC_AIEN, 0);
  155. writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0);
  156. adc_hc1 = FIELD_PREP(ADC_AIEN, 0) |
  157. FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4);
  158. writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1);
  159. adc_hc2 = FIELD_PREP(ADC_AIEN, 0);
  160. writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2);
  161. adc_hc3 = FIELD_PREP(ADC_AIEN, 0) |
  162. FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1);
  163. writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3);
  164. adc_hc4 = FIELD_PREP(ADC_AIEN, 0);
  165. writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4);
  166. }
  167. /*
  168. * TSC setting, confige the pre-charge time and measure delay time.
  169. * different touch screen may need different pre-charge time and
  170. * measure delay time.
  171. */
  172. static void imx6ul_tsc_set(struct imx6ul_tsc *tsc)
  173. {
  174. u32 basic_setting = 0;
  175. u32 debug_mode2;
  176. u32 start;
  177. basic_setting |= FIELD_PREP(MEASURE_DELAY_TIME_MASK,
  178. tsc->measure_delay_time);
  179. basic_setting |= AUTO_MEASURE;
  180. writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING);
  181. debug_mode2 = FIELD_PREP(DE_GLITCH_MASK, tsc->de_glitch);
  182. writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
  183. writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME);
  184. writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN);
  185. writel(MEASURE_SIG_EN | VALID_SIG_EN,
  186. tsc->tsc_regs + REG_TSC_INT_SIG_EN);
  187. /* start sense detection */
  188. start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  189. start |= START_SENSE;
  190. start &= ~TSC_DISABLE;
  191. writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  192. }
  193. static int imx6ul_tsc_init(struct imx6ul_tsc *tsc)
  194. {
  195. int err;
  196. err = imx6ul_adc_init(tsc);
  197. if (err)
  198. return err;
  199. imx6ul_tsc_channel_config(tsc);
  200. imx6ul_tsc_set(tsc);
  201. return 0;
  202. }
  203. static void imx6ul_tsc_disable(struct imx6ul_tsc *tsc)
  204. {
  205. u32 tsc_flow;
  206. u32 adc_cfg;
  207. /* TSC controller enters to idle status */
  208. tsc_flow = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  209. tsc_flow |= TSC_DISABLE;
  210. writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  211. /* ADC controller enters to stop mode */
  212. adc_cfg = readl(tsc->adc_regs + REG_ADC_HC0);
  213. adc_cfg |= ADC_CONV_DISABLE;
  214. writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0);
  215. }
  216. /* Delay some time (max 2ms), wait the pre-charge done. */
  217. static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc)
  218. {
  219. unsigned long timeout = jiffies + msecs_to_jiffies(2);
  220. u32 state_machine;
  221. u32 debug_mode2;
  222. do {
  223. if (time_after(jiffies, timeout))
  224. return false;
  225. usleep_range(200, 400);
  226. debug_mode2 = readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2);
  227. state_machine = FIELD_GET(STATE_MACHINE_MASK, debug_mode2);
  228. } while (state_machine != DETECT_MODE);
  229. usleep_range(200, 400);
  230. return true;
  231. }
  232. static irqreturn_t tsc_irq_fn(int irq, void *dev_id)
  233. {
  234. struct imx6ul_tsc *tsc = dev_id;
  235. u32 status;
  236. u32 value;
  237. u32 x, y;
  238. u32 start;
  239. status = readl(tsc->tsc_regs + REG_TSC_INT_STATUS);
  240. /* write 1 to clear the bit measure-signal */
  241. writel(MEASURE_SIGNAL | DETECT_SIGNAL,
  242. tsc->tsc_regs + REG_TSC_INT_STATUS);
  243. /* It's a HW self-clean bit. Set this bit and start sense detection */
  244. start = readl(tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  245. start |= START_SENSE;
  246. writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL);
  247. if (status & MEASURE_SIGNAL) {
  248. value = readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE);
  249. x = FIELD_GET(X_VALUE_MASK, value);
  250. y = FIELD_GET(Y_VALUE_MASK, value);
  251. /*
  252. * In detect mode, we can get the xnur gpio value,
  253. * otherwise assume contact is stiull active.
  254. */
  255. if (!tsc_wait_detect_mode(tsc) ||
  256. gpiod_get_value_cansleep(tsc->xnur_gpio)) {
  257. input_report_key(tsc->input, BTN_TOUCH, 1);
  258. input_report_abs(tsc->input, ABS_X, x);
  259. input_report_abs(tsc->input, ABS_Y, y);
  260. } else {
  261. input_report_key(tsc->input, BTN_TOUCH, 0);
  262. }
  263. input_sync(tsc->input);
  264. }
  265. return IRQ_HANDLED;
  266. }
  267. static irqreturn_t adc_irq_fn(int irq, void *dev_id)
  268. {
  269. struct imx6ul_tsc *tsc = dev_id;
  270. u32 coco;
  271. coco = readl(tsc->adc_regs + REG_ADC_HS);
  272. if (coco & 0x01) {
  273. readl(tsc->adc_regs + REG_ADC_R0);
  274. complete(&tsc->completion);
  275. }
  276. return IRQ_HANDLED;
  277. }
  278. static int imx6ul_tsc_start(struct imx6ul_tsc *tsc)
  279. {
  280. int err;
  281. err = clk_prepare_enable(tsc->adc_clk);
  282. if (err) {
  283. dev_err(tsc->dev,
  284. "Could not prepare or enable the adc clock: %d\n",
  285. err);
  286. return err;
  287. }
  288. err = clk_prepare_enable(tsc->tsc_clk);
  289. if (err) {
  290. dev_err(tsc->dev,
  291. "Could not prepare or enable the tsc clock: %d\n",
  292. err);
  293. goto disable_adc_clk;
  294. }
  295. err = imx6ul_tsc_init(tsc);
  296. if (err)
  297. goto disable_tsc_clk;
  298. return 0;
  299. disable_tsc_clk:
  300. clk_disable_unprepare(tsc->tsc_clk);
  301. disable_adc_clk:
  302. clk_disable_unprepare(tsc->adc_clk);
  303. return err;
  304. }
  305. static void imx6ul_tsc_stop(struct imx6ul_tsc *tsc)
  306. {
  307. imx6ul_tsc_disable(tsc);
  308. clk_disable_unprepare(tsc->tsc_clk);
  309. clk_disable_unprepare(tsc->adc_clk);
  310. }
  311. static int imx6ul_tsc_open(struct input_dev *input_dev)
  312. {
  313. struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
  314. return imx6ul_tsc_start(tsc);
  315. }
  316. static void imx6ul_tsc_close(struct input_dev *input_dev)
  317. {
  318. struct imx6ul_tsc *tsc = input_get_drvdata(input_dev);
  319. imx6ul_tsc_stop(tsc);
  320. }
  321. static int imx6ul_tsc_probe(struct platform_device *pdev)
  322. {
  323. struct device_node *np = pdev->dev.of_node;
  324. struct imx6ul_tsc *tsc;
  325. struct input_dev *input_dev;
  326. int err;
  327. int tsc_irq;
  328. int adc_irq;
  329. u32 average_samples;
  330. u32 de_glitch;
  331. tsc = devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL);
  332. if (!tsc)
  333. return -ENOMEM;
  334. input_dev = devm_input_allocate_device(&pdev->dev);
  335. if (!input_dev)
  336. return -ENOMEM;
  337. input_dev->name = "iMX6UL Touchscreen Controller";
  338. input_dev->id.bustype = BUS_HOST;
  339. input_dev->open = imx6ul_tsc_open;
  340. input_dev->close = imx6ul_tsc_close;
  341. input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
  342. input_set_abs_params(input_dev, ABS_X, 0, 0xFFF, 0, 0);
  343. input_set_abs_params(input_dev, ABS_Y, 0, 0xFFF, 0, 0);
  344. input_set_drvdata(input_dev, tsc);
  345. tsc->dev = &pdev->dev;
  346. tsc->input = input_dev;
  347. init_completion(&tsc->completion);
  348. tsc->xnur_gpio = devm_gpiod_get(&pdev->dev, "xnur", GPIOD_IN);
  349. if (IS_ERR(tsc->xnur_gpio)) {
  350. err = PTR_ERR(tsc->xnur_gpio);
  351. dev_err(&pdev->dev,
  352. "failed to request GPIO tsc_X- (xnur): %d\n", err);
  353. return err;
  354. }
  355. tsc->tsc_regs = devm_platform_ioremap_resource(pdev, 0);
  356. if (IS_ERR(tsc->tsc_regs)) {
  357. err = PTR_ERR(tsc->tsc_regs);
  358. dev_err(&pdev->dev, "failed to remap tsc memory: %d\n", err);
  359. return err;
  360. }
  361. tsc->adc_regs = devm_platform_ioremap_resource(pdev, 1);
  362. if (IS_ERR(tsc->adc_regs)) {
  363. err = PTR_ERR(tsc->adc_regs);
  364. dev_err(&pdev->dev, "failed to remap adc memory: %d\n", err);
  365. return err;
  366. }
  367. tsc->tsc_clk = devm_clk_get(&pdev->dev, "tsc");
  368. if (IS_ERR(tsc->tsc_clk)) {
  369. err = PTR_ERR(tsc->tsc_clk);
  370. dev_err(&pdev->dev, "failed getting tsc clock: %d\n", err);
  371. return err;
  372. }
  373. tsc->adc_clk = devm_clk_get(&pdev->dev, "adc");
  374. if (IS_ERR(tsc->adc_clk)) {
  375. err = PTR_ERR(tsc->adc_clk);
  376. dev_err(&pdev->dev, "failed getting adc clock: %d\n", err);
  377. return err;
  378. }
  379. tsc_irq = platform_get_irq(pdev, 0);
  380. if (tsc_irq < 0)
  381. return tsc_irq;
  382. adc_irq = platform_get_irq(pdev, 1);
  383. if (adc_irq < 0)
  384. return adc_irq;
  385. err = devm_request_threaded_irq(tsc->dev, tsc_irq,
  386. NULL, tsc_irq_fn, IRQF_ONESHOT,
  387. dev_name(&pdev->dev), tsc);
  388. if (err) {
  389. dev_err(&pdev->dev,
  390. "failed requesting tsc irq %d: %d\n",
  391. tsc_irq, err);
  392. return err;
  393. }
  394. err = devm_request_irq(tsc->dev, adc_irq, adc_irq_fn, 0,
  395. dev_name(&pdev->dev), tsc);
  396. if (err) {
  397. dev_err(&pdev->dev,
  398. "failed requesting adc irq %d: %d\n",
  399. adc_irq, err);
  400. return err;
  401. }
  402. err = of_property_read_u32(np, "measure-delay-time",
  403. &tsc->measure_delay_time);
  404. if (err)
  405. tsc->measure_delay_time = 0xffff;
  406. err = of_property_read_u32(np, "pre-charge-time",
  407. &tsc->pre_charge_time);
  408. if (err)
  409. tsc->pre_charge_time = 0xfff;
  410. err = of_property_read_u32(np, "touchscreen-average-samples",
  411. &average_samples);
  412. if (err)
  413. average_samples = 1;
  414. switch (average_samples) {
  415. case 1:
  416. tsc->average_enable = false;
  417. tsc->average_select = 0; /* value unused; initialize anyway */
  418. break;
  419. case 4:
  420. case 8:
  421. case 16:
  422. case 32:
  423. tsc->average_enable = true;
  424. tsc->average_select = ilog2(average_samples) - 2;
  425. break;
  426. default:
  427. dev_err(&pdev->dev,
  428. "touchscreen-average-samples (%u) must be 1, 4, 8, 16 or 32\n",
  429. average_samples);
  430. return -EINVAL;
  431. }
  432. err = of_property_read_u32(np, "debounce-delay-us", &de_glitch);
  433. if (err) {
  434. tsc->de_glitch = DE_GLITCH_DEF;
  435. } else {
  436. u64 cycles;
  437. unsigned long rate = clk_get_rate(tsc->tsc_clk);
  438. cycles = DIV64_U64_ROUND_UP((u64)de_glitch * rate, USEC_PER_SEC);
  439. if (cycles <= 0x3ff)
  440. tsc->de_glitch = 3;
  441. else if (cycles <= 0x7ff)
  442. tsc->de_glitch = 2;
  443. else if (cycles <= 0xfff)
  444. tsc->de_glitch = 1;
  445. else
  446. tsc->de_glitch = 0;
  447. }
  448. err = input_register_device(tsc->input);
  449. if (err) {
  450. dev_err(&pdev->dev,
  451. "failed to register input device: %d\n", err);
  452. return err;
  453. }
  454. platform_set_drvdata(pdev, tsc);
  455. return 0;
  456. }
  457. static int imx6ul_tsc_suspend(struct device *dev)
  458. {
  459. struct platform_device *pdev = to_platform_device(dev);
  460. struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
  461. struct input_dev *input_dev = tsc->input;
  462. mutex_lock(&input_dev->mutex);
  463. if (input_device_enabled(input_dev))
  464. imx6ul_tsc_stop(tsc);
  465. mutex_unlock(&input_dev->mutex);
  466. return 0;
  467. }
  468. static int imx6ul_tsc_resume(struct device *dev)
  469. {
  470. struct platform_device *pdev = to_platform_device(dev);
  471. struct imx6ul_tsc *tsc = platform_get_drvdata(pdev);
  472. struct input_dev *input_dev = tsc->input;
  473. int retval = 0;
  474. mutex_lock(&input_dev->mutex);
  475. if (input_device_enabled(input_dev))
  476. retval = imx6ul_tsc_start(tsc);
  477. mutex_unlock(&input_dev->mutex);
  478. return retval;
  479. }
  480. static DEFINE_SIMPLE_DEV_PM_OPS(imx6ul_tsc_pm_ops,
  481. imx6ul_tsc_suspend, imx6ul_tsc_resume);
  482. static const struct of_device_id imx6ul_tsc_match[] = {
  483. { .compatible = "fsl,imx6ul-tsc", },
  484. { /* sentinel */ }
  485. };
  486. MODULE_DEVICE_TABLE(of, imx6ul_tsc_match);
  487. static struct platform_driver imx6ul_tsc_driver = {
  488. .driver = {
  489. .name = "imx6ul-tsc",
  490. .of_match_table = imx6ul_tsc_match,
  491. .pm = pm_sleep_ptr(&imx6ul_tsc_pm_ops),
  492. },
  493. .probe = imx6ul_tsc_probe,
  494. };
  495. module_platform_driver(imx6ul_tsc_driver);
  496. MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
  497. MODULE_DESCRIPTION("Freescale i.MX6UL Touchscreen controller driver");
  498. MODULE_LICENSE("GPL v2");