hideep.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012-2017 Hideep, Inc.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/of.h>
  7. #include <linux/firmware.h>
  8. #include <linux/delay.h>
  9. #include <linux/gpio/consumer.h>
  10. #include <linux/i2c.h>
  11. #include <linux/acpi.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/regmap.h>
  14. #include <linux/sysfs.h>
  15. #include <linux/input.h>
  16. #include <linux/input/mt.h>
  17. #include <linux/input/touchscreen.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/unaligned.h>
  20. #define HIDEEP_TS_NAME "HiDeep Touchscreen"
  21. #define HIDEEP_I2C_NAME "hideep_ts"
  22. #define HIDEEP_MT_MAX 10
  23. #define HIDEEP_KEY_MAX 3
  24. /* count(2) + touch data(100) + key data(6) */
  25. #define HIDEEP_MAX_EVENT 108UL
  26. #define HIDEEP_TOUCH_EVENT_INDEX 2
  27. #define HIDEEP_KEY_EVENT_INDEX 102
  28. /* Touch & key event */
  29. #define HIDEEP_EVENT_ADDR 0x240
  30. /* command list */
  31. #define HIDEEP_WORK_MODE 0x081e
  32. #define HIDEEP_RESET_CMD 0x9800
  33. /* event bit */
  34. #define HIDEEP_MT_RELEASED BIT(4)
  35. #define HIDEEP_KEY_PRESSED BIT(7)
  36. #define HIDEEP_KEY_FIRST_PRESSED BIT(8)
  37. #define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \
  38. HIDEEP_KEY_FIRST_PRESSED)
  39. #define HIDEEP_KEY_IDX_MASK 0x0f
  40. /* For NVM */
  41. #define HIDEEP_YRAM_BASE 0x40000000
  42. #define HIDEEP_PERIPHERAL_BASE 0x50000000
  43. #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000)
  44. #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000)
  45. #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000)
  46. #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000)
  47. #define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004)
  48. #define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008)
  49. #define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C)
  50. #define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010)
  51. #define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014)
  52. #define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018)
  53. #define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020)
  54. #define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4)
  55. #define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000)
  56. #define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004)
  57. #define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008)
  58. #define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C)
  59. #define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010)
  60. #define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000)
  61. #define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008)
  62. #define HIDEEP_PERASE 0x00040000
  63. #define HIDEEP_WRONLY 0x00100000
  64. #define HIDEEP_NVM_MASK_OFS 0x0000000C
  65. #define HIDEEP_NVM_DEFAULT_PAGE 0
  66. #define HIDEEP_NVM_SFR_WPAGE 1
  67. #define HIDEEP_NVM_SFR_RPAGE 2
  68. #define HIDEEP_PIO_SIG 0x00400000
  69. #define HIDEEP_PROT_MODE 0x03400000
  70. #define HIDEEP_NVM_PAGE_SIZE 128
  71. #define HIDEEP_DWZ_INFO 0x000002C0
  72. struct hideep_event {
  73. __le16 x;
  74. __le16 y;
  75. __le16 z;
  76. u8 w;
  77. u8 flag;
  78. u8 type;
  79. u8 index;
  80. };
  81. struct dwz_info {
  82. __be32 code_start;
  83. u8 code_crc[12];
  84. __be32 c_code_start;
  85. __be16 gen_ver;
  86. __be16 c_code_len;
  87. __be32 vr_start;
  88. __be16 rsv0;
  89. __be16 vr_len;
  90. __be32 ft_start;
  91. __be16 vr_version;
  92. __be16 ft_len;
  93. __be16 core_ver;
  94. __be16 boot_ver;
  95. __be16 release_ver;
  96. __be16 custom_ver;
  97. u8 factory_id;
  98. u8 panel_type;
  99. u8 model_name[6];
  100. __be16 extra_option;
  101. __be16 product_code;
  102. __be16 vendor_id;
  103. __be16 product_id;
  104. };
  105. struct pgm_packet {
  106. struct {
  107. u8 unused[3];
  108. u8 len;
  109. __be32 addr;
  110. } header;
  111. __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
  112. };
  113. #define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet)
  114. struct hideep_ts {
  115. struct i2c_client *client;
  116. struct input_dev *input_dev;
  117. struct regmap *reg;
  118. struct touchscreen_properties prop;
  119. struct gpio_desc *reset_gpio;
  120. struct regulator *vcc_vdd;
  121. struct regulator *vcc_vid;
  122. struct mutex dev_mutex;
  123. u32 tch_count;
  124. u32 lpm_count;
  125. /*
  126. * Data buffer to read packet from the device (contacts and key
  127. * states). We align it on double-word boundary to keep word-sized
  128. * fields in contact data and double-word-sized fields in program
  129. * packet aligned.
  130. */
  131. u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
  132. int key_num;
  133. u32 key_codes[HIDEEP_KEY_MAX];
  134. struct dwz_info dwz_info;
  135. unsigned int fw_size;
  136. u32 nvm_mask;
  137. };
  138. static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
  139. const __be32 *data, size_t count)
  140. {
  141. struct pgm_packet *packet = (void *)ts->xfer_buf;
  142. size_t len = count * sizeof(*data);
  143. struct i2c_msg msg = {
  144. .addr = ts->client->addr,
  145. .len = len + sizeof(packet->header.len) +
  146. sizeof(packet->header.addr),
  147. .buf = &packet->header.len,
  148. };
  149. int ret;
  150. if (len > HIDEEP_NVM_PAGE_SIZE)
  151. return -EINVAL;
  152. packet->header.len = 0x80 | (count - 1);
  153. packet->header.addr = cpu_to_be32(addr);
  154. memcpy(packet->payload, data, len);
  155. ret = i2c_transfer(ts->client->adapter, &msg, 1);
  156. if (ret != 1)
  157. return ret < 0 ? ret : -EIO;
  158. return 0;
  159. }
  160. static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
  161. __be32 *data, size_t count)
  162. {
  163. struct pgm_packet *packet = (void *)ts->xfer_buf;
  164. size_t len = count * sizeof(*data);
  165. struct i2c_msg msg[] = {
  166. {
  167. .addr = ts->client->addr,
  168. .len = sizeof(packet->header.len) +
  169. sizeof(packet->header.addr),
  170. .buf = &packet->header.len,
  171. },
  172. {
  173. .addr = ts->client->addr,
  174. .flags = I2C_M_RD,
  175. .len = len,
  176. .buf = (u8 *)data,
  177. },
  178. };
  179. int ret;
  180. if (len > HIDEEP_NVM_PAGE_SIZE)
  181. return -EINVAL;
  182. packet->header.len = count - 1;
  183. packet->header.addr = cpu_to_be32(addr);
  184. ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
  185. if (ret != ARRAY_SIZE(msg))
  186. return ret < 0 ? ret : -EIO;
  187. return 0;
  188. }
  189. static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
  190. {
  191. __be32 data;
  192. int error;
  193. error = hideep_pgm_r_mem(ts, addr, &data, 1);
  194. if (error) {
  195. dev_err(&ts->client->dev,
  196. "read of register %#08x failed: %d\n",
  197. addr, error);
  198. return error;
  199. }
  200. *val = be32_to_cpu(data);
  201. return 0;
  202. }
  203. static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
  204. {
  205. __be32 data = cpu_to_be32(val);
  206. int error;
  207. error = hideep_pgm_w_mem(ts, addr, &data, 1);
  208. if (error) {
  209. dev_err(&ts->client->dev,
  210. "write to register %#08x (%#08x) failed: %d\n",
  211. addr, val, error);
  212. return error;
  213. }
  214. return 0;
  215. }
  216. #define SW_RESET_IN_PGM(clk) \
  217. { \
  218. __be32 data = cpu_to_be32(0x01); \
  219. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
  220. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \
  221. /* \
  222. * The first write may already cause a reset, use a raw \
  223. * write for the second write to avoid error logging. \
  224. */ \
  225. hideep_pgm_w_mem(ts, HIDEEP_SYSCON_WDT_CON, &data, 1); \
  226. }
  227. #define SET_FLASH_PIO(ce) \
  228. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \
  229. 0x01 | ((ce) << 1))
  230. #define SET_PIO_SIG(x, y) \
  231. hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
  232. #define SET_FLASH_HWCONTROL() \
  233. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
  234. #define NVM_W_SFR(x, y) \
  235. { \
  236. SET_FLASH_PIO(1); \
  237. SET_PIO_SIG(x, y); \
  238. SET_FLASH_PIO(0); \
  239. }
  240. static void hideep_pgm_set(struct hideep_ts *ts)
  241. {
  242. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
  243. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
  244. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
  245. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
  246. hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
  247. hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
  248. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
  249. }
  250. static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
  251. {
  252. u16 p1 = 0xAF39;
  253. u16 p2 = 0xDF9D;
  254. int error;
  255. error = regmap_bulk_write(ts->reg, p1, &p2, 1);
  256. if (error) {
  257. dev_err(&ts->client->dev,
  258. "%s: regmap_bulk_write() failed with %d\n",
  259. __func__, error);
  260. return error;
  261. }
  262. usleep_range(1000, 1100);
  263. /* flush invalid Tx load register */
  264. error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
  265. if (error)
  266. return error;
  267. error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
  268. if (error)
  269. return error;
  270. return 0;
  271. }
  272. static int hideep_enter_pgm(struct hideep_ts *ts)
  273. {
  274. int retry_count = 10;
  275. u32 pattern;
  276. int error;
  277. while (retry_count--) {
  278. error = hideep_pgm_get_pattern(ts, &pattern);
  279. if (error) {
  280. dev_err(&ts->client->dev,
  281. "hideep_pgm_get_pattern failed: %d\n", error);
  282. } else if (pattern != 0x39AF9DDF) {
  283. dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
  284. __func__, pattern);
  285. } else {
  286. dev_dbg(&ts->client->dev, "found magic code");
  287. hideep_pgm_set(ts);
  288. usleep_range(1000, 1100);
  289. return 0;
  290. }
  291. }
  292. dev_err(&ts->client->dev, "failed to enter pgm mode\n");
  293. SW_RESET_IN_PGM(1000);
  294. return -EIO;
  295. }
  296. static int hideep_nvm_unlock(struct hideep_ts *ts)
  297. {
  298. u32 unmask_code;
  299. int error;
  300. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
  301. error = hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
  302. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  303. if (error)
  304. return error;
  305. /* make it unprotected code */
  306. unmask_code &= ~HIDEEP_PROT_MODE;
  307. /* compare unmask code */
  308. if (unmask_code != ts->nvm_mask)
  309. dev_warn(&ts->client->dev,
  310. "read mask code different %#08x vs %#08x",
  311. unmask_code, ts->nvm_mask);
  312. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
  313. SET_FLASH_PIO(0);
  314. NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
  315. SET_FLASH_HWCONTROL();
  316. hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
  317. return 0;
  318. }
  319. static int hideep_check_status(struct hideep_ts *ts)
  320. {
  321. int time_out = 100;
  322. int status;
  323. int error;
  324. while (time_out--) {
  325. error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
  326. if (!error && status)
  327. return 0;
  328. usleep_range(1000, 1100);
  329. }
  330. return -ETIMEDOUT;
  331. }
  332. static int hideep_program_page(struct hideep_ts *ts, u32 addr,
  333. const __be32 *ucode, size_t xfer_count)
  334. {
  335. u32 val;
  336. int error;
  337. error = hideep_check_status(ts);
  338. if (error)
  339. return -EBUSY;
  340. addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
  341. SET_FLASH_PIO(0);
  342. SET_FLASH_PIO(1);
  343. /* erase page */
  344. SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
  345. SET_FLASH_PIO(0);
  346. error = hideep_check_status(ts);
  347. if (error)
  348. return -EBUSY;
  349. /* write page */
  350. SET_FLASH_PIO(1);
  351. val = be32_to_cpu(ucode[0]);
  352. SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
  353. hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
  354. ucode, xfer_count);
  355. val = be32_to_cpu(ucode[xfer_count - 1]);
  356. SET_PIO_SIG(124, val);
  357. SET_FLASH_PIO(0);
  358. usleep_range(1000, 1100);
  359. error = hideep_check_status(ts);
  360. if (error)
  361. return -EBUSY;
  362. SET_FLASH_HWCONTROL();
  363. return 0;
  364. }
  365. static int hideep_program_nvm(struct hideep_ts *ts,
  366. const __be32 *ucode, size_t ucode_len)
  367. {
  368. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  369. __be32 *current_ucode = packet_r->payload;
  370. size_t xfer_len;
  371. size_t xfer_count;
  372. u32 addr = 0;
  373. int error;
  374. error = hideep_nvm_unlock(ts);
  375. if (error)
  376. return error;
  377. while (ucode_len > 0) {
  378. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  379. xfer_count = xfer_len / sizeof(*ucode);
  380. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  381. current_ucode, xfer_count);
  382. if (error) {
  383. dev_err(&ts->client->dev,
  384. "%s: failed to read page at offset %#08x: %d\n",
  385. __func__, addr, error);
  386. return error;
  387. }
  388. /* See if the page needs updating */
  389. if (memcmp(ucode, current_ucode, xfer_len)) {
  390. error = hideep_program_page(ts, addr,
  391. ucode, xfer_count);
  392. if (error) {
  393. dev_err(&ts->client->dev,
  394. "%s: iwrite failure @%#08x: %d\n",
  395. __func__, addr, error);
  396. return error;
  397. }
  398. usleep_range(1000, 1100);
  399. }
  400. ucode += xfer_count;
  401. addr += xfer_len;
  402. ucode_len -= xfer_len;
  403. }
  404. return 0;
  405. }
  406. static int hideep_verify_nvm(struct hideep_ts *ts,
  407. const __be32 *ucode, size_t ucode_len)
  408. {
  409. struct pgm_packet *packet_r = (void *)ts->xfer_buf;
  410. __be32 *current_ucode = packet_r->payload;
  411. size_t xfer_len;
  412. size_t xfer_count;
  413. u32 addr = 0;
  414. int i;
  415. int error;
  416. while (ucode_len > 0) {
  417. xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
  418. xfer_count = xfer_len / sizeof(*ucode);
  419. error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
  420. current_ucode, xfer_count);
  421. if (error) {
  422. dev_err(&ts->client->dev,
  423. "%s: failed to read page at offset %#08x: %d\n",
  424. __func__, addr, error);
  425. return error;
  426. }
  427. if (memcmp(ucode, current_ucode, xfer_len)) {
  428. const u8 *ucode_bytes = (const u8 *)ucode;
  429. const u8 *current_bytes = (const u8 *)current_ucode;
  430. for (i = 0; i < xfer_len; i++)
  431. if (ucode_bytes[i] != current_bytes[i])
  432. dev_err(&ts->client->dev,
  433. "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
  434. __func__, addr + i,
  435. ucode_bytes[i],
  436. current_bytes[i]);
  437. return -EIO;
  438. }
  439. ucode += xfer_count;
  440. addr += xfer_len;
  441. ucode_len -= xfer_len;
  442. }
  443. return 0;
  444. }
  445. static int hideep_load_dwz(struct hideep_ts *ts)
  446. {
  447. u16 product_code;
  448. int error;
  449. error = hideep_enter_pgm(ts);
  450. if (error)
  451. return error;
  452. msleep(50);
  453. error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
  454. (void *)&ts->dwz_info,
  455. sizeof(ts->dwz_info) / sizeof(__be32));
  456. SW_RESET_IN_PGM(10);
  457. msleep(50);
  458. if (error) {
  459. dev_err(&ts->client->dev,
  460. "failed to fetch DWZ data: %d\n", error);
  461. return error;
  462. }
  463. product_code = be16_to_cpu(ts->dwz_info.product_code);
  464. switch (product_code & 0xF0) {
  465. case 0x40:
  466. dev_dbg(&ts->client->dev, "used crimson IC");
  467. ts->fw_size = 1024 * 48;
  468. ts->nvm_mask = 0x00310000;
  469. break;
  470. case 0x60:
  471. dev_dbg(&ts->client->dev, "used lime IC");
  472. ts->fw_size = 1024 * 64;
  473. ts->nvm_mask = 0x0030027B;
  474. break;
  475. default:
  476. dev_err(&ts->client->dev, "product code is wrong: %#04x",
  477. product_code);
  478. return -EINVAL;
  479. }
  480. dev_dbg(&ts->client->dev, "firmware release version: %#04x",
  481. be16_to_cpu(ts->dwz_info.release_ver));
  482. return 0;
  483. }
  484. static int hideep_flash_firmware(struct hideep_ts *ts,
  485. const __be32 *ucode, size_t ucode_len)
  486. {
  487. int retry_cnt = 3;
  488. int error;
  489. while (retry_cnt--) {
  490. error = hideep_program_nvm(ts, ucode, ucode_len);
  491. if (!error) {
  492. error = hideep_verify_nvm(ts, ucode, ucode_len);
  493. if (!error)
  494. return 0;
  495. }
  496. }
  497. return error;
  498. }
  499. static int hideep_update_firmware(struct hideep_ts *ts,
  500. const __be32 *ucode, size_t ucode_len)
  501. {
  502. int error, error2;
  503. dev_dbg(&ts->client->dev, "starting firmware update");
  504. /* enter program mode */
  505. error = hideep_enter_pgm(ts);
  506. if (error)
  507. return error;
  508. error = hideep_flash_firmware(ts, ucode, ucode_len);
  509. if (error)
  510. dev_err(&ts->client->dev,
  511. "firmware update failed: %d\n", error);
  512. else
  513. dev_dbg(&ts->client->dev, "firmware updated successfully\n");
  514. SW_RESET_IN_PGM(1000);
  515. error2 = hideep_load_dwz(ts);
  516. if (error2)
  517. dev_err(&ts->client->dev,
  518. "failed to load dwz after firmware update: %d\n",
  519. error2);
  520. return error ?: error2;
  521. }
  522. static int hideep_power_on(struct hideep_ts *ts)
  523. {
  524. int error = 0;
  525. error = regulator_enable(ts->vcc_vdd);
  526. if (error)
  527. dev_err(&ts->client->dev,
  528. "failed to enable 'vdd' regulator: %d", error);
  529. usleep_range(999, 1000);
  530. error = regulator_enable(ts->vcc_vid);
  531. if (error)
  532. dev_err(&ts->client->dev,
  533. "failed to enable 'vcc_vid' regulator: %d",
  534. error);
  535. msleep(30);
  536. if (ts->reset_gpio) {
  537. gpiod_set_value_cansleep(ts->reset_gpio, 0);
  538. } else {
  539. error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
  540. if (error)
  541. dev_err(&ts->client->dev,
  542. "failed to send 'reset' command: %d\n", error);
  543. }
  544. msleep(50);
  545. return error;
  546. }
  547. static void hideep_power_off(void *data)
  548. {
  549. struct hideep_ts *ts = data;
  550. if (ts->reset_gpio)
  551. gpiod_set_value(ts->reset_gpio, 1);
  552. regulator_disable(ts->vcc_vid);
  553. regulator_disable(ts->vcc_vdd);
  554. }
  555. #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
  556. static void hideep_report_slot(struct input_dev *input,
  557. const struct hideep_event *event)
  558. {
  559. input_mt_slot(input, event->index & 0x0f);
  560. input_mt_report_slot_state(input,
  561. __GET_MT_TOOL_TYPE(event->type),
  562. !(event->flag & HIDEEP_MT_RELEASED));
  563. if (!(event->flag & HIDEEP_MT_RELEASED)) {
  564. input_report_abs(input, ABS_MT_POSITION_X,
  565. le16_to_cpup(&event->x));
  566. input_report_abs(input, ABS_MT_POSITION_Y,
  567. le16_to_cpup(&event->y));
  568. input_report_abs(input, ABS_MT_PRESSURE,
  569. le16_to_cpup(&event->z));
  570. input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
  571. }
  572. }
  573. static void hideep_parse_and_report(struct hideep_ts *ts)
  574. {
  575. const struct hideep_event *events =
  576. (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
  577. const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
  578. int touch_count = ts->xfer_buf[0];
  579. int key_count = ts->xfer_buf[1] & 0x0f;
  580. int lpm_count = ts->xfer_buf[1] & 0xf0;
  581. int i;
  582. /* get touch event count */
  583. dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
  584. touch_count, key_count, lpm_count);
  585. touch_count = min(touch_count, HIDEEP_MT_MAX);
  586. for (i = 0; i < touch_count; i++)
  587. hideep_report_slot(ts->input_dev, events + i);
  588. key_count = min(key_count, HIDEEP_KEY_MAX);
  589. for (i = 0; i < key_count; i++) {
  590. u8 key_data = keys[i * 2];
  591. input_report_key(ts->input_dev,
  592. ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
  593. key_data & HIDEEP_KEY_PRESSED_MASK);
  594. }
  595. input_mt_sync_frame(ts->input_dev);
  596. input_sync(ts->input_dev);
  597. }
  598. static irqreturn_t hideep_irq(int irq, void *handle)
  599. {
  600. struct hideep_ts *ts = handle;
  601. int error;
  602. BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
  603. error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
  604. ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
  605. if (error) {
  606. dev_err(&ts->client->dev, "failed to read events: %d\n", error);
  607. goto out;
  608. }
  609. hideep_parse_and_report(ts);
  610. out:
  611. return IRQ_HANDLED;
  612. }
  613. static int hideep_get_axis_info(struct hideep_ts *ts)
  614. {
  615. __le16 val[2];
  616. int error;
  617. error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
  618. if (error)
  619. return error;
  620. ts->prop.max_x = le16_to_cpup(val);
  621. ts->prop.max_y = le16_to_cpup(val + 1);
  622. dev_dbg(&ts->client->dev, "X: %d, Y: %d",
  623. ts->prop.max_x, ts->prop.max_y);
  624. return 0;
  625. }
  626. static int hideep_init_input(struct hideep_ts *ts)
  627. {
  628. struct device *dev = &ts->client->dev;
  629. int i;
  630. int error;
  631. ts->input_dev = devm_input_allocate_device(dev);
  632. if (!ts->input_dev) {
  633. dev_err(dev, "failed to allocate input device\n");
  634. return -ENOMEM;
  635. }
  636. ts->input_dev->name = HIDEEP_TS_NAME;
  637. ts->input_dev->id.bustype = BUS_I2C;
  638. input_set_drvdata(ts->input_dev, ts);
  639. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
  640. input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
  641. input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
  642. input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
  643. input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
  644. 0, MT_TOOL_MAX, 0, 0);
  645. touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
  646. if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
  647. error = hideep_get_axis_info(ts);
  648. if (error)
  649. return error;
  650. }
  651. error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
  652. INPUT_MT_DIRECT);
  653. if (error)
  654. return error;
  655. ts->key_num = device_property_count_u32(dev, "linux,keycodes");
  656. if (ts->key_num > HIDEEP_KEY_MAX) {
  657. dev_err(dev, "too many keys defined: %d\n",
  658. ts->key_num);
  659. return -EINVAL;
  660. }
  661. if (ts->key_num <= 0) {
  662. dev_dbg(dev,
  663. "missing or malformed 'linux,keycodes' property\n");
  664. } else {
  665. error = device_property_read_u32_array(dev, "linux,keycodes",
  666. ts->key_codes,
  667. ts->key_num);
  668. if (error) {
  669. dev_dbg(dev, "failed to read keymap: %d", error);
  670. return error;
  671. }
  672. if (ts->key_num) {
  673. ts->input_dev->keycode = ts->key_codes;
  674. ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
  675. ts->input_dev->keycodemax = ts->key_num;
  676. for (i = 0; i < ts->key_num; i++)
  677. input_set_capability(ts->input_dev, EV_KEY,
  678. ts->key_codes[i]);
  679. }
  680. }
  681. error = input_register_device(ts->input_dev);
  682. if (error) {
  683. dev_err(dev, "failed to register input device: %d", error);
  684. return error;
  685. }
  686. return 0;
  687. }
  688. static ssize_t hideep_update_fw(struct device *dev,
  689. struct device_attribute *attr,
  690. const char *buf, size_t count)
  691. {
  692. struct i2c_client *client = to_i2c_client(dev);
  693. struct hideep_ts *ts = i2c_get_clientdata(client);
  694. const struct firmware *fw_entry;
  695. char *fw_name;
  696. int mode;
  697. int error;
  698. error = kstrtoint(buf, 0, &mode);
  699. if (error)
  700. return error;
  701. fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
  702. be16_to_cpu(ts->dwz_info.product_id));
  703. if (!fw_name)
  704. return -ENOMEM;
  705. error = request_firmware(&fw_entry, fw_name, dev);
  706. if (error) {
  707. dev_err(dev, "failed to request firmware %s: %d",
  708. fw_name, error);
  709. goto out_free_fw_name;
  710. }
  711. if (fw_entry->size % sizeof(__be32)) {
  712. dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
  713. error = -EINVAL;
  714. goto out_release_fw;
  715. }
  716. if (fw_entry->size > ts->fw_size) {
  717. dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
  718. fw_entry->size, ts->fw_size);
  719. error = -EFBIG;
  720. goto out_release_fw;
  721. }
  722. mutex_lock(&ts->dev_mutex);
  723. disable_irq(client->irq);
  724. error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
  725. fw_entry->size);
  726. enable_irq(client->irq);
  727. mutex_unlock(&ts->dev_mutex);
  728. out_release_fw:
  729. release_firmware(fw_entry);
  730. out_free_fw_name:
  731. kfree(fw_name);
  732. return error ?: count;
  733. }
  734. static ssize_t hideep_fw_version_show(struct device *dev,
  735. struct device_attribute *attr, char *buf)
  736. {
  737. struct i2c_client *client = to_i2c_client(dev);
  738. struct hideep_ts *ts = i2c_get_clientdata(client);
  739. ssize_t len;
  740. mutex_lock(&ts->dev_mutex);
  741. len = sysfs_emit(buf, "%04x\n", be16_to_cpu(ts->dwz_info.release_ver));
  742. mutex_unlock(&ts->dev_mutex);
  743. return len;
  744. }
  745. static ssize_t hideep_product_id_show(struct device *dev,
  746. struct device_attribute *attr, char *buf)
  747. {
  748. struct i2c_client *client = to_i2c_client(dev);
  749. struct hideep_ts *ts = i2c_get_clientdata(client);
  750. ssize_t len;
  751. mutex_lock(&ts->dev_mutex);
  752. len = sysfs_emit(buf, "%04x\n", be16_to_cpu(ts->dwz_info.product_id));
  753. mutex_unlock(&ts->dev_mutex);
  754. return len;
  755. }
  756. static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
  757. static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
  758. static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
  759. static struct attribute *hideep_ts_attrs[] = {
  760. &dev_attr_version.attr,
  761. &dev_attr_product_id.attr,
  762. &dev_attr_update_fw.attr,
  763. NULL,
  764. };
  765. ATTRIBUTE_GROUPS(hideep_ts);
  766. static void hideep_set_work_mode(struct hideep_ts *ts)
  767. {
  768. /*
  769. * Reset touch report format to the native HiDeep 20 protocol if requested.
  770. * This is necessary to make touchscreens which come up in I2C-HID mode
  771. * work with this driver.
  772. *
  773. * Note this is a kernel internal device-property set by x86 platform code,
  774. * this MUST not be used in devicetree files without first adding it to
  775. * the DT bindings.
  776. */
  777. if (device_property_read_bool(&ts->client->dev, "hideep,force-native-protocol"))
  778. regmap_write(ts->reg, HIDEEP_WORK_MODE, 0x00);
  779. }
  780. static int hideep_suspend(struct device *dev)
  781. {
  782. struct i2c_client *client = to_i2c_client(dev);
  783. struct hideep_ts *ts = i2c_get_clientdata(client);
  784. disable_irq(client->irq);
  785. hideep_power_off(ts);
  786. return 0;
  787. }
  788. static int hideep_resume(struct device *dev)
  789. {
  790. struct i2c_client *client = to_i2c_client(dev);
  791. struct hideep_ts *ts = i2c_get_clientdata(client);
  792. int error;
  793. error = hideep_power_on(ts);
  794. if (error) {
  795. dev_err(&client->dev, "power on failed");
  796. return error;
  797. }
  798. hideep_set_work_mode(ts);
  799. enable_irq(client->irq);
  800. return 0;
  801. }
  802. static DEFINE_SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
  803. static const struct regmap_config hideep_regmap_config = {
  804. .reg_bits = 16,
  805. .reg_format_endian = REGMAP_ENDIAN_LITTLE,
  806. .val_bits = 16,
  807. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  808. .max_register = 0xffff,
  809. };
  810. static int hideep_probe(struct i2c_client *client)
  811. {
  812. struct hideep_ts *ts;
  813. int error;
  814. /* check i2c bus */
  815. if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
  816. dev_err(&client->dev, "check i2c device error");
  817. return -ENODEV;
  818. }
  819. if (client->irq <= 0) {
  820. dev_err(&client->dev, "missing irq: %d\n", client->irq);
  821. return -EINVAL;
  822. }
  823. ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
  824. if (!ts)
  825. return -ENOMEM;
  826. ts->client = client;
  827. i2c_set_clientdata(client, ts);
  828. mutex_init(&ts->dev_mutex);
  829. ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
  830. if (IS_ERR(ts->reg)) {
  831. error = PTR_ERR(ts->reg);
  832. dev_err(&client->dev,
  833. "failed to initialize regmap: %d\n", error);
  834. return error;
  835. }
  836. ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
  837. if (IS_ERR(ts->vcc_vdd))
  838. return PTR_ERR(ts->vcc_vdd);
  839. ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
  840. if (IS_ERR(ts->vcc_vid))
  841. return PTR_ERR(ts->vcc_vid);
  842. ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
  843. "reset", GPIOD_OUT_HIGH);
  844. if (IS_ERR(ts->reset_gpio))
  845. return PTR_ERR(ts->reset_gpio);
  846. error = hideep_power_on(ts);
  847. if (error) {
  848. dev_err(&client->dev, "power on failed: %d\n", error);
  849. return error;
  850. }
  851. error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
  852. if (error)
  853. return error;
  854. error = hideep_load_dwz(ts);
  855. if (error) {
  856. dev_err(&client->dev, "failed to load dwz: %d", error);
  857. return error;
  858. }
  859. hideep_set_work_mode(ts);
  860. error = hideep_init_input(ts);
  861. if (error)
  862. return error;
  863. error = devm_request_threaded_irq(&client->dev, client->irq,
  864. NULL, hideep_irq, IRQF_ONESHOT,
  865. client->name, ts);
  866. if (error) {
  867. dev_err(&client->dev, "failed to request irq %d: %d\n",
  868. client->irq, error);
  869. return error;
  870. }
  871. return 0;
  872. }
  873. static const struct i2c_device_id hideep_i2c_id[] = {
  874. { HIDEEP_I2C_NAME },
  875. { }
  876. };
  877. MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
  878. #ifdef CONFIG_ACPI
  879. static const struct acpi_device_id hideep_acpi_id[] = {
  880. { "HIDP0001", 0 },
  881. { }
  882. };
  883. MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
  884. #endif
  885. #ifdef CONFIG_OF
  886. static const struct of_device_id hideep_match_table[] = {
  887. { .compatible = "hideep,hideep-ts" },
  888. { }
  889. };
  890. MODULE_DEVICE_TABLE(of, hideep_match_table);
  891. #endif
  892. static struct i2c_driver hideep_driver = {
  893. .driver = {
  894. .name = HIDEEP_I2C_NAME,
  895. .dev_groups = hideep_ts_groups,
  896. .of_match_table = of_match_ptr(hideep_match_table),
  897. .acpi_match_table = ACPI_PTR(hideep_acpi_id),
  898. .pm = pm_sleep_ptr(&hideep_pm_ops),
  899. },
  900. .id_table = hideep_i2c_id,
  901. .probe = hideep_probe,
  902. };
  903. module_i2c_driver(hideep_driver);
  904. MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
  905. MODULE_AUTHOR("anthony.kim@hideep.com");
  906. MODULE_LICENSE("GPL v2");