pm8941-pwrkey.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2010-2011, 2020-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2014, Sony Mobile Communications Inc.
  5. */
  6. #include <linux/delay.h>
  7. #include <linux/errno.h>
  8. #include <linux/input.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/kernel.h>
  11. #include <linux/ktime.h>
  12. #include <linux/log2.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/reboot.h>
  18. #include <linux/regmap.h>
  19. #define PON_REV2 0x01
  20. #define PON_SUBTYPE 0x05
  21. #define PON_SUBTYPE_PRIMARY 0x01
  22. #define PON_SUBTYPE_SECONDARY 0x02
  23. #define PON_SUBTYPE_1REG 0x03
  24. #define PON_SUBTYPE_GEN2_PRIMARY 0x04
  25. #define PON_SUBTYPE_GEN2_SECONDARY 0x05
  26. #define PON_SUBTYPE_GEN3_PBS 0x08
  27. #define PON_SUBTYPE_GEN3_HLOS 0x09
  28. #define PON_RT_STS 0x10
  29. #define PON_KPDPWR_N_SET BIT(0)
  30. #define PON_RESIN_N_SET BIT(1)
  31. #define PON_GEN3_RESIN_N_SET BIT(6)
  32. #define PON_GEN3_KPDPWR_N_SET BIT(7)
  33. #define PON_PS_HOLD_RST_CTL 0x5a
  34. #define PON_PS_HOLD_RST_CTL2 0x5b
  35. #define PON_PS_HOLD_ENABLE BIT(7)
  36. #define PON_PS_HOLD_TYPE_MASK 0x0f
  37. #define PON_PS_HOLD_TYPE_WARM_RESET 1
  38. #define PON_PS_HOLD_TYPE_SHUTDOWN 4
  39. #define PON_PS_HOLD_TYPE_HARD_RESET 7
  40. #define PON_PULL_CTL 0x70
  41. #define PON_KPDPWR_PULL_UP BIT(1)
  42. #define PON_RESIN_PULL_UP BIT(0)
  43. #define PON_DBC_CTL 0x71
  44. #define PON_DBC_DELAY_MASK_GEN1 0x7
  45. #define PON_DBC_DELAY_MASK_GEN2 0xf
  46. #define PON_DBC_SHIFT_GEN1 6
  47. #define PON_DBC_SHIFT_GEN2 14
  48. struct pm8941_data {
  49. unsigned int pull_up_bit;
  50. unsigned int status_bit;
  51. bool supports_ps_hold_poff_config;
  52. bool supports_debounce_config;
  53. bool has_pon_pbs;
  54. bool wakeup_source_default;
  55. const char *name;
  56. const char *phys;
  57. };
  58. struct pm8941_pwrkey {
  59. struct device *dev;
  60. int irq;
  61. u32 baseaddr;
  62. u32 pon_pbs_baseaddr;
  63. struct regmap *regmap;
  64. struct input_dev *input;
  65. unsigned int revision;
  66. unsigned int subtype;
  67. struct notifier_block reboot_notifier;
  68. u32 code;
  69. u32 sw_debounce_time_us;
  70. ktime_t sw_debounce_end_time;
  71. bool last_status;
  72. const struct pm8941_data *data;
  73. };
  74. static int pm8941_reboot_notify(struct notifier_block *nb,
  75. unsigned long code, void *unused)
  76. {
  77. struct pm8941_pwrkey *pwrkey = container_of(nb, struct pm8941_pwrkey,
  78. reboot_notifier);
  79. unsigned int enable_reg;
  80. unsigned int reset_type;
  81. int error;
  82. /* PMICs with revision 0 have the enable bit in same register as ctrl */
  83. if (pwrkey->revision == 0)
  84. enable_reg = PON_PS_HOLD_RST_CTL;
  85. else
  86. enable_reg = PON_PS_HOLD_RST_CTL2;
  87. error = regmap_update_bits(pwrkey->regmap,
  88. pwrkey->baseaddr + enable_reg,
  89. PON_PS_HOLD_ENABLE,
  90. 0);
  91. if (error)
  92. dev_err(pwrkey->dev,
  93. "unable to clear ps hold reset enable: %d\n",
  94. error);
  95. /*
  96. * Updates of PON_PS_HOLD_ENABLE requires 3 sleep cycles between
  97. * writes.
  98. */
  99. usleep_range(100, 1000);
  100. switch (code) {
  101. case SYS_HALT:
  102. case SYS_POWER_OFF:
  103. reset_type = PON_PS_HOLD_TYPE_SHUTDOWN;
  104. break;
  105. case SYS_RESTART:
  106. default:
  107. if (reboot_mode == REBOOT_WARM)
  108. reset_type = PON_PS_HOLD_TYPE_WARM_RESET;
  109. else
  110. reset_type = PON_PS_HOLD_TYPE_HARD_RESET;
  111. break;
  112. }
  113. error = regmap_update_bits(pwrkey->regmap,
  114. pwrkey->baseaddr + PON_PS_HOLD_RST_CTL,
  115. PON_PS_HOLD_TYPE_MASK,
  116. reset_type);
  117. if (error)
  118. dev_err(pwrkey->dev, "unable to set ps hold reset type: %d\n",
  119. error);
  120. error = regmap_update_bits(pwrkey->regmap,
  121. pwrkey->baseaddr + enable_reg,
  122. PON_PS_HOLD_ENABLE,
  123. PON_PS_HOLD_ENABLE);
  124. if (error)
  125. dev_err(pwrkey->dev, "unable to re-set enable: %d\n", error);
  126. return NOTIFY_DONE;
  127. }
  128. static irqreturn_t pm8941_pwrkey_irq(int irq, void *_data)
  129. {
  130. struct pm8941_pwrkey *pwrkey = _data;
  131. unsigned int sts;
  132. int err;
  133. if (pwrkey->sw_debounce_time_us) {
  134. if (ktime_before(ktime_get(), pwrkey->sw_debounce_end_time)) {
  135. dev_dbg(pwrkey->dev,
  136. "ignoring key event received before debounce end %lld us\n",
  137. ktime_to_us(pwrkey->sw_debounce_end_time));
  138. return IRQ_HANDLED;
  139. }
  140. }
  141. err = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_RT_STS, &sts);
  142. if (err)
  143. return IRQ_HANDLED;
  144. sts &= pwrkey->data->status_bit;
  145. if (pwrkey->sw_debounce_time_us && !sts)
  146. pwrkey->sw_debounce_end_time = ktime_add_us(ktime_get(),
  147. pwrkey->sw_debounce_time_us);
  148. /*
  149. * Simulate a press event in case a release event occurred without a
  150. * corresponding press event.
  151. */
  152. if (!pwrkey->last_status && !sts) {
  153. input_report_key(pwrkey->input, pwrkey->code, 1);
  154. input_sync(pwrkey->input);
  155. }
  156. pwrkey->last_status = sts;
  157. input_report_key(pwrkey->input, pwrkey->code, sts);
  158. input_sync(pwrkey->input);
  159. return IRQ_HANDLED;
  160. }
  161. static int pm8941_pwrkey_sw_debounce_init(struct pm8941_pwrkey *pwrkey)
  162. {
  163. unsigned int val, addr, mask;
  164. int error;
  165. if (pwrkey->data->has_pon_pbs && !pwrkey->pon_pbs_baseaddr) {
  166. dev_err(pwrkey->dev,
  167. "PON_PBS address missing, can't read HW debounce time\n");
  168. return 0;
  169. }
  170. if (pwrkey->pon_pbs_baseaddr)
  171. addr = pwrkey->pon_pbs_baseaddr + PON_DBC_CTL;
  172. else
  173. addr = pwrkey->baseaddr + PON_DBC_CTL;
  174. error = regmap_read(pwrkey->regmap, addr, &val);
  175. if (error)
  176. return error;
  177. if (pwrkey->subtype >= PON_SUBTYPE_GEN2_PRIMARY)
  178. mask = 0xf;
  179. else
  180. mask = 0x7;
  181. pwrkey->sw_debounce_time_us =
  182. 2 * USEC_PER_SEC / (1 << (mask - (val & mask)));
  183. dev_dbg(pwrkey->dev, "SW debounce time = %u us\n",
  184. pwrkey->sw_debounce_time_us);
  185. return 0;
  186. }
  187. static int pm8941_pwrkey_suspend(struct device *dev)
  188. {
  189. struct pm8941_pwrkey *pwrkey = dev_get_drvdata(dev);
  190. if (device_may_wakeup(dev))
  191. enable_irq_wake(pwrkey->irq);
  192. return 0;
  193. }
  194. static int pm8941_pwrkey_resume(struct device *dev)
  195. {
  196. struct pm8941_pwrkey *pwrkey = dev_get_drvdata(dev);
  197. if (device_may_wakeup(dev))
  198. disable_irq_wake(pwrkey->irq);
  199. return 0;
  200. }
  201. static DEFINE_SIMPLE_DEV_PM_OPS(pm8941_pwr_key_pm_ops,
  202. pm8941_pwrkey_suspend, pm8941_pwrkey_resume);
  203. static int pm8941_pwrkey_probe(struct platform_device *pdev)
  204. {
  205. struct pm8941_pwrkey *pwrkey;
  206. bool pull_up, wakeup;
  207. struct device *parent;
  208. struct device_node *regmap_node;
  209. const __be32 *addr;
  210. u32 req_delay, mask, delay_shift;
  211. int error;
  212. if (of_property_read_u32(pdev->dev.of_node, "debounce", &req_delay))
  213. req_delay = 15625;
  214. if (req_delay > 2000000 || req_delay == 0) {
  215. dev_err(&pdev->dev, "invalid debounce time: %u\n", req_delay);
  216. return -EINVAL;
  217. }
  218. pull_up = of_property_read_bool(pdev->dev.of_node, "bias-pull-up");
  219. pwrkey = devm_kzalloc(&pdev->dev, sizeof(*pwrkey), GFP_KERNEL);
  220. if (!pwrkey)
  221. return -ENOMEM;
  222. pwrkey->dev = &pdev->dev;
  223. pwrkey->data = of_device_get_match_data(&pdev->dev);
  224. parent = pdev->dev.parent;
  225. regmap_node = pdev->dev.of_node;
  226. pwrkey->regmap = dev_get_regmap(parent, NULL);
  227. if (!pwrkey->regmap) {
  228. regmap_node = parent->of_node;
  229. /*
  230. * We failed to get regmap for parent. Let's see if we are
  231. * a child of pon node and read regmap and reg from its
  232. * parent.
  233. */
  234. pwrkey->regmap = dev_get_regmap(parent->parent, NULL);
  235. if (!pwrkey->regmap) {
  236. dev_err(&pdev->dev, "failed to locate regmap\n");
  237. return -ENODEV;
  238. }
  239. }
  240. addr = of_get_address(regmap_node, 0, NULL, NULL);
  241. if (!addr) {
  242. dev_err(&pdev->dev, "reg property missing\n");
  243. return -EINVAL;
  244. }
  245. pwrkey->baseaddr = be32_to_cpup(addr);
  246. if (pwrkey->data->has_pon_pbs) {
  247. /* PON_PBS base address is optional */
  248. addr = of_get_address(regmap_node, 1, NULL, NULL);
  249. if (addr)
  250. pwrkey->pon_pbs_baseaddr = be32_to_cpup(addr);
  251. }
  252. pwrkey->irq = platform_get_irq(pdev, 0);
  253. if (pwrkey->irq < 0)
  254. return pwrkey->irq;
  255. error = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_REV2,
  256. &pwrkey->revision);
  257. if (error) {
  258. dev_err(&pdev->dev, "failed to read revision: %d\n", error);
  259. return error;
  260. }
  261. error = regmap_read(pwrkey->regmap, pwrkey->baseaddr + PON_SUBTYPE,
  262. &pwrkey->subtype);
  263. if (error) {
  264. dev_err(&pdev->dev, "failed to read subtype: %d\n", error);
  265. return error;
  266. }
  267. error = of_property_read_u32(pdev->dev.of_node, "linux,code",
  268. &pwrkey->code);
  269. if (error) {
  270. dev_dbg(&pdev->dev,
  271. "no linux,code assuming power (%d)\n", error);
  272. pwrkey->code = KEY_POWER;
  273. }
  274. pwrkey->input = devm_input_allocate_device(&pdev->dev);
  275. if (!pwrkey->input) {
  276. dev_dbg(&pdev->dev, "unable to allocate input device\n");
  277. return -ENOMEM;
  278. }
  279. input_set_capability(pwrkey->input, EV_KEY, pwrkey->code);
  280. pwrkey->input->name = pwrkey->data->name;
  281. pwrkey->input->phys = pwrkey->data->phys;
  282. if (pwrkey->data->supports_debounce_config) {
  283. if (pwrkey->subtype >= PON_SUBTYPE_GEN2_PRIMARY) {
  284. mask = PON_DBC_DELAY_MASK_GEN2;
  285. delay_shift = PON_DBC_SHIFT_GEN2;
  286. } else {
  287. mask = PON_DBC_DELAY_MASK_GEN1;
  288. delay_shift = PON_DBC_SHIFT_GEN1;
  289. }
  290. req_delay = (req_delay << delay_shift) / USEC_PER_SEC;
  291. req_delay = ilog2(req_delay);
  292. error = regmap_update_bits(pwrkey->regmap,
  293. pwrkey->baseaddr + PON_DBC_CTL,
  294. mask,
  295. req_delay);
  296. if (error) {
  297. dev_err(&pdev->dev, "failed to set debounce: %d\n",
  298. error);
  299. return error;
  300. }
  301. }
  302. error = pm8941_pwrkey_sw_debounce_init(pwrkey);
  303. if (error)
  304. return error;
  305. if (pwrkey->data->pull_up_bit) {
  306. error = regmap_update_bits(pwrkey->regmap,
  307. pwrkey->baseaddr + PON_PULL_CTL,
  308. pwrkey->data->pull_up_bit,
  309. pull_up ? pwrkey->data->pull_up_bit :
  310. 0);
  311. if (error) {
  312. dev_err(&pdev->dev, "failed to set pull: %d\n", error);
  313. return error;
  314. }
  315. }
  316. error = devm_request_threaded_irq(&pdev->dev, pwrkey->irq,
  317. NULL, pm8941_pwrkey_irq,
  318. IRQF_ONESHOT,
  319. pwrkey->data->name, pwrkey);
  320. if (error) {
  321. dev_err(&pdev->dev, "failed requesting IRQ: %d\n", error);
  322. return error;
  323. }
  324. error = input_register_device(pwrkey->input);
  325. if (error) {
  326. dev_err(&pdev->dev, "failed to register input device: %d\n",
  327. error);
  328. return error;
  329. }
  330. if (pwrkey->data->supports_ps_hold_poff_config) {
  331. pwrkey->reboot_notifier.notifier_call = pm8941_reboot_notify;
  332. error = register_reboot_notifier(&pwrkey->reboot_notifier);
  333. if (error) {
  334. dev_err(&pdev->dev, "failed to register reboot notifier: %d\n",
  335. error);
  336. return error;
  337. }
  338. }
  339. wakeup = pwrkey->data->wakeup_source_default ||
  340. of_property_read_bool(pdev->dev.of_node, "wakeup-source");
  341. platform_set_drvdata(pdev, pwrkey);
  342. device_init_wakeup(&pdev->dev, wakeup);
  343. return 0;
  344. }
  345. static void pm8941_pwrkey_remove(struct platform_device *pdev)
  346. {
  347. struct pm8941_pwrkey *pwrkey = platform_get_drvdata(pdev);
  348. if (pwrkey->data->supports_ps_hold_poff_config)
  349. unregister_reboot_notifier(&pwrkey->reboot_notifier);
  350. }
  351. static const struct pm8941_data pwrkey_data = {
  352. .pull_up_bit = PON_KPDPWR_PULL_UP,
  353. .status_bit = PON_KPDPWR_N_SET,
  354. .name = "pm8941_pwrkey",
  355. .phys = "pm8941_pwrkey/input0",
  356. .supports_ps_hold_poff_config = true,
  357. .supports_debounce_config = true,
  358. .has_pon_pbs = false,
  359. .wakeup_source_default = true,
  360. };
  361. static const struct pm8941_data resin_data = {
  362. .pull_up_bit = PON_RESIN_PULL_UP,
  363. .status_bit = PON_RESIN_N_SET,
  364. .name = "pm8941_resin",
  365. .phys = "pm8941_resin/input0",
  366. .supports_ps_hold_poff_config = true,
  367. .supports_debounce_config = true,
  368. .has_pon_pbs = false,
  369. .wakeup_source_default = false,
  370. };
  371. static const struct pm8941_data pon_gen3_pwrkey_data = {
  372. .status_bit = PON_GEN3_KPDPWR_N_SET,
  373. .name = "pmic_pwrkey",
  374. .phys = "pmic_pwrkey/input0",
  375. .supports_ps_hold_poff_config = false,
  376. .supports_debounce_config = false,
  377. .has_pon_pbs = true,
  378. .wakeup_source_default = true,
  379. };
  380. static const struct pm8941_data pon_gen3_resin_data = {
  381. .status_bit = PON_GEN3_RESIN_N_SET,
  382. .name = "pmic_resin",
  383. .phys = "pmic_resin/input0",
  384. .supports_ps_hold_poff_config = false,
  385. .supports_debounce_config = false,
  386. .has_pon_pbs = true,
  387. .wakeup_source_default = false,
  388. };
  389. static const struct of_device_id pm8941_pwr_key_id_table[] = {
  390. { .compatible = "qcom,pm8941-pwrkey", .data = &pwrkey_data },
  391. { .compatible = "qcom,pm8941-resin", .data = &resin_data },
  392. { .compatible = "qcom,pmk8350-pwrkey", .data = &pon_gen3_pwrkey_data },
  393. { .compatible = "qcom,pmk8350-resin", .data = &pon_gen3_resin_data },
  394. { }
  395. };
  396. MODULE_DEVICE_TABLE(of, pm8941_pwr_key_id_table);
  397. static struct platform_driver pm8941_pwrkey_driver = {
  398. .probe = pm8941_pwrkey_probe,
  399. .remove = pm8941_pwrkey_remove,
  400. .driver = {
  401. .name = "pm8941-pwrkey",
  402. .pm = pm_sleep_ptr(&pm8941_pwr_key_pm_ops),
  403. .of_match_table = of_match_ptr(pm8941_pwr_key_id_table),
  404. },
  405. };
  406. module_platform_driver(pm8941_pwrkey_driver);
  407. MODULE_DESCRIPTION("PM8941 Power Key driver");
  408. MODULE_LICENSE("GPL v2");