aw86927.c 23 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2025 Griffin Kroah-Hartman <griffin.kroah@fairphone.com>
  4. *
  5. * Partially based on vendor driver:
  6. * Copyright (c) 2021 AWINIC Technology CO., LTD
  7. *
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/bits.h>
  11. #include <linux/delay.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/i2c.h>
  14. #include <linux/input.h>
  15. #include <linux/module.h>
  16. #include <linux/regmap.h>
  17. #include <linux/regulator/consumer.h>
  18. #include <linux/types.h>
  19. #define AW86927_RSTCFG_REG 0x00
  20. #define AW86927_RSTCFG_SOFTRST 0xaa
  21. #define AW86927_SYSINT_REG 0x02
  22. #define AW86927_SYSINT_BST_SCPI BIT(7)
  23. #define AW86927_SYSINT_BST_OVPI BIT(6)
  24. #define AW86927_SYSINT_UVLI BIT(5)
  25. #define AW86927_SYSINT_FF_AEI BIT(4)
  26. #define AW86927_SYSINT_FF_AFI BIT(3)
  27. #define AW86927_SYSINT_OCDI BIT(2)
  28. #define AW86927_SYSINT_OTI BIT(1)
  29. #define AW86927_SYSINT_DONEI BIT(0)
  30. #define AW86927_SYSINTM_REG 0x03
  31. #define AW86927_SYSINTM_BST_OVPM BIT(6)
  32. #define AW86927_SYSINTM_FF_AEM BIT(4)
  33. #define AW86927_SYSINTM_FF_AFM BIT(3)
  34. #define AW86927_SYSINTM_DONEM BIT(0)
  35. #define AW86927_PLAYCFG1_REG 0x06
  36. #define AW86927_PLAYCFG1_BST_MODE_MASK GENMASK(7, 7)
  37. #define AW86927_PLAYCFG1_BST_MODE_BYPASS 0
  38. #define AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK GENMASK(6, 0)
  39. #define AW86927_PLAYCFG1_BST_8500MV 0x50
  40. #define AW86927_PLAYCFG2_REG 0x07
  41. #define AW86927_PLAYCFG3_REG 0x08
  42. #define AW86927_PLAYCFG3_AUTO_BST_MASK GENMASK(4, 4)
  43. #define AW86927_PLAYCFG3_AUTO_BST_ENABLE 1
  44. #define AW86927_PLAYCFG3_AUTO_BST_DISABLE 0
  45. #define AW86927_PLAYCFG3_PLAY_MODE_MASK GENMASK(1, 0)
  46. #define AW86927_PLAYCFG3_PLAY_MODE_RAM 0
  47. #define AW86927_PLAYCFG4_REG 0x09
  48. #define AW86927_PLAYCFG4_STOP BIT(1)
  49. #define AW86927_PLAYCFG4_GO BIT(0)
  50. #define AW86927_WAVCFG1_REG 0x0a
  51. #define AW86927_WAVCFG1_WAVSEQ1_MASK GENMASK(6, 0)
  52. #define AW86927_WAVCFG2_REG 0x0b
  53. #define AW86927_WAVCFG2_WAVSEQ2_MASK GENMASK(6, 0)
  54. #define AW86927_WAVCFG9_REG 0x12
  55. #define AW86927_WAVCFG9_SEQ1LOOP_MASK GENMASK(7, 4)
  56. #define AW86927_WAVCFG9_SEQ1LOOP_INFINITELY 0x0f
  57. #define AW86927_CONTCFG1_REG 0x18
  58. #define AW86927_CONTCFG1_BRK_BST_MD_MASK GENMASK(6, 6)
  59. #define AW86927_CONTCFG5_REG 0x1c
  60. #define AW86927_CONTCFG5_BST_BRK_GAIN_MASK GENMASK(7, 4)
  61. #define AW86927_CONTCFG5_BRK_GAIN_MASK GENMASK(3, 0)
  62. #define AW86927_CONTCFG10_REG 0x21
  63. #define AW86927_CONTCFG10_BRK_TIME_MASK GENMASK(7, 0)
  64. #define AW86927_CONTCFG10_BRK_TIME_DEFAULT 8
  65. #define AW86927_CONTCFG13_REG 0x24
  66. #define AW86927_CONTCFG13_TSET_MASK GENMASK(7, 4)
  67. #define AW86927_CONTCFG13_BEME_SET_MASK GENMASK(3, 0)
  68. #define AW86927_BASEADDRH_REG 0x2d
  69. #define AW86927_BASEADDRL_REG 0x2e
  70. #define AW86927_GLBRD5_REG 0x3f
  71. #define AW86927_GLBRD5_STATE_MASK GENMASK(3, 0)
  72. #define AW86927_GLBRD5_STATE_STANDBY 0
  73. #define AW86927_RAMADDRH_REG 0x40
  74. #define AW86927_RAMADDRL_REG 0x41
  75. #define AW86927_RAMDATA_REG 0x42
  76. #define AW86927_SYSCTRL3_REG 0x45
  77. #define AW86927_SYSCTRL3_STANDBY_MASK GENMASK(5, 5)
  78. #define AW86927_SYSCTRL3_STANDBY_ON 1
  79. #define AW86927_SYSCTRL3_STANDBY_OFF 0
  80. #define AW86927_SYSCTRL3_EN_RAMINIT_MASK GENMASK(2, 2)
  81. #define AW86927_SYSCTRL3_EN_RAMINIT_ON 1
  82. #define AW86927_SYSCTRL3_EN_RAMINIT_OFF 0
  83. #define AW86927_SYSCTRL4_REG 0x46
  84. #define AW86927_SYSCTRL4_WAVDAT_MODE_MASK GENMASK(6, 5)
  85. #define AW86927_SYSCTRL4_WAVDAT_24K 0
  86. #define AW86927_SYSCTRL4_INT_EDGE_MODE_MASK GENMASK(4, 4)
  87. #define AW86927_SYSCTRL4_INT_EDGE_MODE_POS 0
  88. #define AW86927_SYSCTRL4_INT_MODE_MASK GENMASK(3, 3)
  89. #define AW86927_SYSCTRL4_INT_MODE_EDGE 1
  90. #define AW86927_SYSCTRL4_GAIN_BYPASS_MASK GENMASK(0, 0)
  91. #define AW86927_PWMCFG1_REG 0x48
  92. #define AW86927_PWMCFG1_PRC_EN_MASK GENMASK(7, 7)
  93. #define AW86927_PWMCFG1_PRC_DISABLE 0
  94. #define AW86927_PWMCFG3_REG 0x4a
  95. #define AW86927_PWMCFG3_PR_EN_MASK GENMASK(7, 7)
  96. #define AW86927_PWMCFG3_PRCTIME_MASK GENMASK(6, 0)
  97. #define AW86927_PWMCFG4_REG 0x4b
  98. #define AW86927_PWMCFG4_PRTIME_MASK GENMASK(7, 0)
  99. #define AW86927_VBATCTRL_REG 0x4c
  100. #define AW86927_VBATCTRL_VBAT_MODE_MASK GENMASK(6, 6)
  101. #define AW86927_VBATCTRL_VBAT_MODE_SW 0
  102. #define AW86927_DETCFG1_REG 0x4d
  103. #define AW86927_DETCFG1_DET_GO_MASK GENMASK(1, 0)
  104. #define AW86927_DETCFG1_DET_GO_DET_SEQ0 1
  105. #define AW86927_DETCFG1_DET_GO_NA 0
  106. #define AW86927_DETCFG2_REG 0x4e
  107. #define AW86927_DETCFG2_DET_SEQ0_MASK GENMASK(6, 3)
  108. #define AW86927_DETCFG2_DET_SEQ0_VBAT 0
  109. #define AW86927_DETCFG2_D2S_GAIN_MASK GENMASK(2, 0)
  110. #define AW86927_DETCFG2_D2S_GAIN_10 4
  111. #define AW86927_CHIPIDH_REG 0x57
  112. #define AW86927_CHIPIDL_REG 0x58
  113. #define AW86927_CHIPID 0x9270
  114. #define AW86927_TMCFG_REG 0x5b
  115. #define AW86927_TMCFG_UNLOCK 0x7d
  116. #define AW86927_TMCFG_LOCK 0x00
  117. #define AW86927_ANACFG11_REG 0x70
  118. #define AW86927_ANACFG12_REG 0x71
  119. #define AW86927_ANACFG12_BST_SKIP_MASK GENMASK(7, 7)
  120. #define AW86927_ANACFG12_BST_SKIP_SHUTDOWN 1
  121. #define AW86927_ANACFG13_REG 0x72
  122. #define AW86927_ANACFG13_BST_PC_MASK GENMASK(7, 4)
  123. #define AW86927_ANACFG13_BST_PEAKCUR_3P45A 6
  124. #define AW86927_ANACFG15_REG 0x74
  125. #define AW86927_ANACFG15_BST_PEAK_MODE_MASK GENMASK(7, 7)
  126. #define AW86927_ANACFG15_BST_PEAK_BACK 1
  127. #define AW86927_ANACFG16_REG 0x75
  128. #define AW86927_ANACFG16_BST_SRC_MASK GENMASK(4, 4)
  129. #define AW86927_ANACFG16_BST_SRC_3NS 0
  130. /* default value of base addr */
  131. #define AW86927_RAM_BASE_ADDR 0x800
  132. #define AW86927_BASEADDRH_VAL 0x08
  133. #define AW86927_BASEADDRL_VAL 0x00
  134. enum aw86927_work_mode {
  135. AW86927_STANDBY_MODE,
  136. AW86927_RAM_MODE,
  137. };
  138. struct aw86927_data {
  139. struct work_struct play_work;
  140. struct device *dev;
  141. struct input_dev *input_dev;
  142. struct i2c_client *client;
  143. struct regmap *regmap;
  144. struct gpio_desc *reset_gpio;
  145. bool running;
  146. };
  147. static const struct regmap_config aw86927_regmap_config = {
  148. .reg_bits = 8,
  149. .val_bits = 8,
  150. .cache_type = REGCACHE_NONE,
  151. .max_register = 0x80,
  152. };
  153. /*
  154. * Sine wave representing the magnitude of the drive to be used.
  155. * Data is encoded in two's complement.
  156. * round(84 * sin(x / 16.25))
  157. */
  158. static const u8 aw86927_waveform[] = {
  159. 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x1a, 0x1f, 0x23, 0x28, 0x2d, 0x31, 0x35,
  160. 0x39, 0x3d, 0x41, 0x44, 0x47, 0x4a, 0x4c, 0x4f, 0x51, 0x52, 0x53, 0x54,
  161. 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x52, 0x51, 0x4f, 0x4d, 0x4a, 0x47,
  162. 0x44, 0x41, 0x3d, 0x3a, 0x36, 0x31, 0x2d, 0x28, 0x24, 0x1f, 0x1a, 0x15,
  163. 0x10, 0x0a, 0x05, 0x00, 0xfc, 0xf6, 0xf1, 0xec, 0xe7, 0xe2, 0xdd, 0xd8,
  164. 0xd4, 0xcf, 0xcb, 0xc7, 0xc3, 0xbf, 0xbc, 0xb9, 0xb6, 0xb4, 0xb1, 0xb0,
  165. 0xae, 0xad, 0xac, 0xab, 0xab, 0xab, 0xab, 0xab, 0xac, 0xae, 0xaf, 0xb1,
  166. 0xb3, 0xb6, 0xb8, 0xbc, 0xbf, 0xc2, 0xc6, 0xca, 0xce, 0xd3, 0xd7, 0xdc,
  167. 0xe1, 0xe6, 0xeb, 0xf0, 0xf5, 0xfb
  168. };
  169. struct aw86927_sram_waveform_header {
  170. u8 version;
  171. __be16 start_address;
  172. __be16 end_address;
  173. } __packed;
  174. static const struct aw86927_sram_waveform_header sram_waveform_header = {
  175. .version = 0x01,
  176. .start_address = cpu_to_be16(AW86927_RAM_BASE_ADDR +
  177. sizeof(struct aw86927_sram_waveform_header)),
  178. .end_address = cpu_to_be16(AW86927_RAM_BASE_ADDR +
  179. sizeof(struct aw86927_sram_waveform_header) +
  180. ARRAY_SIZE(aw86927_waveform) - 1),
  181. };
  182. static int aw86927_wait_enter_standby(struct aw86927_data *haptics)
  183. {
  184. unsigned int reg_val;
  185. int err;
  186. err = regmap_read_poll_timeout(haptics->regmap, AW86927_GLBRD5_REG, reg_val,
  187. (FIELD_GET(AW86927_GLBRD5_STATE_MASK, reg_val) ==
  188. AW86927_GLBRD5_STATE_STANDBY),
  189. 2500, 2500 * 100);
  190. if (err) {
  191. dev_err(haptics->dev, "did not enter standby: %d\n", err);
  192. return err;
  193. }
  194. return 0;
  195. }
  196. static int aw86927_play_mode(struct aw86927_data *haptics, u8 play_mode)
  197. {
  198. int err;
  199. switch (play_mode) {
  200. case AW86927_STANDBY_MODE:
  201. /* Briefly toggle standby, then toggle back to standby off */
  202. err = regmap_update_bits(haptics->regmap,
  203. AW86927_SYSCTRL3_REG,
  204. AW86927_SYSCTRL3_STANDBY_MASK,
  205. FIELD_PREP(AW86927_SYSCTRL3_STANDBY_MASK,
  206. AW86927_SYSCTRL3_STANDBY_ON));
  207. if (err)
  208. return err;
  209. err = regmap_update_bits(haptics->regmap,
  210. AW86927_SYSCTRL3_REG,
  211. AW86927_SYSCTRL3_STANDBY_MASK,
  212. FIELD_PREP(AW86927_SYSCTRL3_STANDBY_MASK,
  213. AW86927_SYSCTRL3_STANDBY_OFF));
  214. if (err)
  215. return err;
  216. break;
  217. case AW86927_RAM_MODE:
  218. err = regmap_update_bits(haptics->regmap,
  219. AW86927_PLAYCFG3_REG,
  220. AW86927_PLAYCFG3_PLAY_MODE_MASK,
  221. FIELD_PREP(AW86927_PLAYCFG3_PLAY_MODE_MASK,
  222. AW86927_PLAYCFG3_PLAY_MODE_RAM));
  223. if (err)
  224. return err;
  225. err = regmap_update_bits(haptics->regmap,
  226. AW86927_PLAYCFG1_REG,
  227. AW86927_PLAYCFG1_BST_MODE_MASK,
  228. FIELD_PREP(AW86927_PLAYCFG1_BST_MODE_MASK,
  229. AW86927_PLAYCFG1_BST_MODE_BYPASS));
  230. if (err)
  231. return err;
  232. err = regmap_update_bits(haptics->regmap,
  233. AW86927_VBATCTRL_REG,
  234. AW86927_VBATCTRL_VBAT_MODE_MASK,
  235. FIELD_PREP(AW86927_VBATCTRL_VBAT_MODE_MASK,
  236. AW86927_VBATCTRL_VBAT_MODE_SW));
  237. if (err)
  238. return err;
  239. break;
  240. }
  241. return 0;
  242. }
  243. static int aw86927_stop(struct aw86927_data *haptics)
  244. {
  245. int err;
  246. err = regmap_write(haptics->regmap, AW86927_PLAYCFG4_REG, AW86927_PLAYCFG4_STOP);
  247. if (err) {
  248. dev_err(haptics->dev, "Failed to stop playback: %d\n", err);
  249. return err;
  250. }
  251. err = aw86927_wait_enter_standby(haptics);
  252. if (err) {
  253. dev_err(haptics->dev, "Failed to enter standby, trying to force it\n");
  254. err = aw86927_play_mode(haptics, AW86927_STANDBY_MODE);
  255. if (err)
  256. return err;
  257. }
  258. return 0;
  259. }
  260. static int aw86927_haptics_play(struct input_dev *dev, void *data, struct ff_effect *effect)
  261. {
  262. struct aw86927_data *haptics = input_get_drvdata(dev);
  263. int level;
  264. level = effect->u.rumble.strong_magnitude;
  265. if (!level)
  266. level = effect->u.rumble.weak_magnitude;
  267. /* If already running, don't restart playback */
  268. if (haptics->running && level)
  269. return 0;
  270. haptics->running = level;
  271. schedule_work(&haptics->play_work);
  272. return 0;
  273. }
  274. static int aw86927_play_sine(struct aw86927_data *haptics)
  275. {
  276. int err;
  277. err = aw86927_stop(haptics);
  278. if (err)
  279. return err;
  280. err = aw86927_play_mode(haptics, AW86927_RAM_MODE);
  281. if (err)
  282. return err;
  283. err = regmap_update_bits(haptics->regmap, AW86927_PLAYCFG3_REG,
  284. AW86927_PLAYCFG3_AUTO_BST_MASK,
  285. FIELD_PREP(AW86927_PLAYCFG3_AUTO_BST_MASK,
  286. AW86927_PLAYCFG3_AUTO_BST_ENABLE));
  287. if (err)
  288. return err;
  289. /* Set waveseq 1 to the first wave */
  290. err = regmap_update_bits(haptics->regmap, AW86927_WAVCFG1_REG,
  291. AW86927_WAVCFG1_WAVSEQ1_MASK,
  292. FIELD_PREP(AW86927_WAVCFG1_WAVSEQ1_MASK, 1));
  293. if (err)
  294. return err;
  295. /* set wavseq 2 to zero */
  296. err = regmap_update_bits(haptics->regmap, AW86927_WAVCFG2_REG,
  297. AW86927_WAVCFG2_WAVSEQ2_MASK,
  298. FIELD_PREP(AW86927_WAVCFG2_WAVSEQ2_MASK, 0));
  299. if (err)
  300. return err;
  301. err = regmap_update_bits(haptics->regmap,
  302. AW86927_WAVCFG9_REG,
  303. AW86927_WAVCFG9_SEQ1LOOP_MASK,
  304. FIELD_PREP(AW86927_WAVCFG9_SEQ1LOOP_MASK,
  305. AW86927_WAVCFG9_SEQ1LOOP_INFINITELY));
  306. if (err)
  307. return err;
  308. /* set gain to value lower than 0x80 to avoid distorted playback */
  309. err = regmap_write(haptics->regmap, AW86927_PLAYCFG2_REG, 0x7c);
  310. if (err)
  311. return err;
  312. /* Start playback */
  313. err = regmap_write(haptics->regmap, AW86927_PLAYCFG4_REG, AW86927_PLAYCFG4_GO);
  314. if (err)
  315. return err;
  316. return 0;
  317. }
  318. static void aw86927_close(struct input_dev *input)
  319. {
  320. struct aw86927_data *haptics = input_get_drvdata(input);
  321. struct device *dev = &haptics->client->dev;
  322. int err;
  323. cancel_work_sync(&haptics->play_work);
  324. err = aw86927_stop(haptics);
  325. if (err)
  326. dev_err(dev, "Failed to close the Driver: %d\n", err);
  327. }
  328. static void aw86927_haptics_play_work(struct work_struct *work)
  329. {
  330. struct aw86927_data *haptics =
  331. container_of(work, struct aw86927_data, play_work);
  332. struct device *dev = &haptics->client->dev;
  333. int err;
  334. if (haptics->running)
  335. err = aw86927_play_sine(haptics);
  336. else
  337. err = aw86927_stop(haptics);
  338. if (err)
  339. dev_err(dev, "Failed to execute work command: %d\n", err);
  340. }
  341. static void aw86927_hw_reset(struct aw86927_data *haptics)
  342. {
  343. /* Assert reset */
  344. gpiod_set_value_cansleep(haptics->reset_gpio, 1);
  345. /* Wait ~1ms */
  346. usleep_range(1000, 2000);
  347. /* Deassert reset */
  348. gpiod_set_value_cansleep(haptics->reset_gpio, 0);
  349. /* Wait ~8ms until I2C is accessible */
  350. usleep_range(8000, 8500);
  351. }
  352. static int aw86927_haptic_init(struct aw86927_data *haptics)
  353. {
  354. int err;
  355. err = regmap_update_bits(haptics->regmap,
  356. AW86927_SYSCTRL4_REG,
  357. AW86927_SYSCTRL4_WAVDAT_MODE_MASK,
  358. FIELD_PREP(AW86927_SYSCTRL4_WAVDAT_MODE_MASK,
  359. AW86927_SYSCTRL4_WAVDAT_24K));
  360. if (err)
  361. return err;
  362. /* enable gain bypass */
  363. err = regmap_update_bits(haptics->regmap,
  364. AW86927_SYSCTRL4_REG,
  365. AW86927_SYSCTRL4_GAIN_BYPASS_MASK,
  366. FIELD_PREP(AW86927_SYSCTRL4_GAIN_BYPASS_MASK,
  367. 0x01));
  368. if (err)
  369. return err;
  370. err = regmap_write(haptics->regmap,
  371. AW86927_TMCFG_REG, AW86927_TMCFG_UNLOCK);
  372. if (err)
  373. return err;
  374. err = regmap_write(haptics->regmap, AW86927_ANACFG11_REG, 0x0f);
  375. if (err)
  376. return err;
  377. err = regmap_update_bits(haptics->regmap,
  378. AW86927_ANACFG12_REG,
  379. AW86927_ANACFG12_BST_SKIP_MASK,
  380. FIELD_PREP(AW86927_ANACFG12_BST_SKIP_MASK,
  381. AW86927_ANACFG12_BST_SKIP_SHUTDOWN));
  382. if (err)
  383. return err;
  384. err = regmap_update_bits(haptics->regmap,
  385. AW86927_ANACFG15_REG,
  386. AW86927_ANACFG15_BST_PEAK_MODE_MASK,
  387. FIELD_PREP(AW86927_ANACFG15_BST_PEAK_MODE_MASK,
  388. AW86927_ANACFG15_BST_PEAK_BACK));
  389. if (err)
  390. return err;
  391. err = regmap_update_bits(haptics->regmap,
  392. AW86927_ANACFG16_REG,
  393. AW86927_ANACFG16_BST_SRC_MASK,
  394. FIELD_PREP(AW86927_ANACFG16_BST_SRC_MASK,
  395. AW86927_ANACFG16_BST_SRC_3NS));
  396. if (err)
  397. return err;
  398. err = regmap_write(haptics->regmap,
  399. AW86927_TMCFG_REG, AW86927_TMCFG_LOCK);
  400. if (err)
  401. return err;
  402. err = regmap_update_bits(haptics->regmap,
  403. AW86927_CONTCFG1_REG,
  404. AW86927_CONTCFG1_BRK_BST_MD_MASK,
  405. FIELD_PREP(AW86927_CONTCFG1_BRK_BST_MD_MASK, 0x00));
  406. if (err)
  407. return err;
  408. err = regmap_write(haptics->regmap,
  409. AW86927_CONTCFG5_REG,
  410. FIELD_PREP(AW86927_CONTCFG5_BST_BRK_GAIN_MASK, 0x05) |
  411. FIELD_PREP(AW86927_CONTCFG5_BRK_GAIN_MASK, 0x08));
  412. if (err)
  413. return err;
  414. err = regmap_update_bits(haptics->regmap, AW86927_CONTCFG10_REG,
  415. AW86927_CONTCFG10_BRK_TIME_MASK,
  416. FIELD_PREP(AW86927_CONTCFG10_BRK_TIME_MASK,
  417. AW86927_CONTCFG10_BRK_TIME_DEFAULT));
  418. if (err)
  419. return err;
  420. err = regmap_write(haptics->regmap,
  421. AW86927_CONTCFG13_REG,
  422. FIELD_PREP(AW86927_CONTCFG13_TSET_MASK, 0x06) |
  423. FIELD_PREP(AW86927_CONTCFG13_BEME_SET_MASK, 0x02));
  424. if (err)
  425. return err;
  426. err = regmap_update_bits(haptics->regmap,
  427. AW86927_DETCFG2_REG,
  428. AW86927_DETCFG2_D2S_GAIN_MASK,
  429. FIELD_PREP(AW86927_DETCFG2_D2S_GAIN_MASK,
  430. AW86927_DETCFG2_D2S_GAIN_10));
  431. if (err)
  432. return err;
  433. err = regmap_update_bits(haptics->regmap,
  434. AW86927_PWMCFG1_REG,
  435. AW86927_PWMCFG1_PRC_EN_MASK,
  436. FIELD_PREP(AW86927_PWMCFG1_PRC_EN_MASK,
  437. AW86927_PWMCFG1_PRC_DISABLE));
  438. if (err)
  439. return err;
  440. err = regmap_write(haptics->regmap,
  441. AW86927_PWMCFG3_REG,
  442. FIELD_PREP(AW86927_PWMCFG3_PR_EN_MASK, 0x01) |
  443. FIELD_PREP(AW86927_PWMCFG3_PRCTIME_MASK, 0x3f));
  444. if (err)
  445. return err;
  446. err = regmap_update_bits(haptics->regmap,
  447. AW86927_PWMCFG4_REG,
  448. AW86927_PWMCFG4_PRTIME_MASK,
  449. FIELD_PREP(AW86927_PWMCFG4_PRTIME_MASK, 0x32));
  450. if (err)
  451. return err;
  452. err = regmap_write(haptics->regmap,
  453. AW86927_TMCFG_REG, AW86927_TMCFG_UNLOCK);
  454. if (err)
  455. return err;
  456. err = regmap_update_bits(haptics->regmap,
  457. AW86927_ANACFG13_REG,
  458. AW86927_ANACFG13_BST_PC_MASK,
  459. FIELD_PREP(AW86927_ANACFG13_BST_PC_MASK,
  460. AW86927_ANACFG13_BST_PEAKCUR_3P45A));
  461. if (err)
  462. return err;
  463. err = regmap_write(haptics->regmap,
  464. AW86927_TMCFG_REG, AW86927_TMCFG_LOCK);
  465. if (err)
  466. return err;
  467. err = regmap_update_bits(haptics->regmap,
  468. AW86927_PLAYCFG1_REG,
  469. AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK,
  470. FIELD_PREP(AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK,
  471. AW86927_PLAYCFG1_BST_8500MV));
  472. if (err)
  473. return err;
  474. err = regmap_update_bits(haptics->regmap,
  475. AW86927_PLAYCFG3_REG,
  476. AW86927_PLAYCFG3_AUTO_BST_MASK,
  477. FIELD_PREP(AW86927_PLAYCFG3_AUTO_BST_MASK,
  478. AW86927_PLAYCFG3_AUTO_BST_DISABLE));
  479. if (err)
  480. return err;
  481. return 0;
  482. }
  483. static int aw86927_ram_init(struct aw86927_data *haptics)
  484. {
  485. int err;
  486. err = aw86927_wait_enter_standby(haptics);
  487. if (err)
  488. return err;
  489. /* Enable SRAM init */
  490. err = regmap_update_bits(haptics->regmap,
  491. AW86927_SYSCTRL3_REG,
  492. AW86927_SYSCTRL3_EN_RAMINIT_MASK,
  493. FIELD_PREP(AW86927_SYSCTRL3_EN_RAMINIT_MASK,
  494. AW86927_SYSCTRL3_EN_RAMINIT_ON));
  495. /* Set base address for the start of the SRAM waveforms */
  496. err = regmap_write(haptics->regmap,
  497. AW86927_BASEADDRH_REG, AW86927_BASEADDRH_VAL);
  498. if (err)
  499. return err;
  500. err = regmap_write(haptics->regmap,
  501. AW86927_BASEADDRL_REG, AW86927_BASEADDRL_VAL);
  502. if (err)
  503. return err;
  504. /* Set start of SRAM, before the data is written it will be the same as the base */
  505. err = regmap_write(haptics->regmap,
  506. AW86927_RAMADDRH_REG, AW86927_BASEADDRH_VAL);
  507. if (err)
  508. return err;
  509. err = regmap_write(haptics->regmap,
  510. AW86927_RAMADDRL_REG, AW86927_BASEADDRL_VAL);
  511. if (err)
  512. return err;
  513. /* Write waveform header to SRAM */
  514. err = regmap_noinc_write(haptics->regmap, AW86927_RAMDATA_REG,
  515. &sram_waveform_header, sizeof(sram_waveform_header));
  516. if (err)
  517. return err;
  518. /* Write waveform to SRAM */
  519. err = regmap_noinc_write(haptics->regmap, AW86927_RAMDATA_REG,
  520. aw86927_waveform, ARRAY_SIZE(aw86927_waveform));
  521. if (err)
  522. return err;
  523. err = regmap_update_bits(haptics->regmap,
  524. AW86927_DETCFG2_REG,
  525. AW86927_DETCFG2_DET_SEQ0_MASK,
  526. FIELD_PREP(AW86927_DETCFG2_DET_SEQ0_MASK,
  527. AW86927_DETCFG2_DET_SEQ0_VBAT));
  528. if (err)
  529. return err;
  530. err = regmap_update_bits(haptics->regmap,
  531. AW86927_DETCFG1_REG,
  532. AW86927_DETCFG1_DET_GO_MASK,
  533. FIELD_PREP(AW86927_DETCFG1_DET_GO_MASK,
  534. AW86927_DETCFG1_DET_GO_DET_SEQ0));
  535. if (err)
  536. return err;
  537. usleep_range(3000, 3500);
  538. err = regmap_update_bits(haptics->regmap,
  539. AW86927_DETCFG1_REG,
  540. AW86927_DETCFG1_DET_GO_MASK,
  541. FIELD_PREP(AW86927_DETCFG1_DET_GO_MASK,
  542. AW86927_DETCFG1_DET_GO_NA));
  543. if (err)
  544. return err;
  545. /* Disable SRAM init */
  546. err = regmap_update_bits(haptics->regmap,
  547. AW86927_SYSCTRL3_REG,
  548. AW86927_SYSCTRL3_EN_RAMINIT_MASK,
  549. FIELD_PREP(AW86927_SYSCTRL3_EN_RAMINIT_MASK,
  550. AW86927_SYSCTRL3_EN_RAMINIT_OFF));
  551. if (err)
  552. return err;
  553. return 0;
  554. }
  555. static irqreturn_t aw86927_irq(int irq, void *data)
  556. {
  557. struct aw86927_data *haptics = data;
  558. struct device *dev = &haptics->client->dev;
  559. unsigned int reg_val;
  560. int err;
  561. err = regmap_read(haptics->regmap, AW86927_SYSINT_REG, &reg_val);
  562. if (err) {
  563. dev_err(dev, "Failed to read SYSINT register: %d\n", err);
  564. return IRQ_NONE;
  565. }
  566. if (reg_val & AW86927_SYSINT_BST_SCPI)
  567. dev_err(dev, "Received a Short Circuit Protection interrupt\n");
  568. if (reg_val & AW86927_SYSINT_BST_OVPI)
  569. dev_err(dev, "Received an Over Voltage Protection interrupt\n");
  570. if (reg_val & AW86927_SYSINT_UVLI)
  571. dev_err(dev, "Received an Under Voltage Lock Out interrupt\n");
  572. if (reg_val & AW86927_SYSINT_OCDI)
  573. dev_err(dev, "Received an Over Current interrupt\n");
  574. if (reg_val & AW86927_SYSINT_OTI)
  575. dev_err(dev, "Received an Over Temperature interrupt\n");
  576. if (reg_val & AW86927_SYSINT_DONEI)
  577. dev_dbg(dev, "Chip playback done!\n");
  578. if (reg_val & AW86927_SYSINT_FF_AFI)
  579. dev_dbg(dev, "The RTP mode FIFO is almost full!\n");
  580. if (reg_val & AW86927_SYSINT_FF_AEI)
  581. dev_dbg(dev, "The RTP mode FIFO is almost empty!\n");
  582. return IRQ_HANDLED;
  583. }
  584. static int aw86927_detect(struct aw86927_data *haptics)
  585. {
  586. __be16 read_buf;
  587. u16 chip_id;
  588. int err;
  589. err = regmap_bulk_read(haptics->regmap, AW86927_CHIPIDH_REG, &read_buf, 2);
  590. if (err)
  591. return dev_err_probe(haptics->dev, err, "Failed to read CHIPID registers\n");
  592. chip_id = be16_to_cpu(read_buf);
  593. if (chip_id != AW86927_CHIPID) {
  594. dev_err(haptics->dev, "Unexpected CHIPID value 0x%x\n", chip_id);
  595. return -ENODEV;
  596. }
  597. return 0;
  598. }
  599. static int aw86927_probe(struct i2c_client *client)
  600. {
  601. struct aw86927_data *haptics;
  602. int err;
  603. haptics = devm_kzalloc(&client->dev, sizeof(struct aw86927_data), GFP_KERNEL);
  604. if (!haptics)
  605. return -ENOMEM;
  606. haptics->dev = &client->dev;
  607. haptics->client = client;
  608. i2c_set_clientdata(client, haptics);
  609. haptics->regmap = devm_regmap_init_i2c(client, &aw86927_regmap_config);
  610. if (IS_ERR(haptics->regmap))
  611. return dev_err_probe(haptics->dev, PTR_ERR(haptics->regmap),
  612. "Failed to allocate register map\n");
  613. haptics->input_dev = devm_input_allocate_device(haptics->dev);
  614. if (!haptics->input_dev)
  615. return -ENOMEM;
  616. haptics->reset_gpio = devm_gpiod_get(haptics->dev, "reset", GPIOD_OUT_HIGH);
  617. if (IS_ERR(haptics->reset_gpio))
  618. return dev_err_probe(haptics->dev, PTR_ERR(haptics->reset_gpio),
  619. "Failed to get reset gpio\n");
  620. /* Hardware reset */
  621. aw86927_hw_reset(haptics);
  622. /* Software reset */
  623. err = regmap_write(haptics->regmap, AW86927_RSTCFG_REG, AW86927_RSTCFG_SOFTRST);
  624. if (err)
  625. return dev_err_probe(haptics->dev, err, "Failed Software reset\n");
  626. /* Wait ~3ms until I2C is accessible */
  627. usleep_range(3000, 3500);
  628. err = aw86927_detect(haptics);
  629. if (err)
  630. return dev_err_probe(haptics->dev, err, "Failed to find chip\n");
  631. /* IRQ config */
  632. err = regmap_write(haptics->regmap, AW86927_SYSCTRL4_REG,
  633. FIELD_PREP(AW86927_SYSCTRL4_INT_MODE_MASK,
  634. AW86927_SYSCTRL4_INT_MODE_EDGE) |
  635. FIELD_PREP(AW86927_SYSCTRL4_INT_EDGE_MODE_MASK,
  636. AW86927_SYSCTRL4_INT_EDGE_MODE_POS));
  637. if (err)
  638. return dev_err_probe(haptics->dev, err, "Failed to configure interrupt modes\n");
  639. err = regmap_write(haptics->regmap, AW86927_SYSINTM_REG,
  640. AW86927_SYSINTM_BST_OVPM |
  641. AW86927_SYSINTM_FF_AEM |
  642. AW86927_SYSINTM_FF_AFM |
  643. AW86927_SYSINTM_DONEM);
  644. if (err)
  645. return dev_err_probe(haptics->dev, err, "Failed to configure interrupt masks\n");
  646. err = devm_request_threaded_irq(haptics->dev, client->irq, NULL,
  647. aw86927_irq, IRQF_ONESHOT, NULL, haptics);
  648. if (err)
  649. return dev_err_probe(haptics->dev, err, "Failed to request threaded irq\n");
  650. INIT_WORK(&haptics->play_work, aw86927_haptics_play_work);
  651. haptics->input_dev->name = "aw86927-haptics";
  652. haptics->input_dev->close = aw86927_close;
  653. input_set_drvdata(haptics->input_dev, haptics);
  654. input_set_capability(haptics->input_dev, EV_FF, FF_RUMBLE);
  655. err = input_ff_create_memless(haptics->input_dev, NULL, aw86927_haptics_play);
  656. if (err)
  657. return dev_err_probe(haptics->dev, err, "Failed to create FF dev\n");
  658. /* Set up registers */
  659. err = aw86927_play_mode(haptics, AW86927_STANDBY_MODE);
  660. if (err)
  661. return dev_err_probe(haptics->dev, err,
  662. "Failed to enter standby for Haptic init\n");
  663. err = aw86927_haptic_init(haptics);
  664. if (err)
  665. return dev_err_probe(haptics->dev, err, "Haptic init failed\n");
  666. /* RAM init, upload the waveform for playback */
  667. err = aw86927_ram_init(haptics);
  668. if (err)
  669. return dev_err_probe(haptics->dev, err, "Failed to init aw86927 sram\n");
  670. err = input_register_device(haptics->input_dev);
  671. if (err)
  672. return dev_err_probe(haptics->dev, err, "Failed to register input device\n");
  673. return 0;
  674. }
  675. static const struct of_device_id aw86927_of_id[] = {
  676. { .compatible = "awinic,aw86927" },
  677. { /* sentinel */ }
  678. };
  679. MODULE_DEVICE_TABLE(of, aw86927_of_id);
  680. static struct i2c_driver aw86927_driver = {
  681. .driver = {
  682. .name = "aw86927-haptics",
  683. .of_match_table = aw86927_of_id,
  684. },
  685. .probe = aw86927_probe,
  686. };
  687. module_i2c_driver(aw86927_driver);
  688. MODULE_AUTHOR("Griffin Kroah-Hartman <griffin.kroah@fairphone.com>");
  689. MODULE_DESCRIPTION("AWINIC AW86927 LRA Haptic Driver");
  690. MODULE_LICENSE("GPL");