mtk-pmic-keys.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2017 MediaTek, Inc.
  4. *
  5. * Author: Chen Zhong <chen.zhong@mediatek.com>
  6. */
  7. #include <linux/input.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mfd/mt6323/registers.h>
  11. #include <linux/mfd/mt6331/registers.h>
  12. #include <linux/mfd/mt6357/registers.h>
  13. #include <linux/mfd/mt6358/registers.h>
  14. #include <linux/mfd/mt6359/registers.h>
  15. #include <linux/mfd/mt6397/core.h>
  16. #include <linux/mfd/mt6397/registers.h>
  17. #include <linux/module.h>
  18. #include <linux/of_device.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/regmap.h>
  22. #define MTK_PMIC_RST_DU_MASK GENMASK(9, 8)
  23. #define MTK_PMIC_PWRKEY_RST BIT(6)
  24. #define MTK_PMIC_HOMEKEY_RST BIT(5)
  25. #define MTK_PMIC_MT6331_RST_DU_MASK GENMASK(13, 12)
  26. #define MTK_PMIC_MT6331_PWRKEY_RST BIT(9)
  27. #define MTK_PMIC_MT6331_HOMEKEY_RST BIT(8)
  28. #define MTK_PMIC_PWRKEY_INDEX 0
  29. #define MTK_PMIC_HOMEKEY_INDEX 1
  30. #define MTK_PMIC_MAX_KEY_COUNT 2
  31. struct mtk_pmic_keys_regs {
  32. u32 deb_reg;
  33. u32 deb_mask;
  34. u32 intsel_reg;
  35. u32 intsel_mask;
  36. u32 rst_en_mask;
  37. };
  38. #define MTK_PMIC_KEYS_REGS(_deb_reg, _deb_mask, \
  39. _intsel_reg, _intsel_mask, _rst_mask) \
  40. { \
  41. .deb_reg = _deb_reg, \
  42. .deb_mask = _deb_mask, \
  43. .intsel_reg = _intsel_reg, \
  44. .intsel_mask = _intsel_mask, \
  45. .rst_en_mask = _rst_mask, \
  46. }
  47. struct mtk_pmic_regs {
  48. const struct mtk_pmic_keys_regs keys_regs[MTK_PMIC_MAX_KEY_COUNT];
  49. u32 pmic_rst_reg;
  50. u32 rst_lprst_mask; /* Long-press reset timeout bitmask */
  51. bool key_release_irq;
  52. };
  53. static const struct mtk_pmic_regs mt6397_regs = {
  54. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  55. MTK_PMIC_KEYS_REGS(MT6397_CHRSTATUS,
  56. 0x8, MT6397_INT_RSV, 0x10, MTK_PMIC_PWRKEY_RST),
  57. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  58. MTK_PMIC_KEYS_REGS(MT6397_OCSTATUS2,
  59. 0x10, MT6397_INT_RSV, 0x8, MTK_PMIC_HOMEKEY_RST),
  60. .pmic_rst_reg = MT6397_TOP_RST_MISC,
  61. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  62. };
  63. static const struct mtk_pmic_regs mt6323_regs = {
  64. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  65. MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS,
  66. 0x2, MT6323_INT_MISC_CON, 0x10, MTK_PMIC_PWRKEY_RST),
  67. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  68. MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS,
  69. 0x4, MT6323_INT_MISC_CON, 0x8, MTK_PMIC_HOMEKEY_RST),
  70. .pmic_rst_reg = MT6323_TOP_RST_MISC,
  71. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  72. };
  73. static const struct mtk_pmic_regs mt6331_regs = {
  74. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  75. MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x2,
  76. MT6331_INT_MISC_CON, 0x4,
  77. MTK_PMIC_MT6331_PWRKEY_RST),
  78. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  79. MTK_PMIC_KEYS_REGS(MT6331_TOPSTATUS, 0x4,
  80. MT6331_INT_MISC_CON, 0x2,
  81. MTK_PMIC_MT6331_HOMEKEY_RST),
  82. .pmic_rst_reg = MT6331_TOP_RST_MISC,
  83. .rst_lprst_mask = MTK_PMIC_MT6331_RST_DU_MASK,
  84. };
  85. static const struct mtk_pmic_regs mt6357_regs = {
  86. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  87. MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
  88. 0x2, MT6357_PSC_TOP_INT_CON0, 0x5,
  89. MTK_PMIC_PWRKEY_RST),
  90. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  91. MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS,
  92. 0x8, MT6357_PSC_TOP_INT_CON0, 0xa,
  93. MTK_PMIC_HOMEKEY_INDEX),
  94. .pmic_rst_reg = MT6357_TOP_RST_MISC,
  95. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  96. };
  97. static const struct mtk_pmic_regs mt6358_regs = {
  98. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  99. MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS,
  100. 0x2, MT6358_PSC_TOP_INT_CON0, 0x5,
  101. MTK_PMIC_PWRKEY_RST),
  102. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  103. MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS,
  104. 0x8, MT6358_PSC_TOP_INT_CON0, 0xa,
  105. MTK_PMIC_HOMEKEY_RST),
  106. .pmic_rst_reg = MT6358_TOP_RST_MISC,
  107. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  108. .key_release_irq = true,
  109. };
  110. static const struct mtk_pmic_regs mt6359_regs = {
  111. .keys_regs[MTK_PMIC_PWRKEY_INDEX] =
  112. MTK_PMIC_KEYS_REGS(MT6359_TOPSTATUS,
  113. 0x2, MT6359_PSC_TOP_INT_CON0, 0x5,
  114. MTK_PMIC_PWRKEY_RST),
  115. .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =
  116. MTK_PMIC_KEYS_REGS(MT6359_TOPSTATUS,
  117. 0x8, MT6359_PSC_TOP_INT_CON0, 0xa,
  118. MTK_PMIC_HOMEKEY_RST),
  119. .pmic_rst_reg = MT6359_TOP_RST_MISC,
  120. .rst_lprst_mask = MTK_PMIC_RST_DU_MASK,
  121. .key_release_irq = true,
  122. };
  123. struct mtk_pmic_keys_info {
  124. struct mtk_pmic_keys *keys;
  125. const struct mtk_pmic_keys_regs *regs;
  126. unsigned int keycode;
  127. int irq;
  128. int irq_r; /* optional: release irq if different */
  129. bool wakeup:1;
  130. };
  131. struct mtk_pmic_keys {
  132. struct input_dev *input_dev;
  133. struct device *dev;
  134. struct regmap *regmap;
  135. struct mtk_pmic_keys_info keys[MTK_PMIC_MAX_KEY_COUNT];
  136. };
  137. enum mtk_pmic_keys_lp_mode {
  138. LP_DISABLE,
  139. LP_ONEKEY,
  140. LP_TWOKEY,
  141. };
  142. static void mtk_pmic_keys_lp_reset_setup(struct mtk_pmic_keys *keys,
  143. const struct mtk_pmic_regs *regs)
  144. {
  145. const struct mtk_pmic_keys_regs *kregs_home, *kregs_pwr;
  146. u32 long_press_mode, long_press_debounce;
  147. u32 value, mask;
  148. int error;
  149. kregs_home = &regs->keys_regs[MTK_PMIC_HOMEKEY_INDEX];
  150. kregs_pwr = &regs->keys_regs[MTK_PMIC_PWRKEY_INDEX];
  151. error = of_property_read_u32(keys->dev->of_node, "power-off-time-sec",
  152. &long_press_debounce);
  153. if (error)
  154. long_press_debounce = 0;
  155. mask = regs->rst_lprst_mask;
  156. value = long_press_debounce << (ffs(regs->rst_lprst_mask) - 1);
  157. error = of_property_read_u32(keys->dev->of_node,
  158. "mediatek,long-press-mode",
  159. &long_press_mode);
  160. if (error)
  161. long_press_mode = LP_DISABLE;
  162. switch (long_press_mode) {
  163. case LP_TWOKEY:
  164. value |= kregs_home->rst_en_mask;
  165. fallthrough;
  166. case LP_ONEKEY:
  167. value |= kregs_pwr->rst_en_mask;
  168. fallthrough;
  169. case LP_DISABLE:
  170. mask |= kregs_home->rst_en_mask;
  171. mask |= kregs_pwr->rst_en_mask;
  172. break;
  173. default:
  174. break;
  175. }
  176. regmap_update_bits(keys->regmap, regs->pmic_rst_reg, mask, value);
  177. }
  178. static irqreturn_t mtk_pmic_keys_irq_handler_thread(int irq, void *data)
  179. {
  180. struct mtk_pmic_keys_info *info = data;
  181. u32 key_deb, pressed;
  182. regmap_read(info->keys->regmap, info->regs->deb_reg, &key_deb);
  183. key_deb &= info->regs->deb_mask;
  184. pressed = !key_deb;
  185. input_report_key(info->keys->input_dev, info->keycode, pressed);
  186. input_sync(info->keys->input_dev);
  187. dev_dbg(info->keys->dev, "(%s) key =%d using PMIC\n",
  188. pressed ? "pressed" : "released", info->keycode);
  189. return IRQ_HANDLED;
  190. }
  191. static int mtk_pmic_key_setup(struct mtk_pmic_keys *keys,
  192. struct mtk_pmic_keys_info *info)
  193. {
  194. int ret;
  195. info->keys = keys;
  196. ret = regmap_update_bits(keys->regmap, info->regs->intsel_reg,
  197. info->regs->intsel_mask,
  198. info->regs->intsel_mask);
  199. if (ret < 0)
  200. return ret;
  201. ret = devm_request_threaded_irq(keys->dev, info->irq, NULL,
  202. mtk_pmic_keys_irq_handler_thread,
  203. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  204. "mtk-pmic-keys", info);
  205. if (ret) {
  206. dev_err(keys->dev, "Failed to request IRQ: %d: %d\n",
  207. info->irq, ret);
  208. return ret;
  209. }
  210. if (info->irq_r > 0) {
  211. ret = devm_request_threaded_irq(keys->dev, info->irq_r, NULL,
  212. mtk_pmic_keys_irq_handler_thread,
  213. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  214. "mtk-pmic-keys", info);
  215. if (ret) {
  216. dev_err(keys->dev, "Failed to request IRQ_r: %d: %d\n",
  217. info->irq, ret);
  218. return ret;
  219. }
  220. }
  221. input_set_capability(keys->input_dev, EV_KEY, info->keycode);
  222. return 0;
  223. }
  224. static int mtk_pmic_keys_suspend(struct device *dev)
  225. {
  226. struct mtk_pmic_keys *keys = dev_get_drvdata(dev);
  227. int index;
  228. for (index = 0; index < MTK_PMIC_MAX_KEY_COUNT; index++) {
  229. if (keys->keys[index].wakeup) {
  230. enable_irq_wake(keys->keys[index].irq);
  231. if (keys->keys[index].irq_r > 0)
  232. enable_irq_wake(keys->keys[index].irq_r);
  233. }
  234. }
  235. return 0;
  236. }
  237. static int mtk_pmic_keys_resume(struct device *dev)
  238. {
  239. struct mtk_pmic_keys *keys = dev_get_drvdata(dev);
  240. int index;
  241. for (index = 0; index < MTK_PMIC_MAX_KEY_COUNT; index++) {
  242. if (keys->keys[index].wakeup) {
  243. disable_irq_wake(keys->keys[index].irq);
  244. if (keys->keys[index].irq_r > 0)
  245. disable_irq_wake(keys->keys[index].irq_r);
  246. }
  247. }
  248. return 0;
  249. }
  250. static DEFINE_SIMPLE_DEV_PM_OPS(mtk_pmic_keys_pm_ops, mtk_pmic_keys_suspend,
  251. mtk_pmic_keys_resume);
  252. static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = {
  253. {
  254. .compatible = "mediatek,mt6397-keys",
  255. .data = &mt6397_regs,
  256. }, {
  257. .compatible = "mediatek,mt6323-keys",
  258. .data = &mt6323_regs,
  259. }, {
  260. .compatible = "mediatek,mt6331-keys",
  261. .data = &mt6331_regs,
  262. }, {
  263. .compatible = "mediatek,mt6357-keys",
  264. .data = &mt6357_regs,
  265. }, {
  266. .compatible = "mediatek,mt6358-keys",
  267. .data = &mt6358_regs,
  268. }, {
  269. .compatible = "mediatek,mt6359-keys",
  270. .data = &mt6359_regs,
  271. }, {
  272. /* sentinel */
  273. }
  274. };
  275. MODULE_DEVICE_TABLE(of, of_mtk_pmic_keys_match_tbl);
  276. static int mtk_pmic_keys_probe(struct platform_device *pdev)
  277. {
  278. int error, index = 0;
  279. unsigned int keycount;
  280. struct mt6397_chip *pmic_chip = dev_get_drvdata(pdev->dev.parent);
  281. struct device_node *node = pdev->dev.of_node;
  282. static const char *const irqnames[] = { "powerkey", "homekey" };
  283. static const char *const irqnames_r[] = { "powerkey_r", "homekey_r" };
  284. struct mtk_pmic_keys *keys;
  285. const struct mtk_pmic_regs *mtk_pmic_regs;
  286. struct input_dev *input_dev;
  287. const struct of_device_id *of_id =
  288. of_match_device(of_mtk_pmic_keys_match_tbl, &pdev->dev);
  289. keys = devm_kzalloc(&pdev->dev, sizeof(*keys), GFP_KERNEL);
  290. if (!keys)
  291. return -ENOMEM;
  292. keys->dev = &pdev->dev;
  293. keys->regmap = pmic_chip->regmap;
  294. mtk_pmic_regs = of_id->data;
  295. keys->input_dev = input_dev = devm_input_allocate_device(keys->dev);
  296. if (!input_dev) {
  297. dev_err(keys->dev, "input allocate device fail.\n");
  298. return -ENOMEM;
  299. }
  300. input_dev->name = "mtk-pmic-keys";
  301. input_dev->id.bustype = BUS_HOST;
  302. input_dev->id.vendor = 0x0001;
  303. input_dev->id.product = 0x0001;
  304. input_dev->id.version = 0x0001;
  305. keycount = of_get_available_child_count(node);
  306. if (keycount > MTK_PMIC_MAX_KEY_COUNT ||
  307. keycount > ARRAY_SIZE(irqnames)) {
  308. dev_err(keys->dev, "too many keys defined (%d)\n", keycount);
  309. return -EINVAL;
  310. }
  311. for_each_child_of_node_scoped(node, child) {
  312. keys->keys[index].regs = &mtk_pmic_regs->keys_regs[index];
  313. keys->keys[index].irq =
  314. platform_get_irq_byname(pdev, irqnames[index]);
  315. if (keys->keys[index].irq < 0)
  316. return keys->keys[index].irq;
  317. if (mtk_pmic_regs->key_release_irq) {
  318. keys->keys[index].irq_r = platform_get_irq_byname(pdev,
  319. irqnames_r[index]);
  320. if (keys->keys[index].irq_r < 0)
  321. return keys->keys[index].irq_r;
  322. }
  323. error = of_property_read_u32(child,
  324. "linux,keycodes", &keys->keys[index].keycode);
  325. if (error) {
  326. dev_err(keys->dev,
  327. "failed to read key:%d linux,keycode property: %d\n",
  328. index, error);
  329. return error;
  330. }
  331. if (of_property_read_bool(child, "wakeup-source"))
  332. keys->keys[index].wakeup = true;
  333. error = mtk_pmic_key_setup(keys, &keys->keys[index]);
  334. if (error)
  335. return error;
  336. index++;
  337. }
  338. error = input_register_device(input_dev);
  339. if (error) {
  340. dev_err(&pdev->dev,
  341. "register input device failed (%d)\n", error);
  342. return error;
  343. }
  344. mtk_pmic_keys_lp_reset_setup(keys, mtk_pmic_regs);
  345. platform_set_drvdata(pdev, keys);
  346. return 0;
  347. }
  348. static struct platform_driver pmic_keys_pdrv = {
  349. .probe = mtk_pmic_keys_probe,
  350. .driver = {
  351. .name = "mtk-pmic-keys",
  352. .of_match_table = of_mtk_pmic_keys_match_tbl,
  353. .pm = pm_sleep_ptr(&mtk_pmic_keys_pm_ops),
  354. },
  355. };
  356. module_platform_driver(pmic_keys_pdrv);
  357. MODULE_LICENSE("GPL v2");
  358. MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
  359. MODULE_DESCRIPTION("MTK pmic-keys driver v0.1");