ocrdma_verbs.c 78 KB

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  1. /* This file is part of the Emulex RoCE Device Driver for
  2. * RoCE (RDMA over Converged Ethernet) adapters.
  3. * Copyright (C) 2012-2015 Emulex. All rights reserved.
  4. * EMULEX and SLI are trademarks of Emulex.
  5. * www.emulex.com
  6. *
  7. * This software is available to you under a choice of one of two licenses.
  8. * You may choose to be licensed under the terms of the GNU General Public
  9. * License (GPL) Version 2, available from the file COPYING in the main
  10. * directory of this source tree, or the BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or without
  13. * modification, are permitted provided that the following conditions
  14. * are met:
  15. *
  16. * - Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above copyright
  20. * notice, this list of conditions and the following disclaimer in
  21. * the documentation and/or other materials provided with the distribution.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
  25. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26. * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  27. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  30. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  31. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  32. * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
  33. * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. * Contact Information:
  36. * linux-drivers@emulex.com
  37. *
  38. * Emulex
  39. * 3333 Susan Street
  40. * Costa Mesa, CA 92626
  41. */
  42. #include <linux/dma-mapping.h>
  43. #include <net/addrconf.h>
  44. #include <rdma/ib_verbs.h>
  45. #include <rdma/ib_user_verbs.h>
  46. #include <rdma/iw_cm.h>
  47. #include <rdma/ib_umem.h>
  48. #include <rdma/ib_addr.h>
  49. #include <rdma/ib_cache.h>
  50. #include <rdma/uverbs_ioctl.h>
  51. #include "ocrdma.h"
  52. #include "ocrdma_hw.h"
  53. #include "ocrdma_verbs.h"
  54. #include <rdma/ocrdma-abi.h>
  55. int ocrdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index, u16 *pkey)
  56. {
  57. if (index > 0)
  58. return -EINVAL;
  59. *pkey = 0xffff;
  60. return 0;
  61. }
  62. int ocrdma_query_device(struct ib_device *ibdev, struct ib_device_attr *attr,
  63. struct ib_udata *uhw)
  64. {
  65. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  66. if (uhw->inlen || uhw->outlen)
  67. return -EINVAL;
  68. memset(attr, 0, sizeof *attr);
  69. memcpy(&attr->fw_ver, &dev->attr.fw_ver[0],
  70. min(sizeof(dev->attr.fw_ver), sizeof(attr->fw_ver)));
  71. addrconf_addr_eui48((u8 *)&attr->sys_image_guid,
  72. dev->nic_info.mac_addr);
  73. attr->max_mr_size = dev->attr.max_mr_size;
  74. attr->page_size_cap = 0xffff000;
  75. attr->vendor_id = dev->nic_info.pdev->vendor;
  76. attr->vendor_part_id = dev->nic_info.pdev->device;
  77. attr->hw_ver = dev->asic_id;
  78. attr->max_qp = dev->attr.max_qp;
  79. attr->max_ah = OCRDMA_MAX_AH;
  80. attr->max_qp_wr = dev->attr.max_wqe;
  81. attr->device_cap_flags = IB_DEVICE_CURR_QP_STATE_MOD |
  82. IB_DEVICE_RC_RNR_NAK_GEN |
  83. IB_DEVICE_SHUTDOWN_PORT |
  84. IB_DEVICE_SYS_IMAGE_GUID |
  85. IB_DEVICE_MEM_MGT_EXTENSIONS;
  86. attr->kernel_cap_flags = IBK_LOCAL_DMA_LKEY;
  87. attr->max_send_sge = dev->attr.max_send_sge;
  88. attr->max_recv_sge = dev->attr.max_recv_sge;
  89. attr->max_sge_rd = dev->attr.max_rdma_sge;
  90. attr->max_cq = dev->attr.max_cq;
  91. attr->max_cqe = dev->attr.max_cqe;
  92. attr->max_mr = dev->attr.max_mr;
  93. attr->max_mw = dev->attr.max_mw;
  94. attr->max_pd = dev->attr.max_pd;
  95. attr->atomic_cap = 0;
  96. attr->max_qp_rd_atom =
  97. min(dev->attr.max_ord_per_qp, dev->attr.max_ird_per_qp);
  98. attr->max_qp_init_rd_atom = dev->attr.max_ord_per_qp;
  99. attr->max_srq = dev->attr.max_srq;
  100. attr->max_srq_sge = dev->attr.max_srq_sge;
  101. attr->max_srq_wr = dev->attr.max_rqe;
  102. attr->local_ca_ack_delay = dev->attr.local_ca_ack_delay;
  103. attr->max_fast_reg_page_list_len = dev->attr.max_pages_per_frmr;
  104. attr->max_pkeys = 1;
  105. return 0;
  106. }
  107. static inline void get_link_speed_and_width(struct ocrdma_dev *dev,
  108. u16 *ib_speed, u8 *ib_width)
  109. {
  110. int status;
  111. u8 speed;
  112. status = ocrdma_mbx_get_link_speed(dev, &speed, NULL);
  113. if (status)
  114. speed = OCRDMA_PHYS_LINK_SPEED_ZERO;
  115. switch (speed) {
  116. case OCRDMA_PHYS_LINK_SPEED_1GBPS:
  117. *ib_speed = IB_SPEED_SDR;
  118. *ib_width = IB_WIDTH_1X;
  119. break;
  120. case OCRDMA_PHYS_LINK_SPEED_10GBPS:
  121. *ib_speed = IB_SPEED_QDR;
  122. *ib_width = IB_WIDTH_1X;
  123. break;
  124. case OCRDMA_PHYS_LINK_SPEED_20GBPS:
  125. *ib_speed = IB_SPEED_DDR;
  126. *ib_width = IB_WIDTH_4X;
  127. break;
  128. case OCRDMA_PHYS_LINK_SPEED_40GBPS:
  129. *ib_speed = IB_SPEED_QDR;
  130. *ib_width = IB_WIDTH_4X;
  131. break;
  132. default:
  133. /* Unsupported */
  134. *ib_speed = IB_SPEED_SDR;
  135. *ib_width = IB_WIDTH_1X;
  136. }
  137. }
  138. int ocrdma_query_port(struct ib_device *ibdev,
  139. u32 port, struct ib_port_attr *props)
  140. {
  141. enum ib_port_state port_state;
  142. struct ocrdma_dev *dev;
  143. struct net_device *netdev;
  144. /* props being zeroed by the caller, avoid zeroing it here */
  145. dev = get_ocrdma_dev(ibdev);
  146. netdev = dev->nic_info.netdev;
  147. if (netif_running(netdev) && netif_oper_up(netdev)) {
  148. port_state = IB_PORT_ACTIVE;
  149. props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
  150. } else {
  151. port_state = IB_PORT_DOWN;
  152. props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
  153. }
  154. props->max_mtu = IB_MTU_4096;
  155. props->active_mtu = iboe_get_mtu(netdev->mtu);
  156. props->lid = 0;
  157. props->lmc = 0;
  158. props->sm_lid = 0;
  159. props->sm_sl = 0;
  160. props->state = port_state;
  161. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  162. IB_PORT_DEVICE_MGMT_SUP |
  163. IB_PORT_VENDOR_CLASS_SUP;
  164. props->ip_gids = true;
  165. props->gid_tbl_len = OCRDMA_MAX_SGID;
  166. props->pkey_tbl_len = 1;
  167. props->bad_pkey_cntr = 0;
  168. props->qkey_viol_cntr = 0;
  169. get_link_speed_and_width(dev, &props->active_speed,
  170. &props->active_width);
  171. props->max_msg_sz = 0x80000000;
  172. props->max_vl_num = 4;
  173. return 0;
  174. }
  175. static int ocrdma_add_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  176. unsigned long len)
  177. {
  178. struct ocrdma_mm *mm;
  179. mm = kzalloc_obj(*mm);
  180. if (mm == NULL)
  181. return -ENOMEM;
  182. mm->key.phy_addr = phy_addr;
  183. mm->key.len = len;
  184. INIT_LIST_HEAD(&mm->entry);
  185. mutex_lock(&uctx->mm_list_lock);
  186. list_add_tail(&mm->entry, &uctx->mm_head);
  187. mutex_unlock(&uctx->mm_list_lock);
  188. return 0;
  189. }
  190. static void ocrdma_del_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  191. unsigned long len)
  192. {
  193. struct ocrdma_mm *mm, *tmp;
  194. mutex_lock(&uctx->mm_list_lock);
  195. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  196. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  197. continue;
  198. list_del(&mm->entry);
  199. kfree(mm);
  200. break;
  201. }
  202. mutex_unlock(&uctx->mm_list_lock);
  203. }
  204. static bool ocrdma_search_mmap(struct ocrdma_ucontext *uctx, u64 phy_addr,
  205. unsigned long len)
  206. {
  207. bool found = false;
  208. struct ocrdma_mm *mm;
  209. mutex_lock(&uctx->mm_list_lock);
  210. list_for_each_entry(mm, &uctx->mm_head, entry) {
  211. if (len != mm->key.len && phy_addr != mm->key.phy_addr)
  212. continue;
  213. found = true;
  214. break;
  215. }
  216. mutex_unlock(&uctx->mm_list_lock);
  217. return found;
  218. }
  219. static u16 _ocrdma_pd_mgr_get_bitmap(struct ocrdma_dev *dev, bool dpp_pool)
  220. {
  221. u16 pd_bitmap_idx = 0;
  222. unsigned long *pd_bitmap;
  223. if (dpp_pool) {
  224. pd_bitmap = dev->pd_mgr->pd_dpp_bitmap;
  225. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  226. dev->pd_mgr->max_dpp_pd);
  227. __set_bit(pd_bitmap_idx, pd_bitmap);
  228. dev->pd_mgr->pd_dpp_count++;
  229. if (dev->pd_mgr->pd_dpp_count > dev->pd_mgr->pd_dpp_thrsh)
  230. dev->pd_mgr->pd_dpp_thrsh = dev->pd_mgr->pd_dpp_count;
  231. } else {
  232. pd_bitmap = dev->pd_mgr->pd_norm_bitmap;
  233. pd_bitmap_idx = find_first_zero_bit(pd_bitmap,
  234. dev->pd_mgr->max_normal_pd);
  235. __set_bit(pd_bitmap_idx, pd_bitmap);
  236. dev->pd_mgr->pd_norm_count++;
  237. if (dev->pd_mgr->pd_norm_count > dev->pd_mgr->pd_norm_thrsh)
  238. dev->pd_mgr->pd_norm_thrsh = dev->pd_mgr->pd_norm_count;
  239. }
  240. return pd_bitmap_idx;
  241. }
  242. static int _ocrdma_pd_mgr_put_bitmap(struct ocrdma_dev *dev, u16 pd_id,
  243. bool dpp_pool)
  244. {
  245. u16 pd_count;
  246. u16 pd_bit_index;
  247. pd_count = dpp_pool ? dev->pd_mgr->pd_dpp_count :
  248. dev->pd_mgr->pd_norm_count;
  249. if (pd_count == 0)
  250. return -EINVAL;
  251. if (dpp_pool) {
  252. pd_bit_index = pd_id - dev->pd_mgr->pd_dpp_start;
  253. if (pd_bit_index >= dev->pd_mgr->max_dpp_pd) {
  254. return -EINVAL;
  255. } else {
  256. __clear_bit(pd_bit_index, dev->pd_mgr->pd_dpp_bitmap);
  257. dev->pd_mgr->pd_dpp_count--;
  258. }
  259. } else {
  260. pd_bit_index = pd_id - dev->pd_mgr->pd_norm_start;
  261. if (pd_bit_index >= dev->pd_mgr->max_normal_pd) {
  262. return -EINVAL;
  263. } else {
  264. __clear_bit(pd_bit_index, dev->pd_mgr->pd_norm_bitmap);
  265. dev->pd_mgr->pd_norm_count--;
  266. }
  267. }
  268. return 0;
  269. }
  270. static int ocrdma_put_pd_num(struct ocrdma_dev *dev, u16 pd_id,
  271. bool dpp_pool)
  272. {
  273. int status;
  274. mutex_lock(&dev->dev_lock);
  275. status = _ocrdma_pd_mgr_put_bitmap(dev, pd_id, dpp_pool);
  276. mutex_unlock(&dev->dev_lock);
  277. return status;
  278. }
  279. static int ocrdma_get_pd_num(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
  280. {
  281. u16 pd_idx = 0;
  282. int status = 0;
  283. mutex_lock(&dev->dev_lock);
  284. if (pd->dpp_enabled) {
  285. /* try allocating DPP PD, if not available then normal PD */
  286. if (dev->pd_mgr->pd_dpp_count < dev->pd_mgr->max_dpp_pd) {
  287. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, true);
  288. pd->id = dev->pd_mgr->pd_dpp_start + pd_idx;
  289. pd->dpp_page = dev->pd_mgr->dpp_page_index + pd_idx;
  290. } else if (dev->pd_mgr->pd_norm_count <
  291. dev->pd_mgr->max_normal_pd) {
  292. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  293. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  294. pd->dpp_enabled = false;
  295. } else {
  296. status = -EINVAL;
  297. }
  298. } else {
  299. if (dev->pd_mgr->pd_norm_count < dev->pd_mgr->max_normal_pd) {
  300. pd_idx = _ocrdma_pd_mgr_get_bitmap(dev, false);
  301. pd->id = dev->pd_mgr->pd_norm_start + pd_idx;
  302. } else {
  303. status = -EINVAL;
  304. }
  305. }
  306. mutex_unlock(&dev->dev_lock);
  307. return status;
  308. }
  309. /*
  310. * NOTE:
  311. *
  312. * ocrdma_ucontext must be used here because this function is also
  313. * called from ocrdma_alloc_ucontext where ib_udata does not have
  314. * valid ib_ucontext pointer. ib_uverbs_get_context does not call
  315. * uobj_{alloc|get_xxx} helpers which are used to store the
  316. * ib_ucontext in uverbs_attr_bundle wrapping the ib_udata. so
  317. * ib_udata does NOT imply valid ib_ucontext here!
  318. */
  319. static int _ocrdma_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  320. struct ocrdma_ucontext *uctx,
  321. struct ib_udata *udata)
  322. {
  323. int status;
  324. if (udata && uctx && dev->attr.max_dpp_pds) {
  325. pd->dpp_enabled =
  326. ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R;
  327. pd->num_dpp_qp =
  328. pd->dpp_enabled ? (dev->nic_info.db_page_size /
  329. dev->attr.wqe_size) : 0;
  330. }
  331. if (dev->pd_mgr->pd_prealloc_valid)
  332. return ocrdma_get_pd_num(dev, pd);
  333. retry:
  334. status = ocrdma_mbx_alloc_pd(dev, pd);
  335. if (status) {
  336. if (pd->dpp_enabled) {
  337. pd->dpp_enabled = false;
  338. pd->num_dpp_qp = 0;
  339. goto retry;
  340. }
  341. return status;
  342. }
  343. return 0;
  344. }
  345. static inline int is_ucontext_pd(struct ocrdma_ucontext *uctx,
  346. struct ocrdma_pd *pd)
  347. {
  348. return (uctx->cntxt_pd == pd);
  349. }
  350. static void _ocrdma_dealloc_pd(struct ocrdma_dev *dev,
  351. struct ocrdma_pd *pd)
  352. {
  353. if (dev->pd_mgr->pd_prealloc_valid)
  354. ocrdma_put_pd_num(dev, pd->id, pd->dpp_enabled);
  355. else
  356. ocrdma_mbx_dealloc_pd(dev, pd);
  357. }
  358. static int ocrdma_alloc_ucontext_pd(struct ocrdma_dev *dev,
  359. struct ocrdma_ucontext *uctx,
  360. struct ib_udata *udata)
  361. {
  362. struct ib_device *ibdev = &dev->ibdev;
  363. struct ib_pd *pd;
  364. int status;
  365. pd = rdma_zalloc_drv_obj(ibdev, ib_pd);
  366. if (!pd)
  367. return -ENOMEM;
  368. pd->device = ibdev;
  369. uctx->cntxt_pd = get_ocrdma_pd(pd);
  370. status = _ocrdma_alloc_pd(dev, uctx->cntxt_pd, uctx, udata);
  371. if (status) {
  372. kfree(uctx->cntxt_pd);
  373. goto err;
  374. }
  375. uctx->cntxt_pd->uctx = uctx;
  376. uctx->cntxt_pd->ibpd.device = &dev->ibdev;
  377. err:
  378. return status;
  379. }
  380. static void ocrdma_dealloc_ucontext_pd(struct ocrdma_ucontext *uctx)
  381. {
  382. struct ocrdma_pd *pd = uctx->cntxt_pd;
  383. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  384. if (uctx->pd_in_use) {
  385. pr_err("%s(%d) Freeing in use pdid=0x%x.\n",
  386. __func__, dev->id, pd->id);
  387. }
  388. uctx->cntxt_pd = NULL;
  389. _ocrdma_dealloc_pd(dev, pd);
  390. kfree(pd);
  391. }
  392. static struct ocrdma_pd *ocrdma_get_ucontext_pd(struct ocrdma_ucontext *uctx)
  393. {
  394. struct ocrdma_pd *pd = NULL;
  395. mutex_lock(&uctx->mm_list_lock);
  396. if (!uctx->pd_in_use) {
  397. uctx->pd_in_use = true;
  398. pd = uctx->cntxt_pd;
  399. }
  400. mutex_unlock(&uctx->mm_list_lock);
  401. return pd;
  402. }
  403. static void ocrdma_release_ucontext_pd(struct ocrdma_ucontext *uctx)
  404. {
  405. mutex_lock(&uctx->mm_list_lock);
  406. uctx->pd_in_use = false;
  407. mutex_unlock(&uctx->mm_list_lock);
  408. }
  409. int ocrdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata)
  410. {
  411. struct ib_device *ibdev = uctx->device;
  412. int status;
  413. struct ocrdma_ucontext *ctx = get_ocrdma_ucontext(uctx);
  414. struct ocrdma_alloc_ucontext_resp resp = {};
  415. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  416. struct pci_dev *pdev = dev->nic_info.pdev;
  417. u32 map_len = roundup(sizeof(u32) * 2048, PAGE_SIZE);
  418. if (!udata)
  419. return -EFAULT;
  420. INIT_LIST_HEAD(&ctx->mm_head);
  421. mutex_init(&ctx->mm_list_lock);
  422. ctx->ah_tbl.va = dma_alloc_coherent(&pdev->dev, map_len,
  423. &ctx->ah_tbl.pa, GFP_KERNEL);
  424. if (!ctx->ah_tbl.va)
  425. return -ENOMEM;
  426. ctx->ah_tbl.len = map_len;
  427. resp.ah_tbl_len = ctx->ah_tbl.len;
  428. resp.ah_tbl_page = virt_to_phys(ctx->ah_tbl.va);
  429. status = ocrdma_add_mmap(ctx, resp.ah_tbl_page, resp.ah_tbl_len);
  430. if (status)
  431. goto map_err;
  432. status = ocrdma_alloc_ucontext_pd(dev, ctx, udata);
  433. if (status)
  434. goto pd_err;
  435. resp.dev_id = dev->id;
  436. resp.max_inline_data = dev->attr.max_inline_data;
  437. resp.wqe_size = dev->attr.wqe_size;
  438. resp.rqe_size = dev->attr.rqe_size;
  439. resp.dpp_wqe_size = dev->attr.wqe_size;
  440. memcpy(resp.fw_ver, dev->attr.fw_ver, sizeof(resp.fw_ver));
  441. status = ib_copy_to_udata(udata, &resp, sizeof(resp));
  442. if (status)
  443. goto cpy_err;
  444. return 0;
  445. cpy_err:
  446. ocrdma_dealloc_ucontext_pd(ctx);
  447. pd_err:
  448. ocrdma_del_mmap(ctx, ctx->ah_tbl.pa, ctx->ah_tbl.len);
  449. map_err:
  450. dma_free_coherent(&pdev->dev, ctx->ah_tbl.len, ctx->ah_tbl.va,
  451. ctx->ah_tbl.pa);
  452. return status;
  453. }
  454. void ocrdma_dealloc_ucontext(struct ib_ucontext *ibctx)
  455. {
  456. struct ocrdma_mm *mm, *tmp;
  457. struct ocrdma_ucontext *uctx = get_ocrdma_ucontext(ibctx);
  458. struct ocrdma_dev *dev = get_ocrdma_dev(ibctx->device);
  459. struct pci_dev *pdev = dev->nic_info.pdev;
  460. ocrdma_dealloc_ucontext_pd(uctx);
  461. ocrdma_del_mmap(uctx, uctx->ah_tbl.pa, uctx->ah_tbl.len);
  462. dma_free_coherent(&pdev->dev, uctx->ah_tbl.len, uctx->ah_tbl.va,
  463. uctx->ah_tbl.pa);
  464. list_for_each_entry_safe(mm, tmp, &uctx->mm_head, entry) {
  465. list_del(&mm->entry);
  466. kfree(mm);
  467. }
  468. }
  469. int ocrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  470. {
  471. struct ocrdma_ucontext *ucontext = get_ocrdma_ucontext(context);
  472. struct ocrdma_dev *dev = get_ocrdma_dev(context->device);
  473. unsigned long vm_page = vma->vm_pgoff << PAGE_SHIFT;
  474. u64 unmapped_db = (u64) dev->nic_info.unmapped_db;
  475. unsigned long len = (vma->vm_end - vma->vm_start);
  476. int status;
  477. bool found;
  478. if (vma->vm_start & (PAGE_SIZE - 1))
  479. return -EINVAL;
  480. found = ocrdma_search_mmap(ucontext, vma->vm_pgoff << PAGE_SHIFT, len);
  481. if (!found)
  482. return -EINVAL;
  483. if ((vm_page >= unmapped_db) && (vm_page <= (unmapped_db +
  484. dev->nic_info.db_total_size)) &&
  485. (len <= dev->nic_info.db_page_size)) {
  486. if (vma->vm_flags & VM_READ)
  487. return -EPERM;
  488. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  489. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  490. len, vma->vm_page_prot);
  491. } else if (dev->nic_info.dpp_unmapped_len &&
  492. (vm_page >= (u64) dev->nic_info.dpp_unmapped_addr) &&
  493. (vm_page <= (u64) (dev->nic_info.dpp_unmapped_addr +
  494. dev->nic_info.dpp_unmapped_len)) &&
  495. (len <= dev->nic_info.dpp_unmapped_len)) {
  496. if (vma->vm_flags & VM_READ)
  497. return -EPERM;
  498. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  499. status = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  500. len, vma->vm_page_prot);
  501. } else {
  502. status = remap_pfn_range(vma, vma->vm_start,
  503. vma->vm_pgoff, len, vma->vm_page_prot);
  504. }
  505. return status;
  506. }
  507. static int ocrdma_copy_pd_uresp(struct ocrdma_dev *dev, struct ocrdma_pd *pd,
  508. struct ib_udata *udata)
  509. {
  510. int status;
  511. u64 db_page_addr;
  512. u64 dpp_page_addr = 0;
  513. u32 db_page_size;
  514. struct ocrdma_alloc_pd_uresp rsp;
  515. struct ocrdma_ucontext *uctx = rdma_udata_to_drv_context(
  516. udata, struct ocrdma_ucontext, ibucontext);
  517. memset(&rsp, 0, sizeof(rsp));
  518. rsp.id = pd->id;
  519. rsp.dpp_enabled = pd->dpp_enabled;
  520. db_page_addr = ocrdma_get_db_addr(dev, pd->id);
  521. db_page_size = dev->nic_info.db_page_size;
  522. status = ocrdma_add_mmap(uctx, db_page_addr, db_page_size);
  523. if (status)
  524. return status;
  525. if (pd->dpp_enabled) {
  526. dpp_page_addr = dev->nic_info.dpp_unmapped_addr +
  527. (pd->id * PAGE_SIZE);
  528. status = ocrdma_add_mmap(uctx, dpp_page_addr,
  529. PAGE_SIZE);
  530. if (status)
  531. goto dpp_map_err;
  532. rsp.dpp_page_addr_hi = upper_32_bits(dpp_page_addr);
  533. rsp.dpp_page_addr_lo = dpp_page_addr;
  534. }
  535. status = ib_copy_to_udata(udata, &rsp, sizeof(rsp));
  536. if (status)
  537. goto ucopy_err;
  538. pd->uctx = uctx;
  539. return 0;
  540. ucopy_err:
  541. if (pd->dpp_enabled)
  542. ocrdma_del_mmap(pd->uctx, dpp_page_addr, PAGE_SIZE);
  543. dpp_map_err:
  544. ocrdma_del_mmap(pd->uctx, db_page_addr, db_page_size);
  545. return status;
  546. }
  547. int ocrdma_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  548. {
  549. struct ib_device *ibdev = ibpd->device;
  550. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  551. struct ocrdma_pd *pd;
  552. int status;
  553. u8 is_uctx_pd = false;
  554. struct ocrdma_ucontext *uctx = rdma_udata_to_drv_context(
  555. udata, struct ocrdma_ucontext, ibucontext);
  556. if (udata) {
  557. pd = ocrdma_get_ucontext_pd(uctx);
  558. if (pd) {
  559. is_uctx_pd = true;
  560. goto pd_mapping;
  561. }
  562. }
  563. pd = get_ocrdma_pd(ibpd);
  564. status = _ocrdma_alloc_pd(dev, pd, uctx, udata);
  565. if (status)
  566. goto exit;
  567. pd_mapping:
  568. if (udata) {
  569. status = ocrdma_copy_pd_uresp(dev, pd, udata);
  570. if (status)
  571. goto err;
  572. }
  573. return 0;
  574. err:
  575. if (is_uctx_pd)
  576. ocrdma_release_ucontext_pd(uctx);
  577. else
  578. _ocrdma_dealloc_pd(dev, pd);
  579. exit:
  580. return status;
  581. }
  582. int ocrdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
  583. {
  584. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  585. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  586. struct ocrdma_ucontext *uctx = NULL;
  587. u64 usr_db;
  588. uctx = pd->uctx;
  589. if (uctx) {
  590. u64 dpp_db = dev->nic_info.dpp_unmapped_addr +
  591. (pd->id * PAGE_SIZE);
  592. if (pd->dpp_enabled)
  593. ocrdma_del_mmap(pd->uctx, dpp_db, PAGE_SIZE);
  594. usr_db = ocrdma_get_db_addr(dev, pd->id);
  595. ocrdma_del_mmap(pd->uctx, usr_db, dev->nic_info.db_page_size);
  596. if (is_ucontext_pd(uctx, pd)) {
  597. ocrdma_release_ucontext_pd(uctx);
  598. return 0;
  599. }
  600. }
  601. _ocrdma_dealloc_pd(dev, pd);
  602. return 0;
  603. }
  604. static int ocrdma_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  605. u32 pdid, int acc, u32 num_pbls, u32 addr_check)
  606. {
  607. int status;
  608. mr->hwmr.fr_mr = 0;
  609. mr->hwmr.local_rd = 1;
  610. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  611. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  612. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  613. mr->hwmr.mw_bind = (acc & IB_ACCESS_MW_BIND) ? 1 : 0;
  614. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  615. mr->hwmr.num_pbls = num_pbls;
  616. status = ocrdma_mbx_alloc_lkey(dev, &mr->hwmr, pdid, addr_check);
  617. if (status)
  618. return status;
  619. mr->ibmr.lkey = mr->hwmr.lkey;
  620. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  621. mr->ibmr.rkey = mr->hwmr.lkey;
  622. return 0;
  623. }
  624. struct ib_mr *ocrdma_get_dma_mr(struct ib_pd *ibpd, int acc)
  625. {
  626. int status;
  627. struct ocrdma_mr *mr;
  628. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  629. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  630. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE)) {
  631. pr_err("%s err, invalid access rights\n", __func__);
  632. return ERR_PTR(-EINVAL);
  633. }
  634. mr = kzalloc_obj(*mr);
  635. if (!mr)
  636. return ERR_PTR(-ENOMEM);
  637. status = ocrdma_alloc_lkey(dev, mr, pd->id, acc, 0,
  638. OCRDMA_ADDR_CHECK_DISABLE);
  639. if (status) {
  640. kfree(mr);
  641. return ERR_PTR(status);
  642. }
  643. return &mr->ibmr;
  644. }
  645. static void ocrdma_free_mr_pbl_tbl(struct ocrdma_dev *dev,
  646. struct ocrdma_hw_mr *mr)
  647. {
  648. struct pci_dev *pdev = dev->nic_info.pdev;
  649. int i = 0;
  650. if (mr->pbl_table) {
  651. for (i = 0; i < mr->num_pbls; i++) {
  652. if (!mr->pbl_table[i].va)
  653. continue;
  654. dma_free_coherent(&pdev->dev, mr->pbl_size,
  655. mr->pbl_table[i].va,
  656. mr->pbl_table[i].pa);
  657. }
  658. kfree(mr->pbl_table);
  659. mr->pbl_table = NULL;
  660. }
  661. }
  662. static int ocrdma_get_pbl_info(struct ocrdma_dev *dev, struct ocrdma_mr *mr,
  663. u32 num_pbes)
  664. {
  665. u32 num_pbls = 0;
  666. u32 idx = 0;
  667. int status = 0;
  668. u32 pbl_size;
  669. do {
  670. pbl_size = OCRDMA_MIN_HPAGE_SIZE * (1 << idx);
  671. if (pbl_size > MAX_OCRDMA_PBL_SIZE) {
  672. status = -EFAULT;
  673. break;
  674. }
  675. num_pbls = roundup(num_pbes, (pbl_size / sizeof(u64)));
  676. num_pbls = num_pbls / (pbl_size / sizeof(u64));
  677. idx++;
  678. } while (num_pbls >= dev->attr.max_num_mr_pbl);
  679. mr->hwmr.num_pbes = num_pbes;
  680. mr->hwmr.num_pbls = num_pbls;
  681. mr->hwmr.pbl_size = pbl_size;
  682. return status;
  683. }
  684. static int ocrdma_build_pbl_tbl(struct ocrdma_dev *dev, struct ocrdma_hw_mr *mr)
  685. {
  686. int status = 0;
  687. int i;
  688. u32 dma_len = mr->pbl_size;
  689. struct pci_dev *pdev = dev->nic_info.pdev;
  690. void *va;
  691. dma_addr_t pa;
  692. mr->pbl_table = kzalloc_objs(struct ocrdma_pbl, mr->num_pbls);
  693. if (!mr->pbl_table)
  694. return -ENOMEM;
  695. for (i = 0; i < mr->num_pbls; i++) {
  696. va = dma_alloc_coherent(&pdev->dev, dma_len, &pa, GFP_KERNEL);
  697. if (!va) {
  698. ocrdma_free_mr_pbl_tbl(dev, mr);
  699. status = -ENOMEM;
  700. break;
  701. }
  702. mr->pbl_table[i].va = va;
  703. mr->pbl_table[i].pa = pa;
  704. }
  705. return status;
  706. }
  707. static void build_user_pbes(struct ocrdma_dev *dev, struct ocrdma_mr *mr)
  708. {
  709. struct ocrdma_pbe *pbe;
  710. struct ib_block_iter biter;
  711. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  712. int pbe_cnt;
  713. u64 pg_addr;
  714. if (!mr->hwmr.num_pbes)
  715. return;
  716. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  717. pbe_cnt = 0;
  718. rdma_umem_for_each_dma_block (mr->umem, &biter, PAGE_SIZE) {
  719. /* store the page address in pbe */
  720. pg_addr = rdma_block_iter_dma_address(&biter);
  721. pbe->pa_lo = cpu_to_le32(pg_addr);
  722. pbe->pa_hi = cpu_to_le32(upper_32_bits(pg_addr));
  723. pbe_cnt += 1;
  724. pbe++;
  725. /* if the given pbl is full storing the pbes,
  726. * move to next pbl.
  727. */
  728. if (pbe_cnt == (mr->hwmr.pbl_size / sizeof(u64))) {
  729. pbl_tbl++;
  730. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  731. pbe_cnt = 0;
  732. }
  733. }
  734. }
  735. struct ib_mr *ocrdma_reg_user_mr(struct ib_pd *ibpd, u64 start, u64 len,
  736. u64 usr_addr, int acc, struct ib_dmah *dmah,
  737. struct ib_udata *udata)
  738. {
  739. int status = -ENOMEM;
  740. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  741. struct ocrdma_mr *mr;
  742. struct ocrdma_pd *pd;
  743. if (dmah)
  744. return ERR_PTR(-EOPNOTSUPP);
  745. pd = get_ocrdma_pd(ibpd);
  746. if (acc & IB_ACCESS_REMOTE_WRITE && !(acc & IB_ACCESS_LOCAL_WRITE))
  747. return ERR_PTR(-EINVAL);
  748. mr = kzalloc_obj(*mr);
  749. if (!mr)
  750. return ERR_PTR(status);
  751. mr->umem = ib_umem_get(ibpd->device, start, len, acc);
  752. if (IS_ERR(mr->umem)) {
  753. status = -EFAULT;
  754. goto umem_err;
  755. }
  756. status = ocrdma_get_pbl_info(
  757. dev, mr, ib_umem_num_dma_blocks(mr->umem, PAGE_SIZE));
  758. if (status)
  759. goto umem_err;
  760. mr->hwmr.pbe_size = PAGE_SIZE;
  761. mr->hwmr.va = usr_addr;
  762. mr->hwmr.len = len;
  763. mr->hwmr.remote_wr = (acc & IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  764. mr->hwmr.remote_rd = (acc & IB_ACCESS_REMOTE_READ) ? 1 : 0;
  765. mr->hwmr.local_wr = (acc & IB_ACCESS_LOCAL_WRITE) ? 1 : 0;
  766. mr->hwmr.local_rd = 1;
  767. mr->hwmr.remote_atomic = (acc & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0;
  768. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  769. if (status)
  770. goto umem_err;
  771. build_user_pbes(dev, mr);
  772. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, acc);
  773. if (status)
  774. goto mbx_err;
  775. mr->ibmr.lkey = mr->hwmr.lkey;
  776. if (mr->hwmr.remote_wr || mr->hwmr.remote_rd)
  777. mr->ibmr.rkey = mr->hwmr.lkey;
  778. return &mr->ibmr;
  779. mbx_err:
  780. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  781. umem_err:
  782. kfree(mr);
  783. return ERR_PTR(status);
  784. }
  785. int ocrdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
  786. {
  787. struct ocrdma_mr *mr = get_ocrdma_mr(ib_mr);
  788. struct ocrdma_dev *dev = get_ocrdma_dev(ib_mr->device);
  789. (void) ocrdma_mbx_dealloc_lkey(dev, mr->hwmr.fr_mr, mr->hwmr.lkey);
  790. kfree(mr->pages);
  791. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  792. /* it could be user registered memory. */
  793. ib_umem_release(mr->umem);
  794. kfree(mr);
  795. /* Don't stop cleanup, in case FW is unresponsive */
  796. if (dev->mqe_ctx.fw_error_state) {
  797. pr_err("%s(%d) fw not responding.\n",
  798. __func__, dev->id);
  799. }
  800. return 0;
  801. }
  802. static int ocrdma_copy_cq_uresp(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
  803. struct ib_udata *udata)
  804. {
  805. int status;
  806. struct ocrdma_ucontext *uctx = rdma_udata_to_drv_context(
  807. udata, struct ocrdma_ucontext, ibucontext);
  808. struct ocrdma_create_cq_uresp uresp;
  809. /* this must be user flow! */
  810. if (!udata)
  811. return -EINVAL;
  812. memset(&uresp, 0, sizeof(uresp));
  813. uresp.cq_id = cq->id;
  814. uresp.page_size = PAGE_ALIGN(cq->len);
  815. uresp.num_pages = 1;
  816. uresp.max_hw_cqe = cq->max_hw_cqe;
  817. uresp.page_addr[0] = virt_to_phys(cq->va);
  818. uresp.db_page_addr = ocrdma_get_db_addr(dev, uctx->cntxt_pd->id);
  819. uresp.db_page_size = dev->nic_info.db_page_size;
  820. uresp.phase_change = cq->phase_change ? 1 : 0;
  821. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  822. if (status) {
  823. pr_err("%s(%d) copy error cqid=0x%x.\n",
  824. __func__, dev->id, cq->id);
  825. goto err;
  826. }
  827. status = ocrdma_add_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  828. if (status)
  829. goto err;
  830. status = ocrdma_add_mmap(uctx, uresp.page_addr[0], uresp.page_size);
  831. if (status) {
  832. ocrdma_del_mmap(uctx, uresp.db_page_addr, uresp.db_page_size);
  833. goto err;
  834. }
  835. cq->ucontext = uctx;
  836. err:
  837. return status;
  838. }
  839. int ocrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
  840. struct uverbs_attr_bundle *attrs)
  841. {
  842. struct ib_udata *udata = &attrs->driver_udata;
  843. struct ib_device *ibdev = ibcq->device;
  844. int entries = attr->cqe;
  845. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  846. struct ocrdma_dev *dev = get_ocrdma_dev(ibdev);
  847. struct ocrdma_ucontext *uctx = rdma_udata_to_drv_context(
  848. udata, struct ocrdma_ucontext, ibucontext);
  849. u16 pd_id = 0;
  850. int status;
  851. struct ocrdma_create_cq_ureq ureq;
  852. if (attr->flags)
  853. return -EOPNOTSUPP;
  854. if (udata) {
  855. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  856. return -EFAULT;
  857. } else
  858. ureq.dpp_cq = 0;
  859. spin_lock_init(&cq->cq_lock);
  860. spin_lock_init(&cq->comp_handler_lock);
  861. INIT_LIST_HEAD(&cq->sq_head);
  862. INIT_LIST_HEAD(&cq->rq_head);
  863. if (udata)
  864. pd_id = uctx->cntxt_pd->id;
  865. status = ocrdma_mbx_create_cq(dev, cq, entries, ureq.dpp_cq, pd_id);
  866. if (status)
  867. return status;
  868. if (udata) {
  869. status = ocrdma_copy_cq_uresp(dev, cq, udata);
  870. if (status)
  871. goto ctx_err;
  872. }
  873. cq->phase = OCRDMA_CQE_VALID;
  874. dev->cq_tbl[cq->id] = cq;
  875. return 0;
  876. ctx_err:
  877. ocrdma_mbx_destroy_cq(dev, cq);
  878. return status;
  879. }
  880. int ocrdma_resize_cq(struct ib_cq *ibcq, int new_cnt,
  881. struct ib_udata *udata)
  882. {
  883. int status = 0;
  884. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  885. if (new_cnt < 1 || new_cnt > cq->max_hw_cqe) {
  886. status = -EINVAL;
  887. return status;
  888. }
  889. ibcq->cqe = new_cnt;
  890. return status;
  891. }
  892. static void ocrdma_flush_cq(struct ocrdma_cq *cq)
  893. {
  894. int cqe_cnt;
  895. int valid_count = 0;
  896. unsigned long flags;
  897. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  898. struct ocrdma_cqe *cqe = NULL;
  899. cqe = cq->va;
  900. cqe_cnt = cq->cqe_cnt;
  901. /* Last irq might have scheduled a polling thread
  902. * sync-up with it before hard flushing.
  903. */
  904. spin_lock_irqsave(&cq->cq_lock, flags);
  905. while (cqe_cnt) {
  906. if (is_cqe_valid(cq, cqe))
  907. valid_count++;
  908. cqe++;
  909. cqe_cnt--;
  910. }
  911. ocrdma_ring_cq_db(dev, cq->id, false, false, valid_count);
  912. spin_unlock_irqrestore(&cq->cq_lock, flags);
  913. }
  914. int ocrdma_destroy_cq(struct ib_cq *ibcq, struct ib_udata *udata)
  915. {
  916. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  917. struct ocrdma_eq *eq = NULL;
  918. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  919. int pdid = 0;
  920. u32 irq, indx;
  921. dev->cq_tbl[cq->id] = NULL;
  922. indx = ocrdma_get_eq_table_index(dev, cq->eqn);
  923. eq = &dev->eq_tbl[indx];
  924. irq = ocrdma_get_irq(dev, eq);
  925. synchronize_irq(irq);
  926. ocrdma_flush_cq(cq);
  927. ocrdma_mbx_destroy_cq(dev, cq);
  928. if (cq->ucontext) {
  929. pdid = cq->ucontext->cntxt_pd->id;
  930. ocrdma_del_mmap(cq->ucontext, (u64) cq->pa,
  931. PAGE_ALIGN(cq->len));
  932. ocrdma_del_mmap(cq->ucontext,
  933. ocrdma_get_db_addr(dev, pdid),
  934. dev->nic_info.db_page_size);
  935. }
  936. return 0;
  937. }
  938. static int ocrdma_add_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  939. {
  940. int status = -EINVAL;
  941. if (qp->id < OCRDMA_MAX_QP && dev->qp_tbl[qp->id] == NULL) {
  942. dev->qp_tbl[qp->id] = qp;
  943. status = 0;
  944. }
  945. return status;
  946. }
  947. static void ocrdma_del_qpn_map(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
  948. {
  949. dev->qp_tbl[qp->id] = NULL;
  950. }
  951. static int ocrdma_check_qp_params(struct ib_pd *ibpd, struct ocrdma_dev *dev,
  952. struct ib_qp_init_attr *attrs,
  953. struct ib_udata *udata)
  954. {
  955. if ((attrs->qp_type != IB_QPT_GSI) &&
  956. (attrs->qp_type != IB_QPT_RC) &&
  957. (attrs->qp_type != IB_QPT_UC) &&
  958. (attrs->qp_type != IB_QPT_UD)) {
  959. pr_err("%s(%d) unsupported qp type=0x%x requested\n",
  960. __func__, dev->id, attrs->qp_type);
  961. return -EOPNOTSUPP;
  962. }
  963. /* Skip the check for QP1 to support CM size of 128 */
  964. if ((attrs->qp_type != IB_QPT_GSI) &&
  965. (attrs->cap.max_send_wr > dev->attr.max_wqe)) {
  966. pr_err("%s(%d) unsupported send_wr=0x%x requested\n",
  967. __func__, dev->id, attrs->cap.max_send_wr);
  968. pr_err("%s(%d) supported send_wr=0x%x\n",
  969. __func__, dev->id, dev->attr.max_wqe);
  970. return -EINVAL;
  971. }
  972. if (!attrs->srq && (attrs->cap.max_recv_wr > dev->attr.max_rqe)) {
  973. pr_err("%s(%d) unsupported recv_wr=0x%x requested\n",
  974. __func__, dev->id, attrs->cap.max_recv_wr);
  975. pr_err("%s(%d) supported recv_wr=0x%x\n",
  976. __func__, dev->id, dev->attr.max_rqe);
  977. return -EINVAL;
  978. }
  979. if (attrs->cap.max_inline_data > dev->attr.max_inline_data) {
  980. pr_err("%s(%d) unsupported inline data size=0x%x requested\n",
  981. __func__, dev->id, attrs->cap.max_inline_data);
  982. pr_err("%s(%d) supported inline data size=0x%x\n",
  983. __func__, dev->id, dev->attr.max_inline_data);
  984. return -EINVAL;
  985. }
  986. if (attrs->cap.max_send_sge > dev->attr.max_send_sge) {
  987. pr_err("%s(%d) unsupported send_sge=0x%x requested\n",
  988. __func__, dev->id, attrs->cap.max_send_sge);
  989. pr_err("%s(%d) supported send_sge=0x%x\n",
  990. __func__, dev->id, dev->attr.max_send_sge);
  991. return -EINVAL;
  992. }
  993. if (attrs->cap.max_recv_sge > dev->attr.max_recv_sge) {
  994. pr_err("%s(%d) unsupported recv_sge=0x%x requested\n",
  995. __func__, dev->id, attrs->cap.max_recv_sge);
  996. pr_err("%s(%d) supported recv_sge=0x%x\n",
  997. __func__, dev->id, dev->attr.max_recv_sge);
  998. return -EINVAL;
  999. }
  1000. /* unprivileged user space cannot create special QP */
  1001. if (udata && attrs->qp_type == IB_QPT_GSI) {
  1002. pr_err
  1003. ("%s(%d) Userspace can't create special QPs of type=0x%x\n",
  1004. __func__, dev->id, attrs->qp_type);
  1005. return -EINVAL;
  1006. }
  1007. /* allow creating only one GSI type of QP */
  1008. if (attrs->qp_type == IB_QPT_GSI && dev->gsi_qp_created) {
  1009. pr_err("%s(%d) GSI special QPs already created.\n",
  1010. __func__, dev->id);
  1011. return -EINVAL;
  1012. }
  1013. /* verify consumer QPs are not trying to use GSI QP's CQ */
  1014. if ((attrs->qp_type != IB_QPT_GSI) && (dev->gsi_qp_created)) {
  1015. if ((dev->gsi_sqcq == get_ocrdma_cq(attrs->send_cq)) ||
  1016. (dev->gsi_rqcq == get_ocrdma_cq(attrs->recv_cq))) {
  1017. pr_err("%s(%d) Consumer QP cannot use GSI CQs.\n",
  1018. __func__, dev->id);
  1019. return -EINVAL;
  1020. }
  1021. }
  1022. return 0;
  1023. }
  1024. static int ocrdma_copy_qp_uresp(struct ocrdma_qp *qp,
  1025. struct ib_udata *udata, int dpp_offset,
  1026. int dpp_credit_lmt, int srq)
  1027. {
  1028. int status;
  1029. u64 usr_db;
  1030. struct ocrdma_create_qp_uresp uresp;
  1031. struct ocrdma_pd *pd = qp->pd;
  1032. struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
  1033. memset(&uresp, 0, sizeof(uresp));
  1034. usr_db = dev->nic_info.unmapped_db +
  1035. (pd->id * dev->nic_info.db_page_size);
  1036. uresp.qp_id = qp->id;
  1037. uresp.sq_dbid = qp->sq.dbid;
  1038. uresp.num_sq_pages = 1;
  1039. uresp.sq_page_size = PAGE_ALIGN(qp->sq.len);
  1040. uresp.sq_page_addr[0] = virt_to_phys(qp->sq.va);
  1041. uresp.num_wqe_allocated = qp->sq.max_cnt;
  1042. if (!srq) {
  1043. uresp.rq_dbid = qp->rq.dbid;
  1044. uresp.num_rq_pages = 1;
  1045. uresp.rq_page_size = PAGE_ALIGN(qp->rq.len);
  1046. uresp.rq_page_addr[0] = virt_to_phys(qp->rq.va);
  1047. uresp.num_rqe_allocated = qp->rq.max_cnt;
  1048. }
  1049. uresp.db_page_addr = usr_db;
  1050. uresp.db_page_size = dev->nic_info.db_page_size;
  1051. uresp.db_sq_offset = OCRDMA_DB_GEN2_SQ_OFFSET;
  1052. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1053. uresp.db_shift = OCRDMA_DB_RQ_SHIFT;
  1054. if (qp->dpp_enabled) {
  1055. uresp.dpp_credit = dpp_credit_lmt;
  1056. uresp.dpp_offset = dpp_offset;
  1057. }
  1058. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1059. if (status) {
  1060. pr_err("%s(%d) user copy error.\n", __func__, dev->id);
  1061. goto err;
  1062. }
  1063. status = ocrdma_add_mmap(pd->uctx, uresp.sq_page_addr[0],
  1064. uresp.sq_page_size);
  1065. if (status)
  1066. goto err;
  1067. if (!srq) {
  1068. status = ocrdma_add_mmap(pd->uctx, uresp.rq_page_addr[0],
  1069. uresp.rq_page_size);
  1070. if (status)
  1071. goto rq_map_err;
  1072. }
  1073. return status;
  1074. rq_map_err:
  1075. ocrdma_del_mmap(pd->uctx, uresp.sq_page_addr[0], uresp.sq_page_size);
  1076. err:
  1077. return status;
  1078. }
  1079. static void ocrdma_set_qp_db(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
  1080. struct ocrdma_pd *pd)
  1081. {
  1082. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1083. qp->sq_db = dev->nic_info.db +
  1084. (pd->id * dev->nic_info.db_page_size) +
  1085. OCRDMA_DB_GEN2_SQ_OFFSET;
  1086. qp->rq_db = dev->nic_info.db +
  1087. (pd->id * dev->nic_info.db_page_size) +
  1088. OCRDMA_DB_GEN2_RQ_OFFSET;
  1089. } else {
  1090. qp->sq_db = dev->nic_info.db +
  1091. (pd->id * dev->nic_info.db_page_size) +
  1092. OCRDMA_DB_SQ_OFFSET;
  1093. qp->rq_db = dev->nic_info.db +
  1094. (pd->id * dev->nic_info.db_page_size) +
  1095. OCRDMA_DB_RQ_OFFSET;
  1096. }
  1097. }
  1098. static int ocrdma_alloc_wr_id_tbl(struct ocrdma_qp *qp)
  1099. {
  1100. qp->wqe_wr_id_tbl =
  1101. kzalloc_objs(*(qp->wqe_wr_id_tbl), qp->sq.max_cnt);
  1102. if (qp->wqe_wr_id_tbl == NULL)
  1103. return -ENOMEM;
  1104. qp->rqe_wr_id_tbl =
  1105. kcalloc(qp->rq.max_cnt, sizeof(u64), GFP_KERNEL);
  1106. if (qp->rqe_wr_id_tbl == NULL)
  1107. return -ENOMEM;
  1108. return 0;
  1109. }
  1110. static void ocrdma_set_qp_init_params(struct ocrdma_qp *qp,
  1111. struct ocrdma_pd *pd,
  1112. struct ib_qp_init_attr *attrs)
  1113. {
  1114. qp->pd = pd;
  1115. spin_lock_init(&qp->q_lock);
  1116. INIT_LIST_HEAD(&qp->sq_entry);
  1117. INIT_LIST_HEAD(&qp->rq_entry);
  1118. qp->qp_type = attrs->qp_type;
  1119. qp->cap_flags = OCRDMA_QP_INB_RD | OCRDMA_QP_INB_WR;
  1120. qp->max_inline_data = attrs->cap.max_inline_data;
  1121. qp->sq.max_sges = attrs->cap.max_send_sge;
  1122. qp->rq.max_sges = attrs->cap.max_recv_sge;
  1123. qp->state = OCRDMA_QPS_RST;
  1124. qp->signaled = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
  1125. }
  1126. static void ocrdma_store_gsi_qp_cq(struct ocrdma_dev *dev,
  1127. struct ib_qp_init_attr *attrs)
  1128. {
  1129. if (attrs->qp_type == IB_QPT_GSI) {
  1130. dev->gsi_qp_created = 1;
  1131. dev->gsi_sqcq = get_ocrdma_cq(attrs->send_cq);
  1132. dev->gsi_rqcq = get_ocrdma_cq(attrs->recv_cq);
  1133. }
  1134. }
  1135. int ocrdma_create_qp(struct ib_qp *ibqp, struct ib_qp_init_attr *attrs,
  1136. struct ib_udata *udata)
  1137. {
  1138. int status;
  1139. struct ib_pd *ibpd = ibqp->pd;
  1140. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  1141. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1142. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1143. struct ocrdma_create_qp_ureq ureq;
  1144. u16 dpp_credit_lmt, dpp_offset;
  1145. if (attrs->create_flags)
  1146. return -EOPNOTSUPP;
  1147. status = ocrdma_check_qp_params(ibpd, dev, attrs, udata);
  1148. if (status)
  1149. goto gen_err;
  1150. memset(&ureq, 0, sizeof(ureq));
  1151. if (udata) {
  1152. if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
  1153. return -EFAULT;
  1154. }
  1155. ocrdma_set_qp_init_params(qp, pd, attrs);
  1156. if (udata == NULL)
  1157. qp->cap_flags |= (OCRDMA_QP_MW_BIND | OCRDMA_QP_LKEY0 |
  1158. OCRDMA_QP_FAST_REG);
  1159. mutex_lock(&dev->dev_lock);
  1160. status = ocrdma_mbx_create_qp(qp, attrs, ureq.enable_dpp_cq,
  1161. ureq.dpp_cq_id,
  1162. &dpp_offset, &dpp_credit_lmt);
  1163. if (status)
  1164. goto mbx_err;
  1165. /* user space QP's wr_id table are managed in library */
  1166. if (udata == NULL) {
  1167. status = ocrdma_alloc_wr_id_tbl(qp);
  1168. if (status)
  1169. goto map_err;
  1170. }
  1171. status = ocrdma_add_qpn_map(dev, qp);
  1172. if (status)
  1173. goto map_err;
  1174. ocrdma_set_qp_db(dev, qp, pd);
  1175. if (udata) {
  1176. status = ocrdma_copy_qp_uresp(qp, udata, dpp_offset,
  1177. dpp_credit_lmt,
  1178. (attrs->srq != NULL));
  1179. if (status)
  1180. goto cpy_err;
  1181. }
  1182. ocrdma_store_gsi_qp_cq(dev, attrs);
  1183. qp->ibqp.qp_num = qp->id;
  1184. mutex_unlock(&dev->dev_lock);
  1185. return 0;
  1186. cpy_err:
  1187. ocrdma_del_qpn_map(dev, qp);
  1188. map_err:
  1189. ocrdma_mbx_destroy_qp(dev, qp);
  1190. mbx_err:
  1191. mutex_unlock(&dev->dev_lock);
  1192. kfree(qp->wqe_wr_id_tbl);
  1193. kfree(qp->rqe_wr_id_tbl);
  1194. pr_err("%s(%d) error=%d\n", __func__, dev->id, status);
  1195. gen_err:
  1196. return status;
  1197. }
  1198. int _ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1199. int attr_mask)
  1200. {
  1201. int status = 0;
  1202. struct ocrdma_qp *qp;
  1203. struct ocrdma_dev *dev;
  1204. enum ib_qp_state old_qps;
  1205. qp = get_ocrdma_qp(ibqp);
  1206. dev = get_ocrdma_dev(ibqp->device);
  1207. if (attr_mask & IB_QP_STATE)
  1208. status = ocrdma_qp_state_change(qp, attr->qp_state, &old_qps);
  1209. /* if new and previous states are same hw doesn't need to
  1210. * know about it.
  1211. */
  1212. if (status < 0)
  1213. return status;
  1214. return ocrdma_mbx_modify_qp(dev, qp, attr, attr_mask);
  1215. }
  1216. int ocrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1217. int attr_mask, struct ib_udata *udata)
  1218. {
  1219. unsigned long flags;
  1220. int status = -EINVAL;
  1221. struct ocrdma_qp *qp;
  1222. struct ocrdma_dev *dev;
  1223. enum ib_qp_state old_qps, new_qps;
  1224. if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
  1225. return -EOPNOTSUPP;
  1226. qp = get_ocrdma_qp(ibqp);
  1227. dev = get_ocrdma_dev(ibqp->device);
  1228. /* syncronize with multiple context trying to change, retrive qps */
  1229. mutex_lock(&dev->dev_lock);
  1230. /* syncronize with wqe, rqe posting and cqe processing contexts */
  1231. spin_lock_irqsave(&qp->q_lock, flags);
  1232. old_qps = get_ibqp_state(qp->state);
  1233. if (attr_mask & IB_QP_STATE)
  1234. new_qps = attr->qp_state;
  1235. else
  1236. new_qps = old_qps;
  1237. spin_unlock_irqrestore(&qp->q_lock, flags);
  1238. if (!ib_modify_qp_is_ok(old_qps, new_qps, ibqp->qp_type, attr_mask)) {
  1239. pr_err("%s(%d) invalid attribute mask=0x%x specified for\n"
  1240. "qpn=0x%x of type=0x%x old_qps=0x%x, new_qps=0x%x\n",
  1241. __func__, dev->id, attr_mask, qp->id, ibqp->qp_type,
  1242. old_qps, new_qps);
  1243. goto param_err;
  1244. }
  1245. status = _ocrdma_modify_qp(ibqp, attr, attr_mask);
  1246. if (status > 0)
  1247. status = 0;
  1248. param_err:
  1249. mutex_unlock(&dev->dev_lock);
  1250. return status;
  1251. }
  1252. static enum ib_mtu ocrdma_mtu_int_to_enum(u16 mtu)
  1253. {
  1254. switch (mtu) {
  1255. case 256:
  1256. return IB_MTU_256;
  1257. case 512:
  1258. return IB_MTU_512;
  1259. case 1024:
  1260. return IB_MTU_1024;
  1261. case 2048:
  1262. return IB_MTU_2048;
  1263. case 4096:
  1264. return IB_MTU_4096;
  1265. default:
  1266. return IB_MTU_1024;
  1267. }
  1268. }
  1269. static int ocrdma_to_ib_qp_acc_flags(int qp_cap_flags)
  1270. {
  1271. int ib_qp_acc_flags = 0;
  1272. if (qp_cap_flags & OCRDMA_QP_INB_WR)
  1273. ib_qp_acc_flags |= IB_ACCESS_REMOTE_WRITE;
  1274. if (qp_cap_flags & OCRDMA_QP_INB_RD)
  1275. ib_qp_acc_flags |= IB_ACCESS_LOCAL_WRITE;
  1276. return ib_qp_acc_flags;
  1277. }
  1278. int ocrdma_query_qp(struct ib_qp *ibqp,
  1279. struct ib_qp_attr *qp_attr,
  1280. int attr_mask, struct ib_qp_init_attr *qp_init_attr)
  1281. {
  1282. int status;
  1283. u32 qp_state;
  1284. struct ocrdma_qp_params params;
  1285. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1286. struct ocrdma_dev *dev = get_ocrdma_dev(ibqp->device);
  1287. memset(&params, 0, sizeof(params));
  1288. mutex_lock(&dev->dev_lock);
  1289. status = ocrdma_mbx_query_qp(dev, qp, &params);
  1290. mutex_unlock(&dev->dev_lock);
  1291. if (status)
  1292. goto mbx_err;
  1293. if (qp->qp_type == IB_QPT_UD)
  1294. qp_attr->qkey = params.qkey;
  1295. qp_attr->path_mtu =
  1296. ocrdma_mtu_int_to_enum(params.path_mtu_pkey_indx &
  1297. OCRDMA_QP_PARAMS_PATH_MTU_MASK) >>
  1298. OCRDMA_QP_PARAMS_PATH_MTU_SHIFT;
  1299. qp_attr->path_mig_state = IB_MIG_MIGRATED;
  1300. qp_attr->rq_psn = params.hop_lmt_rq_psn & OCRDMA_QP_PARAMS_RQ_PSN_MASK;
  1301. qp_attr->sq_psn = params.tclass_sq_psn & OCRDMA_QP_PARAMS_SQ_PSN_MASK;
  1302. qp_attr->dest_qp_num =
  1303. params.ack_to_rnr_rtc_dest_qpn & OCRDMA_QP_PARAMS_DEST_QPN_MASK;
  1304. qp_attr->qp_access_flags = ocrdma_to_ib_qp_acc_flags(qp->cap_flags);
  1305. qp_attr->cap.max_send_wr = qp->sq.max_cnt - 1;
  1306. qp_attr->cap.max_recv_wr = qp->rq.max_cnt - 1;
  1307. qp_attr->cap.max_send_sge = qp->sq.max_sges;
  1308. qp_attr->cap.max_recv_sge = qp->rq.max_sges;
  1309. qp_attr->cap.max_inline_data = qp->max_inline_data;
  1310. qp_init_attr->cap = qp_attr->cap;
  1311. qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
  1312. rdma_ah_set_grh(&qp_attr->ah_attr, NULL,
  1313. params.rnt_rc_sl_fl &
  1314. OCRDMA_QP_PARAMS_FLOW_LABEL_MASK,
  1315. qp->sgid_idx,
  1316. (params.hop_lmt_rq_psn &
  1317. OCRDMA_QP_PARAMS_HOP_LMT_MASK) >>
  1318. OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,
  1319. (params.tclass_sq_psn &
  1320. OCRDMA_QP_PARAMS_TCLASS_MASK) >>
  1321. OCRDMA_QP_PARAMS_TCLASS_SHIFT);
  1322. rdma_ah_set_dgid_raw(&qp_attr->ah_attr, &params.dgid[0]);
  1323. rdma_ah_set_port_num(&qp_attr->ah_attr, 1);
  1324. rdma_ah_set_sl(&qp_attr->ah_attr, (params.rnt_rc_sl_fl &
  1325. OCRDMA_QP_PARAMS_SL_MASK) >>
  1326. OCRDMA_QP_PARAMS_SL_SHIFT);
  1327. qp_attr->timeout = (params.ack_to_rnr_rtc_dest_qpn &
  1328. OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK) >>
  1329. OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
  1330. qp_attr->rnr_retry = (params.ack_to_rnr_rtc_dest_qpn &
  1331. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK) >>
  1332. OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT;
  1333. qp_attr->retry_cnt =
  1334. (params.rnt_rc_sl_fl & OCRDMA_QP_PARAMS_RETRY_CNT_MASK) >>
  1335. OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT;
  1336. qp_attr->min_rnr_timer = 0;
  1337. qp_attr->pkey_index = 0;
  1338. qp_attr->port_num = 1;
  1339. rdma_ah_set_path_bits(&qp_attr->ah_attr, 0);
  1340. rdma_ah_set_static_rate(&qp_attr->ah_attr, 0);
  1341. qp_attr->alt_pkey_index = 0;
  1342. qp_attr->alt_port_num = 0;
  1343. qp_attr->alt_timeout = 0;
  1344. memset(&qp_attr->alt_ah_attr, 0, sizeof(qp_attr->alt_ah_attr));
  1345. qp_state = (params.max_sge_recv_flags & OCRDMA_QP_PARAMS_STATE_MASK) >>
  1346. OCRDMA_QP_PARAMS_STATE_SHIFT;
  1347. qp_attr->qp_state = get_ibqp_state(qp_state);
  1348. qp_attr->cur_qp_state = qp_attr->qp_state;
  1349. qp_attr->sq_draining = (qp_state == OCRDMA_QPS_SQ_DRAINING) ? 1 : 0;
  1350. qp_attr->max_dest_rd_atomic =
  1351. params.max_ord_ird >> OCRDMA_QP_PARAMS_MAX_ORD_SHIFT;
  1352. qp_attr->max_rd_atomic =
  1353. params.max_ord_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK;
  1354. qp_attr->en_sqd_async_notify = (params.max_sge_recv_flags &
  1355. OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC) ? 1 : 0;
  1356. /* Sync driver QP state with FW */
  1357. ocrdma_qp_state_change(qp, qp_attr->qp_state, NULL);
  1358. mbx_err:
  1359. return status;
  1360. }
  1361. static void ocrdma_srq_toggle_bit(struct ocrdma_srq *srq, unsigned int idx)
  1362. {
  1363. unsigned int i = idx / 32;
  1364. u32 mask = (1U << (idx % 32));
  1365. srq->idx_bit_fields[i] ^= mask;
  1366. }
  1367. static int ocrdma_hwq_free_cnt(struct ocrdma_qp_hwq_info *q)
  1368. {
  1369. return ((q->max_wqe_idx - q->head) + q->tail) % q->max_cnt;
  1370. }
  1371. static int is_hw_sq_empty(struct ocrdma_qp *qp)
  1372. {
  1373. return (qp->sq.tail == qp->sq.head);
  1374. }
  1375. static int is_hw_rq_empty(struct ocrdma_qp *qp)
  1376. {
  1377. return (qp->rq.tail == qp->rq.head);
  1378. }
  1379. static void *ocrdma_hwq_head(struct ocrdma_qp_hwq_info *q)
  1380. {
  1381. return q->va + (q->head * q->entry_size);
  1382. }
  1383. static void *ocrdma_hwq_head_from_idx(struct ocrdma_qp_hwq_info *q,
  1384. u32 idx)
  1385. {
  1386. return q->va + (idx * q->entry_size);
  1387. }
  1388. static void ocrdma_hwq_inc_head(struct ocrdma_qp_hwq_info *q)
  1389. {
  1390. q->head = (q->head + 1) & q->max_wqe_idx;
  1391. }
  1392. static void ocrdma_hwq_inc_tail(struct ocrdma_qp_hwq_info *q)
  1393. {
  1394. q->tail = (q->tail + 1) & q->max_wqe_idx;
  1395. }
  1396. /* discard the cqe for a given QP */
  1397. static void ocrdma_discard_cqes(struct ocrdma_qp *qp, struct ocrdma_cq *cq)
  1398. {
  1399. unsigned long cq_flags;
  1400. unsigned long flags;
  1401. u32 cur_getp, stop_getp;
  1402. struct ocrdma_cqe *cqe;
  1403. u32 qpn = 0, wqe_idx = 0;
  1404. spin_lock_irqsave(&cq->cq_lock, cq_flags);
  1405. /* traverse through the CQEs in the hw CQ,
  1406. * find the matching CQE for a given qp,
  1407. * mark the matching one discarded by clearing qpn.
  1408. * ring the doorbell in the poll_cq() as
  1409. * we don't complete out of order cqe.
  1410. */
  1411. cur_getp = cq->getp;
  1412. /* find upto when do we reap the cq. */
  1413. stop_getp = cur_getp;
  1414. do {
  1415. if (is_hw_sq_empty(qp) && (!qp->srq && is_hw_rq_empty(qp)))
  1416. break;
  1417. cqe = cq->va + cur_getp;
  1418. /* if (a) done reaping whole hw cq, or
  1419. * (b) qp_xq becomes empty.
  1420. * then exit
  1421. */
  1422. qpn = cqe->cmn.qpn & OCRDMA_CQE_QPN_MASK;
  1423. /* if previously discarded cqe found, skip that too. */
  1424. /* check for matching qp */
  1425. if (qpn == 0 || qpn != qp->id)
  1426. goto skip_cqe;
  1427. if (is_cqe_for_sq(cqe)) {
  1428. ocrdma_hwq_inc_tail(&qp->sq);
  1429. } else {
  1430. if (qp->srq) {
  1431. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  1432. OCRDMA_CQE_BUFTAG_SHIFT) &
  1433. qp->srq->rq.max_wqe_idx;
  1434. BUG_ON(wqe_idx < 1);
  1435. spin_lock_irqsave(&qp->srq->q_lock, flags);
  1436. ocrdma_hwq_inc_tail(&qp->srq->rq);
  1437. ocrdma_srq_toggle_bit(qp->srq, wqe_idx - 1);
  1438. spin_unlock_irqrestore(&qp->srq->q_lock, flags);
  1439. } else {
  1440. ocrdma_hwq_inc_tail(&qp->rq);
  1441. }
  1442. }
  1443. /* mark cqe discarded so that it is not picked up later
  1444. * in the poll_cq().
  1445. */
  1446. cqe->cmn.qpn = 0;
  1447. skip_cqe:
  1448. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  1449. } while (cur_getp != stop_getp);
  1450. spin_unlock_irqrestore(&cq->cq_lock, cq_flags);
  1451. }
  1452. void ocrdma_del_flush_qp(struct ocrdma_qp *qp)
  1453. {
  1454. int found = false;
  1455. unsigned long flags;
  1456. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  1457. /* sync with any active CQ poll */
  1458. spin_lock_irqsave(&dev->flush_q_lock, flags);
  1459. found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
  1460. if (found)
  1461. list_del(&qp->sq_entry);
  1462. if (!qp->srq) {
  1463. found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
  1464. if (found)
  1465. list_del(&qp->rq_entry);
  1466. }
  1467. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  1468. }
  1469. int ocrdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
  1470. {
  1471. struct ocrdma_pd *pd;
  1472. struct ocrdma_qp *qp;
  1473. struct ocrdma_dev *dev;
  1474. struct ib_qp_attr attrs;
  1475. int attr_mask;
  1476. unsigned long flags;
  1477. qp = get_ocrdma_qp(ibqp);
  1478. dev = get_ocrdma_dev(ibqp->device);
  1479. pd = qp->pd;
  1480. /* change the QP state to ERROR */
  1481. if (qp->state != OCRDMA_QPS_RST) {
  1482. attrs.qp_state = IB_QPS_ERR;
  1483. attr_mask = IB_QP_STATE;
  1484. _ocrdma_modify_qp(ibqp, &attrs, attr_mask);
  1485. }
  1486. /* ensure that CQEs for newly created QP (whose id may be same with
  1487. * one which just getting destroyed are same), dont get
  1488. * discarded until the old CQEs are discarded.
  1489. */
  1490. mutex_lock(&dev->dev_lock);
  1491. (void) ocrdma_mbx_destroy_qp(dev, qp);
  1492. /*
  1493. * acquire CQ lock while destroy is in progress, in order to
  1494. * protect against proessing in-flight CQEs for this QP.
  1495. */
  1496. spin_lock_irqsave(&qp->sq_cq->cq_lock, flags);
  1497. if (qp->rq_cq && (qp->rq_cq != qp->sq_cq)) {
  1498. spin_lock(&qp->rq_cq->cq_lock);
  1499. ocrdma_del_qpn_map(dev, qp);
  1500. spin_unlock(&qp->rq_cq->cq_lock);
  1501. } else {
  1502. ocrdma_del_qpn_map(dev, qp);
  1503. }
  1504. spin_unlock_irqrestore(&qp->sq_cq->cq_lock, flags);
  1505. if (!pd->uctx) {
  1506. ocrdma_discard_cqes(qp, qp->sq_cq);
  1507. ocrdma_discard_cqes(qp, qp->rq_cq);
  1508. }
  1509. mutex_unlock(&dev->dev_lock);
  1510. if (pd->uctx) {
  1511. ocrdma_del_mmap(pd->uctx, (u64) qp->sq.pa,
  1512. PAGE_ALIGN(qp->sq.len));
  1513. if (!qp->srq)
  1514. ocrdma_del_mmap(pd->uctx, (u64) qp->rq.pa,
  1515. PAGE_ALIGN(qp->rq.len));
  1516. }
  1517. ocrdma_del_flush_qp(qp);
  1518. kfree(qp->wqe_wr_id_tbl);
  1519. kfree(qp->rqe_wr_id_tbl);
  1520. return 0;
  1521. }
  1522. static int ocrdma_copy_srq_uresp(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
  1523. struct ib_udata *udata)
  1524. {
  1525. int status;
  1526. struct ocrdma_create_srq_uresp uresp;
  1527. memset(&uresp, 0, sizeof(uresp));
  1528. uresp.rq_dbid = srq->rq.dbid;
  1529. uresp.num_rq_pages = 1;
  1530. uresp.rq_page_addr[0] = virt_to_phys(srq->rq.va);
  1531. uresp.rq_page_size = srq->rq.len;
  1532. uresp.db_page_addr = dev->nic_info.unmapped_db +
  1533. (srq->pd->id * dev->nic_info.db_page_size);
  1534. uresp.db_page_size = dev->nic_info.db_page_size;
  1535. uresp.num_rqe_allocated = srq->rq.max_cnt;
  1536. if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
  1537. uresp.db_rq_offset = OCRDMA_DB_GEN2_RQ_OFFSET;
  1538. uresp.db_shift = 24;
  1539. } else {
  1540. uresp.db_rq_offset = OCRDMA_DB_RQ_OFFSET;
  1541. uresp.db_shift = 16;
  1542. }
  1543. status = ib_copy_to_udata(udata, &uresp, sizeof(uresp));
  1544. if (status)
  1545. return status;
  1546. status = ocrdma_add_mmap(srq->pd->uctx, uresp.rq_page_addr[0],
  1547. uresp.rq_page_size);
  1548. if (status)
  1549. return status;
  1550. return status;
  1551. }
  1552. int ocrdma_create_srq(struct ib_srq *ibsrq, struct ib_srq_init_attr *init_attr,
  1553. struct ib_udata *udata)
  1554. {
  1555. int status;
  1556. struct ocrdma_pd *pd = get_ocrdma_pd(ibsrq->pd);
  1557. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1558. struct ocrdma_srq *srq = get_ocrdma_srq(ibsrq);
  1559. if (init_attr->srq_type != IB_SRQT_BASIC)
  1560. return -EOPNOTSUPP;
  1561. if (init_attr->attr.max_sge > dev->attr.max_recv_sge)
  1562. return -EINVAL;
  1563. if (init_attr->attr.max_wr > dev->attr.max_rqe)
  1564. return -EINVAL;
  1565. spin_lock_init(&srq->q_lock);
  1566. srq->pd = pd;
  1567. srq->db = dev->nic_info.db + (pd->id * dev->nic_info.db_page_size);
  1568. status = ocrdma_mbx_create_srq(dev, srq, init_attr, pd);
  1569. if (status)
  1570. return status;
  1571. if (!udata) {
  1572. srq->rqe_wr_id_tbl = kcalloc(srq->rq.max_cnt, sizeof(u64),
  1573. GFP_KERNEL);
  1574. if (!srq->rqe_wr_id_tbl) {
  1575. status = -ENOMEM;
  1576. goto arm_err;
  1577. }
  1578. srq->bit_fields_len = (srq->rq.max_cnt / 32) +
  1579. (srq->rq.max_cnt % 32 ? 1 : 0);
  1580. srq->idx_bit_fields =
  1581. kmalloc_array(srq->bit_fields_len, sizeof(u32),
  1582. GFP_KERNEL);
  1583. if (!srq->idx_bit_fields) {
  1584. status = -ENOMEM;
  1585. goto arm_err;
  1586. }
  1587. memset(srq->idx_bit_fields, 0xff,
  1588. srq->bit_fields_len * sizeof(u32));
  1589. }
  1590. if (init_attr->attr.srq_limit) {
  1591. status = ocrdma_mbx_modify_srq(srq, &init_attr->attr);
  1592. if (status)
  1593. goto arm_err;
  1594. }
  1595. if (udata) {
  1596. status = ocrdma_copy_srq_uresp(dev, srq, udata);
  1597. if (status)
  1598. goto arm_err;
  1599. }
  1600. return 0;
  1601. arm_err:
  1602. ocrdma_mbx_destroy_srq(dev, srq);
  1603. kfree(srq->rqe_wr_id_tbl);
  1604. kfree(srq->idx_bit_fields);
  1605. return status;
  1606. }
  1607. int ocrdma_modify_srq(struct ib_srq *ibsrq,
  1608. struct ib_srq_attr *srq_attr,
  1609. enum ib_srq_attr_mask srq_attr_mask,
  1610. struct ib_udata *udata)
  1611. {
  1612. int status;
  1613. struct ocrdma_srq *srq;
  1614. srq = get_ocrdma_srq(ibsrq);
  1615. if (srq_attr_mask & IB_SRQ_MAX_WR)
  1616. status = -EINVAL;
  1617. else
  1618. status = ocrdma_mbx_modify_srq(srq, srq_attr);
  1619. return status;
  1620. }
  1621. int ocrdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  1622. {
  1623. struct ocrdma_srq *srq;
  1624. srq = get_ocrdma_srq(ibsrq);
  1625. return ocrdma_mbx_query_srq(srq, srq_attr);
  1626. }
  1627. int ocrdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata)
  1628. {
  1629. struct ocrdma_srq *srq;
  1630. struct ocrdma_dev *dev = get_ocrdma_dev(ibsrq->device);
  1631. srq = get_ocrdma_srq(ibsrq);
  1632. ocrdma_mbx_destroy_srq(dev, srq);
  1633. if (srq->pd->uctx)
  1634. ocrdma_del_mmap(srq->pd->uctx, (u64) srq->rq.pa,
  1635. PAGE_ALIGN(srq->rq.len));
  1636. kfree(srq->idx_bit_fields);
  1637. kfree(srq->rqe_wr_id_tbl);
  1638. return 0;
  1639. }
  1640. /* unprivileged verbs and their support functions. */
  1641. static void ocrdma_build_ud_hdr(struct ocrdma_qp *qp,
  1642. struct ocrdma_hdr_wqe *hdr,
  1643. const struct ib_send_wr *wr)
  1644. {
  1645. struct ocrdma_ewqe_ud_hdr *ud_hdr =
  1646. (struct ocrdma_ewqe_ud_hdr *)(hdr + 1);
  1647. struct ocrdma_ah *ah = get_ocrdma_ah(ud_wr(wr)->ah);
  1648. ud_hdr->rsvd_dest_qpn = ud_wr(wr)->remote_qpn;
  1649. if (qp->qp_type == IB_QPT_GSI)
  1650. ud_hdr->qkey = qp->qkey;
  1651. else
  1652. ud_hdr->qkey = ud_wr(wr)->remote_qkey;
  1653. ud_hdr->rsvd_ahid = ah->id;
  1654. ud_hdr->hdr_type = ah->hdr_type;
  1655. if (ah->av->valid & OCRDMA_AV_VLAN_VALID)
  1656. hdr->cw |= (OCRDMA_FLAG_AH_VLAN_PR << OCRDMA_WQE_FLAGS_SHIFT);
  1657. }
  1658. static void ocrdma_build_sges(struct ocrdma_hdr_wqe *hdr,
  1659. struct ocrdma_sge *sge, int num_sge,
  1660. struct ib_sge *sg_list)
  1661. {
  1662. int i;
  1663. for (i = 0; i < num_sge; i++) {
  1664. sge[i].lrkey = sg_list[i].lkey;
  1665. sge[i].addr_lo = sg_list[i].addr;
  1666. sge[i].addr_hi = upper_32_bits(sg_list[i].addr);
  1667. sge[i].len = sg_list[i].length;
  1668. hdr->total_len += sg_list[i].length;
  1669. }
  1670. if (num_sge == 0)
  1671. memset(sge, 0, sizeof(*sge));
  1672. }
  1673. static inline uint32_t ocrdma_sglist_len(struct ib_sge *sg_list, int num_sge)
  1674. {
  1675. uint32_t total_len = 0, i;
  1676. for (i = 0; i < num_sge; i++)
  1677. total_len += sg_list[i].length;
  1678. return total_len;
  1679. }
  1680. static int ocrdma_build_inline_sges(struct ocrdma_qp *qp,
  1681. struct ocrdma_hdr_wqe *hdr,
  1682. struct ocrdma_sge *sge,
  1683. const struct ib_send_wr *wr, u32 wqe_size)
  1684. {
  1685. int i;
  1686. char *dpp_addr;
  1687. if (wr->send_flags & IB_SEND_INLINE && qp->qp_type != IB_QPT_UD) {
  1688. hdr->total_len = ocrdma_sglist_len(wr->sg_list, wr->num_sge);
  1689. if (unlikely(hdr->total_len > qp->max_inline_data)) {
  1690. pr_err("%s() supported_len=0x%x,\n"
  1691. " unsupported len req=0x%x\n", __func__,
  1692. qp->max_inline_data, hdr->total_len);
  1693. return -EINVAL;
  1694. }
  1695. dpp_addr = (char *)sge;
  1696. for (i = 0; i < wr->num_sge; i++) {
  1697. memcpy(dpp_addr,
  1698. (void *)(unsigned long)wr->sg_list[i].addr,
  1699. wr->sg_list[i].length);
  1700. dpp_addr += wr->sg_list[i].length;
  1701. }
  1702. wqe_size += roundup(hdr->total_len, OCRDMA_WQE_ALIGN_BYTES);
  1703. if (0 == hdr->total_len)
  1704. wqe_size += sizeof(struct ocrdma_sge);
  1705. hdr->cw |= (OCRDMA_TYPE_INLINE << OCRDMA_WQE_TYPE_SHIFT);
  1706. } else {
  1707. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1708. if (wr->num_sge)
  1709. wqe_size += (wr->num_sge * sizeof(struct ocrdma_sge));
  1710. else
  1711. wqe_size += sizeof(struct ocrdma_sge);
  1712. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1713. }
  1714. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1715. return 0;
  1716. }
  1717. static int ocrdma_build_send(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1718. const struct ib_send_wr *wr)
  1719. {
  1720. struct ocrdma_sge *sge;
  1721. u32 wqe_size = sizeof(*hdr);
  1722. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  1723. ocrdma_build_ud_hdr(qp, hdr, wr);
  1724. sge = (struct ocrdma_sge *)(hdr + 2);
  1725. wqe_size += sizeof(struct ocrdma_ewqe_ud_hdr);
  1726. } else {
  1727. sge = (struct ocrdma_sge *)(hdr + 1);
  1728. }
  1729. return ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1730. }
  1731. static int ocrdma_build_write(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1732. const struct ib_send_wr *wr)
  1733. {
  1734. int status;
  1735. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1736. struct ocrdma_sge *sge = ext_rw + 1;
  1737. u32 wqe_size = sizeof(*hdr) + sizeof(*ext_rw);
  1738. status = ocrdma_build_inline_sges(qp, hdr, sge, wr, wqe_size);
  1739. if (status)
  1740. return status;
  1741. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1742. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1743. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1744. ext_rw->len = hdr->total_len;
  1745. return 0;
  1746. }
  1747. static void ocrdma_build_read(struct ocrdma_qp *qp, struct ocrdma_hdr_wqe *hdr,
  1748. const struct ib_send_wr *wr)
  1749. {
  1750. struct ocrdma_sge *ext_rw = (struct ocrdma_sge *)(hdr + 1);
  1751. struct ocrdma_sge *sge = ext_rw + 1;
  1752. u32 wqe_size = ((wr->num_sge + 1) * sizeof(struct ocrdma_sge)) +
  1753. sizeof(struct ocrdma_hdr_wqe);
  1754. ocrdma_build_sges(hdr, sge, wr->num_sge, wr->sg_list);
  1755. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1756. hdr->cw |= (OCRDMA_READ << OCRDMA_WQE_OPCODE_SHIFT);
  1757. hdr->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1758. ext_rw->addr_lo = rdma_wr(wr)->remote_addr;
  1759. ext_rw->addr_hi = upper_32_bits(rdma_wr(wr)->remote_addr);
  1760. ext_rw->lrkey = rdma_wr(wr)->rkey;
  1761. ext_rw->len = hdr->total_len;
  1762. }
  1763. static int get_encoded_page_size(int pg_sz)
  1764. {
  1765. /* Max size is 256M 4096 << 16 */
  1766. int i = 0;
  1767. for (; i < 17; i++)
  1768. if (pg_sz == (4096 << i))
  1769. break;
  1770. return i;
  1771. }
  1772. static int ocrdma_build_reg(struct ocrdma_qp *qp,
  1773. struct ocrdma_hdr_wqe *hdr,
  1774. const struct ib_reg_wr *wr)
  1775. {
  1776. u64 fbo;
  1777. struct ocrdma_ewqe_fr *fast_reg = (struct ocrdma_ewqe_fr *)(hdr + 1);
  1778. struct ocrdma_mr *mr = get_ocrdma_mr(wr->mr);
  1779. struct ocrdma_pbl *pbl_tbl = mr->hwmr.pbl_table;
  1780. struct ocrdma_pbe *pbe;
  1781. u32 wqe_size = sizeof(*fast_reg) + sizeof(*hdr);
  1782. int num_pbes = 0, i;
  1783. wqe_size = roundup(wqe_size, OCRDMA_WQE_ALIGN_BYTES);
  1784. hdr->cw |= (OCRDMA_FR_MR << OCRDMA_WQE_OPCODE_SHIFT);
  1785. hdr->cw |= ((wqe_size / OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT);
  1786. if (wr->access & IB_ACCESS_LOCAL_WRITE)
  1787. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_LOCAL_WR;
  1788. if (wr->access & IB_ACCESS_REMOTE_WRITE)
  1789. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_WR;
  1790. if (wr->access & IB_ACCESS_REMOTE_READ)
  1791. hdr->rsvd_lkey_flags |= OCRDMA_LKEY_FLAG_REMOTE_RD;
  1792. hdr->lkey = wr->key;
  1793. hdr->total_len = mr->ibmr.length;
  1794. fbo = mr->ibmr.iova - mr->pages[0];
  1795. fast_reg->va_hi = upper_32_bits(mr->ibmr.iova);
  1796. fast_reg->va_lo = (u32) (mr->ibmr.iova & 0xffffffff);
  1797. fast_reg->fbo_hi = upper_32_bits(fbo);
  1798. fast_reg->fbo_lo = (u32) fbo & 0xffffffff;
  1799. fast_reg->num_sges = mr->npages;
  1800. fast_reg->size_sge = get_encoded_page_size(mr->ibmr.page_size);
  1801. pbe = pbl_tbl->va;
  1802. for (i = 0; i < mr->npages; i++) {
  1803. u64 buf_addr = mr->pages[i];
  1804. pbe->pa_lo = cpu_to_le32((u32) (buf_addr & PAGE_MASK));
  1805. pbe->pa_hi = cpu_to_le32((u32) upper_32_bits(buf_addr));
  1806. num_pbes += 1;
  1807. pbe++;
  1808. /* if the pbl is full storing the pbes,
  1809. * move to next pbl.
  1810. */
  1811. if (num_pbes == (mr->hwmr.pbl_size/sizeof(u64))) {
  1812. pbl_tbl++;
  1813. pbe = (struct ocrdma_pbe *)pbl_tbl->va;
  1814. }
  1815. }
  1816. return 0;
  1817. }
  1818. static void ocrdma_ring_sq_db(struct ocrdma_qp *qp)
  1819. {
  1820. u32 val = qp->sq.dbid | (1 << OCRDMA_DB_SQ_SHIFT);
  1821. iowrite32(val, qp->sq_db);
  1822. }
  1823. int ocrdma_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
  1824. const struct ib_send_wr **bad_wr)
  1825. {
  1826. int status = 0;
  1827. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1828. struct ocrdma_hdr_wqe *hdr;
  1829. unsigned long flags;
  1830. spin_lock_irqsave(&qp->q_lock, flags);
  1831. if (qp->state != OCRDMA_QPS_RTS && qp->state != OCRDMA_QPS_SQD) {
  1832. spin_unlock_irqrestore(&qp->q_lock, flags);
  1833. *bad_wr = wr;
  1834. return -EINVAL;
  1835. }
  1836. while (wr) {
  1837. if (qp->qp_type == IB_QPT_UD &&
  1838. (wr->opcode != IB_WR_SEND &&
  1839. wr->opcode != IB_WR_SEND_WITH_IMM)) {
  1840. *bad_wr = wr;
  1841. status = -EINVAL;
  1842. break;
  1843. }
  1844. if (ocrdma_hwq_free_cnt(&qp->sq) == 0 ||
  1845. wr->num_sge > qp->sq.max_sges) {
  1846. *bad_wr = wr;
  1847. status = -ENOMEM;
  1848. break;
  1849. }
  1850. hdr = ocrdma_hwq_head(&qp->sq);
  1851. hdr->cw = 0;
  1852. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1853. hdr->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1854. if (wr->send_flags & IB_SEND_FENCE)
  1855. hdr->cw |=
  1856. (OCRDMA_FLAG_FENCE_L << OCRDMA_WQE_FLAGS_SHIFT);
  1857. if (wr->send_flags & IB_SEND_SOLICITED)
  1858. hdr->cw |=
  1859. (OCRDMA_FLAG_SOLICIT << OCRDMA_WQE_FLAGS_SHIFT);
  1860. hdr->total_len = 0;
  1861. switch (wr->opcode) {
  1862. case IB_WR_SEND_WITH_IMM:
  1863. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1864. hdr->immdt = ntohl(wr->ex.imm_data);
  1865. fallthrough;
  1866. case IB_WR_SEND:
  1867. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1868. ocrdma_build_send(qp, hdr, wr);
  1869. break;
  1870. case IB_WR_SEND_WITH_INV:
  1871. hdr->cw |= (OCRDMA_FLAG_INV << OCRDMA_WQE_FLAGS_SHIFT);
  1872. hdr->cw |= (OCRDMA_SEND << OCRDMA_WQE_OPCODE_SHIFT);
  1873. hdr->lkey = wr->ex.invalidate_rkey;
  1874. status = ocrdma_build_send(qp, hdr, wr);
  1875. break;
  1876. case IB_WR_RDMA_WRITE_WITH_IMM:
  1877. hdr->cw |= (OCRDMA_FLAG_IMM << OCRDMA_WQE_FLAGS_SHIFT);
  1878. hdr->immdt = ntohl(wr->ex.imm_data);
  1879. fallthrough;
  1880. case IB_WR_RDMA_WRITE:
  1881. hdr->cw |= (OCRDMA_WRITE << OCRDMA_WQE_OPCODE_SHIFT);
  1882. status = ocrdma_build_write(qp, hdr, wr);
  1883. break;
  1884. case IB_WR_RDMA_READ:
  1885. ocrdma_build_read(qp, hdr, wr);
  1886. break;
  1887. case IB_WR_LOCAL_INV:
  1888. hdr->cw |=
  1889. (OCRDMA_LKEY_INV << OCRDMA_WQE_OPCODE_SHIFT);
  1890. hdr->cw |= ((sizeof(struct ocrdma_hdr_wqe) +
  1891. sizeof(struct ocrdma_sge)) /
  1892. OCRDMA_WQE_STRIDE) << OCRDMA_WQE_SIZE_SHIFT;
  1893. hdr->lkey = wr->ex.invalidate_rkey;
  1894. break;
  1895. case IB_WR_REG_MR:
  1896. status = ocrdma_build_reg(qp, hdr, reg_wr(wr));
  1897. break;
  1898. default:
  1899. status = -EINVAL;
  1900. break;
  1901. }
  1902. if (status) {
  1903. *bad_wr = wr;
  1904. break;
  1905. }
  1906. if (wr->send_flags & IB_SEND_SIGNALED || qp->signaled)
  1907. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 1;
  1908. else
  1909. qp->wqe_wr_id_tbl[qp->sq.head].signaled = 0;
  1910. qp->wqe_wr_id_tbl[qp->sq.head].wrid = wr->wr_id;
  1911. ocrdma_cpu_to_le32(hdr, ((hdr->cw >> OCRDMA_WQE_SIZE_SHIFT) &
  1912. OCRDMA_WQE_SIZE_MASK) * OCRDMA_WQE_STRIDE);
  1913. /* make sure wqe is written before adapter can access it */
  1914. wmb();
  1915. /* inform hw to start processing it */
  1916. ocrdma_ring_sq_db(qp);
  1917. /* update pointer, counter for next wr */
  1918. ocrdma_hwq_inc_head(&qp->sq);
  1919. wr = wr->next;
  1920. }
  1921. spin_unlock_irqrestore(&qp->q_lock, flags);
  1922. return status;
  1923. }
  1924. static void ocrdma_ring_rq_db(struct ocrdma_qp *qp)
  1925. {
  1926. u32 val = qp->rq.dbid | (1 << OCRDMA_DB_RQ_SHIFT);
  1927. iowrite32(val, qp->rq_db);
  1928. }
  1929. static void ocrdma_build_rqe(struct ocrdma_hdr_wqe *rqe,
  1930. const struct ib_recv_wr *wr, u16 tag)
  1931. {
  1932. u32 wqe_size = 0;
  1933. struct ocrdma_sge *sge;
  1934. if (wr->num_sge)
  1935. wqe_size = (wr->num_sge * sizeof(*sge)) + sizeof(*rqe);
  1936. else
  1937. wqe_size = sizeof(*sge) + sizeof(*rqe);
  1938. rqe->cw = ((wqe_size / OCRDMA_WQE_STRIDE) <<
  1939. OCRDMA_WQE_SIZE_SHIFT);
  1940. rqe->cw |= (OCRDMA_FLAG_SIG << OCRDMA_WQE_FLAGS_SHIFT);
  1941. rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
  1942. rqe->total_len = 0;
  1943. rqe->rsvd_tag = tag;
  1944. sge = (struct ocrdma_sge *)(rqe + 1);
  1945. ocrdma_build_sges(rqe, sge, wr->num_sge, wr->sg_list);
  1946. ocrdma_cpu_to_le32(rqe, wqe_size);
  1947. }
  1948. int ocrdma_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
  1949. const struct ib_recv_wr **bad_wr)
  1950. {
  1951. int status = 0;
  1952. unsigned long flags;
  1953. struct ocrdma_qp *qp = get_ocrdma_qp(ibqp);
  1954. struct ocrdma_hdr_wqe *rqe;
  1955. spin_lock_irqsave(&qp->q_lock, flags);
  1956. if (qp->state == OCRDMA_QPS_RST || qp->state == OCRDMA_QPS_ERR) {
  1957. spin_unlock_irqrestore(&qp->q_lock, flags);
  1958. *bad_wr = wr;
  1959. return -EINVAL;
  1960. }
  1961. while (wr) {
  1962. if (ocrdma_hwq_free_cnt(&qp->rq) == 0 ||
  1963. wr->num_sge > qp->rq.max_sges) {
  1964. *bad_wr = wr;
  1965. status = -ENOMEM;
  1966. break;
  1967. }
  1968. rqe = ocrdma_hwq_head(&qp->rq);
  1969. ocrdma_build_rqe(rqe, wr, 0);
  1970. qp->rqe_wr_id_tbl[qp->rq.head] = wr->wr_id;
  1971. /* make sure rqe is written before adapter can access it */
  1972. wmb();
  1973. /* inform hw to start processing it */
  1974. ocrdma_ring_rq_db(qp);
  1975. /* update pointer, counter for next wr */
  1976. ocrdma_hwq_inc_head(&qp->rq);
  1977. wr = wr->next;
  1978. }
  1979. spin_unlock_irqrestore(&qp->q_lock, flags);
  1980. return status;
  1981. }
  1982. /* cqe for srq's rqe can potentially arrive out of order.
  1983. * index gives the entry in the shadow table where to store
  1984. * the wr_id. tag/index is returned in cqe to reference back
  1985. * for a given rqe.
  1986. */
  1987. static int ocrdma_srq_get_idx(struct ocrdma_srq *srq)
  1988. {
  1989. int row = 0;
  1990. int indx = 0;
  1991. for (row = 0; row < srq->bit_fields_len; row++) {
  1992. if (srq->idx_bit_fields[row]) {
  1993. indx = ffs(srq->idx_bit_fields[row]);
  1994. indx = (row * 32) + (indx - 1);
  1995. BUG_ON(indx >= srq->rq.max_cnt);
  1996. ocrdma_srq_toggle_bit(srq, indx);
  1997. break;
  1998. }
  1999. }
  2000. BUG_ON(row == srq->bit_fields_len);
  2001. return indx + 1; /* Use from index 1 */
  2002. }
  2003. static void ocrdma_ring_srq_db(struct ocrdma_srq *srq)
  2004. {
  2005. u32 val = srq->rq.dbid | (1 << 16);
  2006. iowrite32(val, srq->db + OCRDMA_DB_GEN2_SRQ_OFFSET);
  2007. }
  2008. int ocrdma_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
  2009. const struct ib_recv_wr **bad_wr)
  2010. {
  2011. int status = 0;
  2012. unsigned long flags;
  2013. struct ocrdma_srq *srq;
  2014. struct ocrdma_hdr_wqe *rqe;
  2015. u16 tag;
  2016. srq = get_ocrdma_srq(ibsrq);
  2017. spin_lock_irqsave(&srq->q_lock, flags);
  2018. while (wr) {
  2019. if (ocrdma_hwq_free_cnt(&srq->rq) == 0 ||
  2020. wr->num_sge > srq->rq.max_sges) {
  2021. status = -ENOMEM;
  2022. *bad_wr = wr;
  2023. break;
  2024. }
  2025. tag = ocrdma_srq_get_idx(srq);
  2026. rqe = ocrdma_hwq_head(&srq->rq);
  2027. ocrdma_build_rqe(rqe, wr, tag);
  2028. srq->rqe_wr_id_tbl[tag] = wr->wr_id;
  2029. /* make sure rqe is written before adapter can perform DMA */
  2030. wmb();
  2031. /* inform hw to start processing it */
  2032. ocrdma_ring_srq_db(srq);
  2033. /* update pointer, counter for next wr */
  2034. ocrdma_hwq_inc_head(&srq->rq);
  2035. wr = wr->next;
  2036. }
  2037. spin_unlock_irqrestore(&srq->q_lock, flags);
  2038. return status;
  2039. }
  2040. static enum ib_wc_status ocrdma_to_ibwc_err(u16 status)
  2041. {
  2042. enum ib_wc_status ibwc_status;
  2043. switch (status) {
  2044. case OCRDMA_CQE_GENERAL_ERR:
  2045. ibwc_status = IB_WC_GENERAL_ERR;
  2046. break;
  2047. case OCRDMA_CQE_LOC_LEN_ERR:
  2048. ibwc_status = IB_WC_LOC_LEN_ERR;
  2049. break;
  2050. case OCRDMA_CQE_LOC_QP_OP_ERR:
  2051. ibwc_status = IB_WC_LOC_QP_OP_ERR;
  2052. break;
  2053. case OCRDMA_CQE_LOC_EEC_OP_ERR:
  2054. ibwc_status = IB_WC_LOC_EEC_OP_ERR;
  2055. break;
  2056. case OCRDMA_CQE_LOC_PROT_ERR:
  2057. ibwc_status = IB_WC_LOC_PROT_ERR;
  2058. break;
  2059. case OCRDMA_CQE_WR_FLUSH_ERR:
  2060. ibwc_status = IB_WC_WR_FLUSH_ERR;
  2061. break;
  2062. case OCRDMA_CQE_MW_BIND_ERR:
  2063. ibwc_status = IB_WC_MW_BIND_ERR;
  2064. break;
  2065. case OCRDMA_CQE_BAD_RESP_ERR:
  2066. ibwc_status = IB_WC_BAD_RESP_ERR;
  2067. break;
  2068. case OCRDMA_CQE_LOC_ACCESS_ERR:
  2069. ibwc_status = IB_WC_LOC_ACCESS_ERR;
  2070. break;
  2071. case OCRDMA_CQE_REM_INV_REQ_ERR:
  2072. ibwc_status = IB_WC_REM_INV_REQ_ERR;
  2073. break;
  2074. case OCRDMA_CQE_REM_ACCESS_ERR:
  2075. ibwc_status = IB_WC_REM_ACCESS_ERR;
  2076. break;
  2077. case OCRDMA_CQE_REM_OP_ERR:
  2078. ibwc_status = IB_WC_REM_OP_ERR;
  2079. break;
  2080. case OCRDMA_CQE_RETRY_EXC_ERR:
  2081. ibwc_status = IB_WC_RETRY_EXC_ERR;
  2082. break;
  2083. case OCRDMA_CQE_RNR_RETRY_EXC_ERR:
  2084. ibwc_status = IB_WC_RNR_RETRY_EXC_ERR;
  2085. break;
  2086. case OCRDMA_CQE_LOC_RDD_VIOL_ERR:
  2087. ibwc_status = IB_WC_LOC_RDD_VIOL_ERR;
  2088. break;
  2089. case OCRDMA_CQE_REM_INV_RD_REQ_ERR:
  2090. ibwc_status = IB_WC_REM_INV_RD_REQ_ERR;
  2091. break;
  2092. case OCRDMA_CQE_REM_ABORT_ERR:
  2093. ibwc_status = IB_WC_REM_ABORT_ERR;
  2094. break;
  2095. case OCRDMA_CQE_INV_EECN_ERR:
  2096. ibwc_status = IB_WC_INV_EECN_ERR;
  2097. break;
  2098. case OCRDMA_CQE_INV_EEC_STATE_ERR:
  2099. ibwc_status = IB_WC_INV_EEC_STATE_ERR;
  2100. break;
  2101. case OCRDMA_CQE_FATAL_ERR:
  2102. ibwc_status = IB_WC_FATAL_ERR;
  2103. break;
  2104. case OCRDMA_CQE_RESP_TIMEOUT_ERR:
  2105. ibwc_status = IB_WC_RESP_TIMEOUT_ERR;
  2106. break;
  2107. default:
  2108. ibwc_status = IB_WC_GENERAL_ERR;
  2109. break;
  2110. }
  2111. return ibwc_status;
  2112. }
  2113. static void ocrdma_update_wc(struct ocrdma_qp *qp, struct ib_wc *ibwc,
  2114. u32 wqe_idx)
  2115. {
  2116. struct ocrdma_hdr_wqe *hdr;
  2117. struct ocrdma_sge *rw;
  2118. int opcode;
  2119. hdr = ocrdma_hwq_head_from_idx(&qp->sq, wqe_idx);
  2120. ibwc->wr_id = qp->wqe_wr_id_tbl[wqe_idx].wrid;
  2121. /* Undo the hdr->cw swap */
  2122. opcode = le32_to_cpu(hdr->cw) & OCRDMA_WQE_OPCODE_MASK;
  2123. switch (opcode) {
  2124. case OCRDMA_WRITE:
  2125. ibwc->opcode = IB_WC_RDMA_WRITE;
  2126. break;
  2127. case OCRDMA_READ:
  2128. rw = (struct ocrdma_sge *)(hdr + 1);
  2129. ibwc->opcode = IB_WC_RDMA_READ;
  2130. ibwc->byte_len = rw->len;
  2131. break;
  2132. case OCRDMA_SEND:
  2133. ibwc->opcode = IB_WC_SEND;
  2134. break;
  2135. case OCRDMA_FR_MR:
  2136. ibwc->opcode = IB_WC_REG_MR;
  2137. break;
  2138. case OCRDMA_LKEY_INV:
  2139. ibwc->opcode = IB_WC_LOCAL_INV;
  2140. break;
  2141. default:
  2142. ibwc->status = IB_WC_GENERAL_ERR;
  2143. pr_err("%s() invalid opcode received = 0x%x\n",
  2144. __func__, hdr->cw & OCRDMA_WQE_OPCODE_MASK);
  2145. break;
  2146. }
  2147. }
  2148. static void ocrdma_set_cqe_status_flushed(struct ocrdma_qp *qp,
  2149. struct ocrdma_cqe *cqe)
  2150. {
  2151. if (is_cqe_for_sq(cqe)) {
  2152. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2153. cqe->flags_status_srcqpn) &
  2154. ~OCRDMA_CQE_STATUS_MASK);
  2155. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2156. cqe->flags_status_srcqpn) |
  2157. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2158. OCRDMA_CQE_STATUS_SHIFT));
  2159. } else {
  2160. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2161. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2162. cqe->flags_status_srcqpn) &
  2163. ~OCRDMA_CQE_UD_STATUS_MASK);
  2164. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2165. cqe->flags_status_srcqpn) |
  2166. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2167. OCRDMA_CQE_UD_STATUS_SHIFT));
  2168. } else {
  2169. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2170. cqe->flags_status_srcqpn) &
  2171. ~OCRDMA_CQE_STATUS_MASK);
  2172. cqe->flags_status_srcqpn = cpu_to_le32(le32_to_cpu(
  2173. cqe->flags_status_srcqpn) |
  2174. (OCRDMA_CQE_WR_FLUSH_ERR <<
  2175. OCRDMA_CQE_STATUS_SHIFT));
  2176. }
  2177. }
  2178. }
  2179. static bool ocrdma_update_err_cqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2180. struct ocrdma_qp *qp, int status)
  2181. {
  2182. bool expand = false;
  2183. ibwc->byte_len = 0;
  2184. ibwc->qp = &qp->ibqp;
  2185. ibwc->status = ocrdma_to_ibwc_err(status);
  2186. ocrdma_flush_qp(qp);
  2187. ocrdma_qp_state_change(qp, IB_QPS_ERR, NULL);
  2188. /* if wqe/rqe pending for which cqe needs to be returned,
  2189. * trigger inflating it.
  2190. */
  2191. if (!is_hw_rq_empty(qp) || !is_hw_sq_empty(qp)) {
  2192. expand = true;
  2193. ocrdma_set_cqe_status_flushed(qp, cqe);
  2194. }
  2195. return expand;
  2196. }
  2197. static int ocrdma_update_err_rcqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2198. struct ocrdma_qp *qp, int status)
  2199. {
  2200. ibwc->opcode = IB_WC_RECV;
  2201. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2202. ocrdma_hwq_inc_tail(&qp->rq);
  2203. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2204. }
  2205. static int ocrdma_update_err_scqe(struct ib_wc *ibwc, struct ocrdma_cqe *cqe,
  2206. struct ocrdma_qp *qp, int status)
  2207. {
  2208. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2209. ocrdma_hwq_inc_tail(&qp->sq);
  2210. return ocrdma_update_err_cqe(ibwc, cqe, qp, status);
  2211. }
  2212. static bool ocrdma_poll_err_scqe(struct ocrdma_qp *qp,
  2213. struct ocrdma_cqe *cqe, struct ib_wc *ibwc,
  2214. bool *polled, bool *stop)
  2215. {
  2216. bool expand;
  2217. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2218. int status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2219. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2220. if (status < OCRDMA_MAX_CQE_ERR)
  2221. atomic_inc(&dev->cqe_err_stats[status]);
  2222. /* when hw sq is empty, but rq is not empty, so we continue
  2223. * to keep the cqe in order to get the cq event again.
  2224. */
  2225. if (is_hw_sq_empty(qp) && !is_hw_rq_empty(qp)) {
  2226. /* when cq for rq and sq is same, it is safe to return
  2227. * flush cqe for RQEs.
  2228. */
  2229. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2230. *polled = true;
  2231. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2232. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2233. } else {
  2234. /* stop processing further cqe as this cqe is used for
  2235. * triggering cq event on buddy cq of RQ.
  2236. * When QP is destroyed, this cqe will be removed
  2237. * from the cq's hardware q.
  2238. */
  2239. *polled = false;
  2240. *stop = true;
  2241. expand = false;
  2242. }
  2243. } else if (is_hw_sq_empty(qp)) {
  2244. /* Do nothing */
  2245. expand = false;
  2246. *polled = false;
  2247. *stop = false;
  2248. } else {
  2249. *polled = true;
  2250. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2251. }
  2252. return expand;
  2253. }
  2254. static bool ocrdma_poll_success_scqe(struct ocrdma_qp *qp,
  2255. struct ocrdma_cqe *cqe,
  2256. struct ib_wc *ibwc, bool *polled)
  2257. {
  2258. bool expand = false;
  2259. int tail = qp->sq.tail;
  2260. u32 wqe_idx;
  2261. if (!qp->wqe_wr_id_tbl[tail].signaled) {
  2262. *polled = false; /* WC cannot be consumed yet */
  2263. } else {
  2264. ibwc->status = IB_WC_SUCCESS;
  2265. ibwc->wc_flags = 0;
  2266. ibwc->qp = &qp->ibqp;
  2267. ocrdma_update_wc(qp, ibwc, tail);
  2268. *polled = true;
  2269. }
  2270. wqe_idx = (le32_to_cpu(cqe->wq.wqeidx) &
  2271. OCRDMA_CQE_WQEIDX_MASK) & qp->sq.max_wqe_idx;
  2272. if (tail != wqe_idx)
  2273. expand = true; /* Coalesced CQE can't be consumed yet */
  2274. ocrdma_hwq_inc_tail(&qp->sq);
  2275. return expand;
  2276. }
  2277. static bool ocrdma_poll_scqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2278. struct ib_wc *ibwc, bool *polled, bool *stop)
  2279. {
  2280. int status;
  2281. bool expand;
  2282. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2283. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2284. if (status == OCRDMA_CQE_SUCCESS)
  2285. expand = ocrdma_poll_success_scqe(qp, cqe, ibwc, polled);
  2286. else
  2287. expand = ocrdma_poll_err_scqe(qp, cqe, ibwc, polled, stop);
  2288. return expand;
  2289. }
  2290. static int ocrdma_update_ud_rcqe(struct ocrdma_dev *dev, struct ib_wc *ibwc,
  2291. struct ocrdma_cqe *cqe)
  2292. {
  2293. int status;
  2294. u16 hdr_type = 0;
  2295. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2296. OCRDMA_CQE_UD_STATUS_MASK) >> OCRDMA_CQE_UD_STATUS_SHIFT;
  2297. ibwc->src_qp = le32_to_cpu(cqe->flags_status_srcqpn) &
  2298. OCRDMA_CQE_SRCQP_MASK;
  2299. ibwc->pkey_index = 0;
  2300. ibwc->wc_flags = IB_WC_GRH;
  2301. ibwc->byte_len = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2302. OCRDMA_CQE_UD_XFER_LEN_SHIFT) &
  2303. OCRDMA_CQE_UD_XFER_LEN_MASK;
  2304. if (ocrdma_is_udp_encap_supported(dev)) {
  2305. hdr_type = (le32_to_cpu(cqe->ud.rxlen_pkey) >>
  2306. OCRDMA_CQE_UD_L3TYPE_SHIFT) &
  2307. OCRDMA_CQE_UD_L3TYPE_MASK;
  2308. ibwc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
  2309. ibwc->network_hdr_type = hdr_type;
  2310. }
  2311. return status;
  2312. }
  2313. static void ocrdma_update_free_srq_cqe(struct ib_wc *ibwc,
  2314. struct ocrdma_cqe *cqe,
  2315. struct ocrdma_qp *qp)
  2316. {
  2317. unsigned long flags;
  2318. struct ocrdma_srq *srq;
  2319. u32 wqe_idx;
  2320. srq = get_ocrdma_srq(qp->ibqp.srq);
  2321. wqe_idx = (le32_to_cpu(cqe->rq.buftag_qpn) >>
  2322. OCRDMA_CQE_BUFTAG_SHIFT) & srq->rq.max_wqe_idx;
  2323. BUG_ON(wqe_idx < 1);
  2324. ibwc->wr_id = srq->rqe_wr_id_tbl[wqe_idx];
  2325. spin_lock_irqsave(&srq->q_lock, flags);
  2326. ocrdma_srq_toggle_bit(srq, wqe_idx - 1);
  2327. spin_unlock_irqrestore(&srq->q_lock, flags);
  2328. ocrdma_hwq_inc_tail(&srq->rq);
  2329. }
  2330. static bool ocrdma_poll_err_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2331. struct ib_wc *ibwc, bool *polled, bool *stop,
  2332. int status)
  2333. {
  2334. bool expand;
  2335. struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
  2336. if (status < OCRDMA_MAX_CQE_ERR)
  2337. atomic_inc(&dev->cqe_err_stats[status]);
  2338. /* when hw_rq is empty, but wq is not empty, so continue
  2339. * to keep the cqe to get the cq event again.
  2340. */
  2341. if (is_hw_rq_empty(qp) && !is_hw_sq_empty(qp)) {
  2342. if (!qp->srq && (qp->sq_cq == qp->rq_cq)) {
  2343. *polled = true;
  2344. status = OCRDMA_CQE_WR_FLUSH_ERR;
  2345. expand = ocrdma_update_err_scqe(ibwc, cqe, qp, status);
  2346. } else {
  2347. *polled = false;
  2348. *stop = true;
  2349. expand = false;
  2350. }
  2351. } else if (is_hw_rq_empty(qp)) {
  2352. /* Do nothing */
  2353. expand = false;
  2354. *polled = false;
  2355. *stop = false;
  2356. } else {
  2357. *polled = true;
  2358. expand = ocrdma_update_err_rcqe(ibwc, cqe, qp, status);
  2359. }
  2360. return expand;
  2361. }
  2362. static void ocrdma_poll_success_rcqe(struct ocrdma_qp *qp,
  2363. struct ocrdma_cqe *cqe, struct ib_wc *ibwc)
  2364. {
  2365. struct ocrdma_dev *dev;
  2366. dev = get_ocrdma_dev(qp->ibqp.device);
  2367. ibwc->opcode = IB_WC_RECV;
  2368. ibwc->qp = &qp->ibqp;
  2369. ibwc->status = IB_WC_SUCCESS;
  2370. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI)
  2371. ocrdma_update_ud_rcqe(dev, ibwc, cqe);
  2372. else
  2373. ibwc->byte_len = le32_to_cpu(cqe->rq.rxlen);
  2374. if (is_cqe_imm(cqe)) {
  2375. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2376. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2377. } else if (is_cqe_wr_imm(cqe)) {
  2378. ibwc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
  2379. ibwc->ex.imm_data = htonl(le32_to_cpu(cqe->rq.lkey_immdt));
  2380. ibwc->wc_flags |= IB_WC_WITH_IMM;
  2381. } else if (is_cqe_invalidated(cqe)) {
  2382. ibwc->ex.invalidate_rkey = le32_to_cpu(cqe->rq.lkey_immdt);
  2383. ibwc->wc_flags |= IB_WC_WITH_INVALIDATE;
  2384. }
  2385. if (qp->ibqp.srq) {
  2386. ocrdma_update_free_srq_cqe(ibwc, cqe, qp);
  2387. } else {
  2388. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2389. ocrdma_hwq_inc_tail(&qp->rq);
  2390. }
  2391. }
  2392. static bool ocrdma_poll_rcqe(struct ocrdma_qp *qp, struct ocrdma_cqe *cqe,
  2393. struct ib_wc *ibwc, bool *polled, bool *stop)
  2394. {
  2395. int status;
  2396. bool expand = false;
  2397. ibwc->wc_flags = 0;
  2398. if (qp->qp_type == IB_QPT_UD || qp->qp_type == IB_QPT_GSI) {
  2399. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2400. OCRDMA_CQE_UD_STATUS_MASK) >>
  2401. OCRDMA_CQE_UD_STATUS_SHIFT;
  2402. } else {
  2403. status = (le32_to_cpu(cqe->flags_status_srcqpn) &
  2404. OCRDMA_CQE_STATUS_MASK) >> OCRDMA_CQE_STATUS_SHIFT;
  2405. }
  2406. if (status == OCRDMA_CQE_SUCCESS) {
  2407. *polled = true;
  2408. ocrdma_poll_success_rcqe(qp, cqe, ibwc);
  2409. } else {
  2410. expand = ocrdma_poll_err_rcqe(qp, cqe, ibwc, polled, stop,
  2411. status);
  2412. }
  2413. return expand;
  2414. }
  2415. static void ocrdma_change_cq_phase(struct ocrdma_cq *cq, struct ocrdma_cqe *cqe,
  2416. u16 cur_getp)
  2417. {
  2418. if (cq->phase_change) {
  2419. if (cur_getp == 0)
  2420. cq->phase = (~cq->phase & OCRDMA_CQE_VALID);
  2421. } else {
  2422. /* clear valid bit */
  2423. cqe->flags_status_srcqpn = 0;
  2424. }
  2425. }
  2426. static int ocrdma_poll_hwcq(struct ocrdma_cq *cq, int num_entries,
  2427. struct ib_wc *ibwc)
  2428. {
  2429. u16 qpn = 0;
  2430. int i = 0;
  2431. bool expand = false;
  2432. int polled_hw_cqes = 0;
  2433. struct ocrdma_qp *qp = NULL;
  2434. struct ocrdma_dev *dev = get_ocrdma_dev(cq->ibcq.device);
  2435. struct ocrdma_cqe *cqe;
  2436. u16 cur_getp; bool polled = false; bool stop = false;
  2437. cur_getp = cq->getp;
  2438. while (num_entries) {
  2439. cqe = cq->va + cur_getp;
  2440. /* check whether valid cqe or not */
  2441. if (!is_cqe_valid(cq, cqe))
  2442. break;
  2443. qpn = (le32_to_cpu(cqe->cmn.qpn) & OCRDMA_CQE_QPN_MASK);
  2444. /* ignore discarded cqe */
  2445. if (qpn == 0)
  2446. goto skip_cqe;
  2447. qp = dev->qp_tbl[qpn];
  2448. BUG_ON(qp == NULL);
  2449. if (is_cqe_for_sq(cqe)) {
  2450. expand = ocrdma_poll_scqe(qp, cqe, ibwc, &polled,
  2451. &stop);
  2452. } else {
  2453. expand = ocrdma_poll_rcqe(qp, cqe, ibwc, &polled,
  2454. &stop);
  2455. }
  2456. if (expand)
  2457. goto expand_cqe;
  2458. if (stop)
  2459. goto stop_cqe;
  2460. /* clear qpn to avoid duplicate processing by discard_cqe() */
  2461. cqe->cmn.qpn = 0;
  2462. skip_cqe:
  2463. polled_hw_cqes += 1;
  2464. cur_getp = (cur_getp + 1) % cq->max_hw_cqe;
  2465. ocrdma_change_cq_phase(cq, cqe, cur_getp);
  2466. expand_cqe:
  2467. if (polled) {
  2468. num_entries -= 1;
  2469. i += 1;
  2470. ibwc = ibwc + 1;
  2471. polled = false;
  2472. }
  2473. }
  2474. stop_cqe:
  2475. cq->getp = cur_getp;
  2476. if (polled_hw_cqes)
  2477. ocrdma_ring_cq_db(dev, cq->id, false, false, polled_hw_cqes);
  2478. return i;
  2479. }
  2480. /* insert error cqe if the QP's SQ or RQ's CQ matches the CQ under poll. */
  2481. static int ocrdma_add_err_cqe(struct ocrdma_cq *cq, int num_entries,
  2482. struct ocrdma_qp *qp, struct ib_wc *ibwc)
  2483. {
  2484. int err_cqes = 0;
  2485. while (num_entries) {
  2486. if (is_hw_sq_empty(qp) && is_hw_rq_empty(qp))
  2487. break;
  2488. if (!is_hw_sq_empty(qp) && qp->sq_cq == cq) {
  2489. ocrdma_update_wc(qp, ibwc, qp->sq.tail);
  2490. ocrdma_hwq_inc_tail(&qp->sq);
  2491. } else if (!is_hw_rq_empty(qp) && qp->rq_cq == cq) {
  2492. ibwc->wr_id = qp->rqe_wr_id_tbl[qp->rq.tail];
  2493. ocrdma_hwq_inc_tail(&qp->rq);
  2494. } else {
  2495. return err_cqes;
  2496. }
  2497. ibwc->byte_len = 0;
  2498. ibwc->status = IB_WC_WR_FLUSH_ERR;
  2499. ibwc = ibwc + 1;
  2500. err_cqes += 1;
  2501. num_entries -= 1;
  2502. }
  2503. return err_cqes;
  2504. }
  2505. int ocrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
  2506. {
  2507. int cqes_to_poll = num_entries;
  2508. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2509. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2510. int num_os_cqe = 0, err_cqes = 0;
  2511. struct ocrdma_qp *qp;
  2512. unsigned long flags;
  2513. /* poll cqes from adapter CQ */
  2514. spin_lock_irqsave(&cq->cq_lock, flags);
  2515. num_os_cqe = ocrdma_poll_hwcq(cq, cqes_to_poll, wc);
  2516. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2517. cqes_to_poll -= num_os_cqe;
  2518. if (cqes_to_poll) {
  2519. wc = wc + num_os_cqe;
  2520. /* adapter returns single error cqe when qp moves to
  2521. * error state. So insert error cqes with wc_status as
  2522. * FLUSHED for pending WQEs and RQEs of QP's SQ and RQ
  2523. * respectively which uses this CQ.
  2524. */
  2525. spin_lock_irqsave(&dev->flush_q_lock, flags);
  2526. list_for_each_entry(qp, &cq->sq_head, sq_entry) {
  2527. if (cqes_to_poll == 0)
  2528. break;
  2529. err_cqes = ocrdma_add_err_cqe(cq, cqes_to_poll, qp, wc);
  2530. cqes_to_poll -= err_cqes;
  2531. num_os_cqe += err_cqes;
  2532. wc = wc + err_cqes;
  2533. }
  2534. spin_unlock_irqrestore(&dev->flush_q_lock, flags);
  2535. }
  2536. return num_os_cqe;
  2537. }
  2538. int ocrdma_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags cq_flags)
  2539. {
  2540. struct ocrdma_cq *cq = get_ocrdma_cq(ibcq);
  2541. struct ocrdma_dev *dev = get_ocrdma_dev(ibcq->device);
  2542. u16 cq_id;
  2543. unsigned long flags;
  2544. bool arm_needed = false, sol_needed = false;
  2545. cq_id = cq->id;
  2546. spin_lock_irqsave(&cq->cq_lock, flags);
  2547. if (cq_flags & IB_CQ_NEXT_COMP || cq_flags & IB_CQ_SOLICITED)
  2548. arm_needed = true;
  2549. if (cq_flags & IB_CQ_SOLICITED)
  2550. sol_needed = true;
  2551. ocrdma_ring_cq_db(dev, cq_id, arm_needed, sol_needed, 0);
  2552. spin_unlock_irqrestore(&cq->cq_lock, flags);
  2553. return 0;
  2554. }
  2555. struct ib_mr *ocrdma_alloc_mr(struct ib_pd *ibpd, enum ib_mr_type mr_type,
  2556. u32 max_num_sg)
  2557. {
  2558. int status;
  2559. struct ocrdma_mr *mr;
  2560. struct ocrdma_pd *pd = get_ocrdma_pd(ibpd);
  2561. struct ocrdma_dev *dev = get_ocrdma_dev(ibpd->device);
  2562. if (mr_type != IB_MR_TYPE_MEM_REG)
  2563. return ERR_PTR(-EINVAL);
  2564. if (max_num_sg > dev->attr.max_pages_per_frmr)
  2565. return ERR_PTR(-EINVAL);
  2566. mr = kzalloc_obj(*mr);
  2567. if (!mr)
  2568. return ERR_PTR(-ENOMEM);
  2569. mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
  2570. if (!mr->pages) {
  2571. status = -ENOMEM;
  2572. goto pl_err;
  2573. }
  2574. status = ocrdma_get_pbl_info(dev, mr, max_num_sg);
  2575. if (status)
  2576. goto pbl_err;
  2577. mr->hwmr.fr_mr = 1;
  2578. mr->hwmr.remote_rd = 0;
  2579. mr->hwmr.remote_wr = 0;
  2580. mr->hwmr.local_rd = 0;
  2581. mr->hwmr.local_wr = 0;
  2582. mr->hwmr.mw_bind = 0;
  2583. status = ocrdma_build_pbl_tbl(dev, &mr->hwmr);
  2584. if (status)
  2585. goto pbl_err;
  2586. status = ocrdma_reg_mr(dev, &mr->hwmr, pd->id, 0);
  2587. if (status)
  2588. goto mbx_err;
  2589. mr->ibmr.rkey = mr->hwmr.lkey;
  2590. mr->ibmr.lkey = mr->hwmr.lkey;
  2591. dev->stag_arr[(mr->hwmr.lkey >> 8) & (OCRDMA_MAX_STAG - 1)] =
  2592. (unsigned long) mr;
  2593. return &mr->ibmr;
  2594. mbx_err:
  2595. ocrdma_free_mr_pbl_tbl(dev, &mr->hwmr);
  2596. pbl_err:
  2597. kfree(mr->pages);
  2598. pl_err:
  2599. kfree(mr);
  2600. return ERR_PTR(-ENOMEM);
  2601. }
  2602. static int ocrdma_set_page(struct ib_mr *ibmr, u64 addr)
  2603. {
  2604. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2605. if (unlikely(mr->npages == mr->hwmr.num_pbes))
  2606. return -ENOMEM;
  2607. mr->pages[mr->npages++] = addr;
  2608. return 0;
  2609. }
  2610. int ocrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
  2611. unsigned int *sg_offset)
  2612. {
  2613. struct ocrdma_mr *mr = get_ocrdma_mr(ibmr);
  2614. mr->npages = 0;
  2615. return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, ocrdma_set_page);
  2616. }