rw.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2016 HGST, a Western Digital Company.
  4. */
  5. #include <linux/memremap.h>
  6. #include <linux/moduleparam.h>
  7. #include <linux/slab.h>
  8. #include <linux/pci-p2pdma.h>
  9. #include <rdma/mr_pool.h>
  10. #include <rdma/rw.h>
  11. enum {
  12. RDMA_RW_SINGLE_WR,
  13. RDMA_RW_MULTI_WR,
  14. RDMA_RW_MR,
  15. RDMA_RW_SIG_MR,
  16. RDMA_RW_IOVA,
  17. };
  18. static bool rdma_rw_force_mr;
  19. module_param_named(force_mr, rdma_rw_force_mr, bool, 0);
  20. MODULE_PARM_DESC(force_mr, "Force usage of MRs for RDMA READ/WRITE operations");
  21. /*
  22. * Report whether memory registration should be used. Memory registration must
  23. * be used for iWarp devices because of iWARP-specific limitations. Memory
  24. * registration is also enabled if registering memory might yield better
  25. * performance than using multiple SGE entries, see rdma_rw_io_needs_mr()
  26. */
  27. static inline bool rdma_rw_can_use_mr(struct ib_device *dev, u32 port_num)
  28. {
  29. if (rdma_protocol_iwarp(dev, port_num))
  30. return true;
  31. if (dev->attrs.max_sgl_rd)
  32. return true;
  33. if (unlikely(rdma_rw_force_mr))
  34. return true;
  35. return false;
  36. }
  37. /*
  38. * Check if the device will use memory registration for this RW operation.
  39. * For RDMA READs we must use MRs on iWarp and can optionally use them as an
  40. * optimization otherwise. Additionally we have a debug option to force usage
  41. * of MRs to help testing this code path.
  42. */
  43. static inline bool rdma_rw_io_needs_mr(struct ib_device *dev, u32 port_num,
  44. enum dma_data_direction dir, int dma_nents)
  45. {
  46. if (dir == DMA_FROM_DEVICE) {
  47. if (rdma_protocol_iwarp(dev, port_num))
  48. return true;
  49. if (dev->attrs.max_sgl_rd && dma_nents > dev->attrs.max_sgl_rd)
  50. return true;
  51. }
  52. if (unlikely(rdma_rw_force_mr))
  53. return true;
  54. return false;
  55. }
  56. static inline u32 rdma_rw_fr_page_list_len(struct ib_device *dev,
  57. bool pi_support)
  58. {
  59. u32 max_pages;
  60. if (pi_support)
  61. max_pages = dev->attrs.max_pi_fast_reg_page_list_len;
  62. else
  63. max_pages = dev->attrs.max_fast_reg_page_list_len;
  64. /* arbitrary limit to avoid allocating gigantic resources */
  65. return min_t(u32, max_pages, 256);
  66. }
  67. static inline int rdma_rw_inv_key(struct rdma_rw_reg_ctx *reg)
  68. {
  69. int count = 0;
  70. if (reg->mr->need_inval) {
  71. reg->inv_wr.opcode = IB_WR_LOCAL_INV;
  72. reg->inv_wr.ex.invalidate_rkey = reg->mr->lkey;
  73. reg->inv_wr.next = &reg->reg_wr.wr;
  74. count++;
  75. } else {
  76. reg->inv_wr.next = NULL;
  77. }
  78. return count;
  79. }
  80. /* Caller must have zero-initialized *reg. */
  81. static int rdma_rw_init_one_mr(struct ib_qp *qp, u32 port_num,
  82. struct rdma_rw_reg_ctx *reg, struct scatterlist *sg,
  83. u32 sg_cnt, u32 offset)
  84. {
  85. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device,
  86. qp->integrity_en);
  87. u32 nents = min(sg_cnt, pages_per_mr);
  88. int count = 0, ret;
  89. reg->mr = ib_mr_pool_get(qp, &qp->rdma_mrs);
  90. if (!reg->mr)
  91. return -EAGAIN;
  92. count += rdma_rw_inv_key(reg);
  93. ret = ib_map_mr_sg(reg->mr, sg, nents, &offset, PAGE_SIZE);
  94. if (ret < 0 || ret < nents) {
  95. ib_mr_pool_put(qp, &qp->rdma_mrs, reg->mr);
  96. return -EINVAL;
  97. }
  98. reg->reg_wr.wr.opcode = IB_WR_REG_MR;
  99. reg->reg_wr.mr = reg->mr;
  100. reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
  101. if (rdma_protocol_iwarp(qp->device, port_num))
  102. reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
  103. count++;
  104. reg->sge.addr = reg->mr->iova;
  105. reg->sge.length = reg->mr->length;
  106. return count;
  107. }
  108. static int rdma_rw_init_reg_wr(struct rdma_rw_reg_ctx *reg,
  109. struct rdma_rw_reg_ctx *prev, struct ib_qp *qp, u32 port_num,
  110. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  111. {
  112. if (prev) {
  113. if (reg->mr->need_inval)
  114. prev->wr.wr.next = &reg->inv_wr;
  115. else
  116. prev->wr.wr.next = &reg->reg_wr.wr;
  117. }
  118. reg->reg_wr.wr.next = &reg->wr.wr;
  119. reg->wr.wr.sg_list = &reg->sge;
  120. reg->wr.wr.num_sge = 1;
  121. reg->wr.remote_addr = remote_addr;
  122. reg->wr.rkey = rkey;
  123. if (dir == DMA_TO_DEVICE) {
  124. reg->wr.wr.opcode = IB_WR_RDMA_WRITE;
  125. } else if (!rdma_cap_read_inv(qp->device, port_num)) {
  126. reg->wr.wr.opcode = IB_WR_RDMA_READ;
  127. } else {
  128. reg->wr.wr.opcode = IB_WR_RDMA_READ_WITH_INV;
  129. reg->wr.wr.ex.invalidate_rkey = reg->mr->lkey;
  130. }
  131. return 1;
  132. }
  133. static int rdma_rw_init_mr_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  134. u32 port_num, struct scatterlist *sg, u32 sg_cnt, u32 offset,
  135. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  136. {
  137. struct rdma_rw_reg_ctx *prev = NULL;
  138. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device,
  139. qp->integrity_en);
  140. int i, j, ret = 0, count = 0;
  141. ctx->nr_ops = DIV_ROUND_UP(sg_cnt, pages_per_mr);
  142. ctx->reg = kzalloc_objs(*ctx->reg, ctx->nr_ops);
  143. if (!ctx->reg) {
  144. ret = -ENOMEM;
  145. goto out;
  146. }
  147. for (i = 0; i < ctx->nr_ops; i++) {
  148. struct rdma_rw_reg_ctx *reg = &ctx->reg[i];
  149. u32 nents = min(sg_cnt, pages_per_mr);
  150. ret = rdma_rw_init_one_mr(qp, port_num, reg, sg, sg_cnt,
  151. offset);
  152. if (ret < 0)
  153. goto out_free;
  154. count += ret;
  155. count += rdma_rw_init_reg_wr(reg, prev, qp, port_num,
  156. remote_addr, rkey, dir);
  157. remote_addr += reg->sge.length;
  158. sg_cnt -= nents;
  159. for (j = 0; j < nents; j++)
  160. sg = sg_next(sg);
  161. prev = reg;
  162. offset = 0;
  163. }
  164. if (prev)
  165. prev->wr.wr.next = NULL;
  166. ctx->type = RDMA_RW_MR;
  167. return count;
  168. out_free:
  169. while (--i >= 0)
  170. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  171. kfree(ctx->reg);
  172. out:
  173. return ret;
  174. }
  175. static int rdma_rw_init_mr_wrs_bvec(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  176. u32 port_num, const struct bio_vec *bvecs, u32 nr_bvec,
  177. struct bvec_iter *iter, u64 remote_addr, u32 rkey,
  178. enum dma_data_direction dir)
  179. {
  180. struct ib_device *dev = qp->pd->device;
  181. struct rdma_rw_reg_ctx *prev = NULL;
  182. u32 pages_per_mr = rdma_rw_fr_page_list_len(dev, qp->integrity_en);
  183. struct scatterlist *sg;
  184. int i, ret, count = 0;
  185. u32 nents = 0;
  186. ctx->reg = kzalloc_objs(*ctx->reg, DIV_ROUND_UP(nr_bvec, pages_per_mr));
  187. if (!ctx->reg)
  188. return -ENOMEM;
  189. /*
  190. * Build scatterlist from bvecs using the iterator. This follows
  191. * the pattern from __blk_rq_map_sg.
  192. */
  193. ctx->reg[0].sgt.sgl = kmalloc_objs(*ctx->reg[0].sgt.sgl, nr_bvec);
  194. if (!ctx->reg[0].sgt.sgl) {
  195. ret = -ENOMEM;
  196. goto out_free_reg;
  197. }
  198. sg_init_table(ctx->reg[0].sgt.sgl, nr_bvec);
  199. for (sg = ctx->reg[0].sgt.sgl; iter->bi_size; sg = sg_next(sg)) {
  200. struct bio_vec bv = mp_bvec_iter_bvec(bvecs, *iter);
  201. if (nents >= nr_bvec) {
  202. ret = -EINVAL;
  203. goto out_free_sgl;
  204. }
  205. sg_set_page(sg, bv.bv_page, bv.bv_len, bv.bv_offset);
  206. bvec_iter_advance(bvecs, iter, bv.bv_len);
  207. nents++;
  208. }
  209. sg_mark_end(sg_last(ctx->reg[0].sgt.sgl, nents));
  210. ctx->reg[0].sgt.orig_nents = nents;
  211. /* DMA map the scatterlist */
  212. ret = ib_dma_map_sgtable_attrs(dev, &ctx->reg[0].sgt, dir, 0);
  213. if (ret)
  214. goto out_free_sgl;
  215. ctx->nr_ops = DIV_ROUND_UP(ctx->reg[0].sgt.nents, pages_per_mr);
  216. sg = ctx->reg[0].sgt.sgl;
  217. nents = ctx->reg[0].sgt.nents;
  218. for (i = 0; i < ctx->nr_ops; i++) {
  219. struct rdma_rw_reg_ctx *reg = &ctx->reg[i];
  220. u32 sge_cnt = min(nents, pages_per_mr);
  221. ret = rdma_rw_init_one_mr(qp, port_num, reg, sg, sge_cnt, 0);
  222. if (ret < 0)
  223. goto out_free_mrs;
  224. count += ret;
  225. count += rdma_rw_init_reg_wr(reg, prev, qp, port_num,
  226. remote_addr, rkey, dir);
  227. remote_addr += reg->sge.length;
  228. nents -= sge_cnt;
  229. sg += sge_cnt;
  230. prev = reg;
  231. }
  232. if (prev)
  233. prev->wr.wr.next = NULL;
  234. ctx->type = RDMA_RW_MR;
  235. return count;
  236. out_free_mrs:
  237. while (--i >= 0)
  238. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  239. ib_dma_unmap_sgtable_attrs(dev, &ctx->reg[0].sgt, dir, 0);
  240. out_free_sgl:
  241. kfree(ctx->reg[0].sgt.sgl);
  242. out_free_reg:
  243. kfree(ctx->reg);
  244. return ret;
  245. }
  246. static int rdma_rw_init_map_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  247. struct scatterlist *sg, u32 sg_cnt, u32 offset,
  248. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  249. {
  250. u32 max_sge = dir == DMA_TO_DEVICE ? qp->max_write_sge :
  251. qp->max_read_sge;
  252. struct ib_sge *sge;
  253. u32 total_len = 0, i, j;
  254. ctx->nr_ops = DIV_ROUND_UP(sg_cnt, max_sge);
  255. ctx->map.sges = sge = kzalloc_objs(*sge, sg_cnt);
  256. if (!ctx->map.sges)
  257. goto out;
  258. ctx->map.wrs = kzalloc_objs(*ctx->map.wrs, ctx->nr_ops);
  259. if (!ctx->map.wrs)
  260. goto out_free_sges;
  261. for (i = 0; i < ctx->nr_ops; i++) {
  262. struct ib_rdma_wr *rdma_wr = &ctx->map.wrs[i];
  263. u32 nr_sge = min(sg_cnt, max_sge);
  264. if (dir == DMA_TO_DEVICE)
  265. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  266. else
  267. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  268. rdma_wr->remote_addr = remote_addr + total_len;
  269. rdma_wr->rkey = rkey;
  270. rdma_wr->wr.num_sge = nr_sge;
  271. rdma_wr->wr.sg_list = sge;
  272. for (j = 0; j < nr_sge; j++, sg = sg_next(sg)) {
  273. sge->addr = sg_dma_address(sg) + offset;
  274. sge->length = sg_dma_len(sg) - offset;
  275. sge->lkey = qp->pd->local_dma_lkey;
  276. total_len += sge->length;
  277. sge++;
  278. sg_cnt--;
  279. offset = 0;
  280. }
  281. rdma_wr->wr.next = i + 1 < ctx->nr_ops ?
  282. &ctx->map.wrs[i + 1].wr : NULL;
  283. }
  284. ctx->type = RDMA_RW_MULTI_WR;
  285. return ctx->nr_ops;
  286. out_free_sges:
  287. kfree(ctx->map.sges);
  288. out:
  289. return -ENOMEM;
  290. }
  291. static int rdma_rw_init_single_wr(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  292. struct scatterlist *sg, u32 offset, u64 remote_addr, u32 rkey,
  293. enum dma_data_direction dir)
  294. {
  295. struct ib_rdma_wr *rdma_wr = &ctx->single.wr;
  296. ctx->nr_ops = 1;
  297. ctx->single.sge.lkey = qp->pd->local_dma_lkey;
  298. ctx->single.sge.addr = sg_dma_address(sg) + offset;
  299. ctx->single.sge.length = sg_dma_len(sg) - offset;
  300. memset(rdma_wr, 0, sizeof(*rdma_wr));
  301. if (dir == DMA_TO_DEVICE)
  302. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  303. else
  304. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  305. rdma_wr->wr.sg_list = &ctx->single.sge;
  306. rdma_wr->wr.num_sge = 1;
  307. rdma_wr->remote_addr = remote_addr;
  308. rdma_wr->rkey = rkey;
  309. ctx->type = RDMA_RW_SINGLE_WR;
  310. return 1;
  311. }
  312. static int rdma_rw_init_single_wr_bvec(struct rdma_rw_ctx *ctx,
  313. struct ib_qp *qp, const struct bio_vec *bvecs,
  314. struct bvec_iter *iter, u64 remote_addr, u32 rkey,
  315. enum dma_data_direction dir)
  316. {
  317. struct ib_device *dev = qp->pd->device;
  318. struct ib_rdma_wr *rdma_wr = &ctx->single.wr;
  319. struct bio_vec bv = mp_bvec_iter_bvec(bvecs, *iter);
  320. u64 dma_addr;
  321. ctx->nr_ops = 1;
  322. dma_addr = ib_dma_map_bvec(dev, &bv, dir);
  323. if (ib_dma_mapping_error(dev, dma_addr))
  324. return -ENOMEM;
  325. ctx->single.sge.lkey = qp->pd->local_dma_lkey;
  326. ctx->single.sge.addr = dma_addr;
  327. ctx->single.sge.length = bv.bv_len;
  328. memset(rdma_wr, 0, sizeof(*rdma_wr));
  329. if (dir == DMA_TO_DEVICE)
  330. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  331. else
  332. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  333. rdma_wr->wr.sg_list = &ctx->single.sge;
  334. rdma_wr->wr.num_sge = 1;
  335. rdma_wr->remote_addr = remote_addr;
  336. rdma_wr->rkey = rkey;
  337. ctx->type = RDMA_RW_SINGLE_WR;
  338. return 1;
  339. }
  340. static int rdma_rw_init_map_wrs_bvec(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  341. const struct bio_vec *bvecs, u32 nr_bvec, struct bvec_iter *iter,
  342. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  343. {
  344. struct ib_device *dev = qp->pd->device;
  345. u32 max_sge = dir == DMA_TO_DEVICE ? qp->max_write_sge :
  346. qp->max_read_sge;
  347. struct ib_sge *sge;
  348. u32 total_len = 0, i, j;
  349. u32 mapped_bvecs = 0;
  350. u32 nr_ops = DIV_ROUND_UP(nr_bvec, max_sge);
  351. size_t sges_size = array_size(nr_bvec, sizeof(*ctx->map.sges));
  352. size_t wrs_offset = ALIGN(sges_size, __alignof__(*ctx->map.wrs));
  353. size_t wrs_size = array_size(nr_ops, sizeof(*ctx->map.wrs));
  354. void *mem;
  355. if (sges_size == SIZE_MAX || wrs_size == SIZE_MAX ||
  356. check_add_overflow(wrs_offset, wrs_size, &wrs_size))
  357. return -ENOMEM;
  358. mem = kzalloc(wrs_size, GFP_KERNEL);
  359. if (!mem)
  360. return -ENOMEM;
  361. ctx->map.sges = sge = mem;
  362. ctx->map.wrs = mem + wrs_offset;
  363. for (i = 0; i < nr_ops; i++) {
  364. struct ib_rdma_wr *rdma_wr = &ctx->map.wrs[i];
  365. u32 nr_sge = min(nr_bvec - mapped_bvecs, max_sge);
  366. if (dir == DMA_TO_DEVICE)
  367. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  368. else
  369. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  370. rdma_wr->remote_addr = remote_addr + total_len;
  371. rdma_wr->rkey = rkey;
  372. rdma_wr->wr.num_sge = nr_sge;
  373. rdma_wr->wr.sg_list = sge;
  374. for (j = 0; j < nr_sge; j++) {
  375. struct bio_vec bv = mp_bvec_iter_bvec(bvecs, *iter);
  376. u64 dma_addr;
  377. dma_addr = ib_dma_map_bvec(dev, &bv, dir);
  378. if (ib_dma_mapping_error(dev, dma_addr))
  379. goto out_unmap;
  380. mapped_bvecs++;
  381. sge->addr = dma_addr;
  382. sge->length = bv.bv_len;
  383. sge->lkey = qp->pd->local_dma_lkey;
  384. total_len += bv.bv_len;
  385. sge++;
  386. bvec_iter_advance_single(bvecs, iter, bv.bv_len);
  387. }
  388. rdma_wr->wr.next = i + 1 < nr_ops ?
  389. &ctx->map.wrs[i + 1].wr : NULL;
  390. }
  391. ctx->nr_ops = nr_ops;
  392. ctx->type = RDMA_RW_MULTI_WR;
  393. return nr_ops;
  394. out_unmap:
  395. for (i = 0; i < mapped_bvecs; i++)
  396. ib_dma_unmap_bvec(dev, ctx->map.sges[i].addr,
  397. ctx->map.sges[i].length, dir);
  398. kfree(ctx->map.sges);
  399. return -ENOMEM;
  400. }
  401. /*
  402. * Try to use the two-step IOVA API to map bvecs into a contiguous DMA range.
  403. * This reduces IOTLB sync overhead by doing one sync at the end instead of
  404. * one per bvec, and produces a contiguous DMA address range that can be
  405. * described by a single SGE.
  406. *
  407. * Returns the number of WQEs (always 1) on success, -EOPNOTSUPP if IOVA
  408. * mapping is not available, or another negative error code on failure.
  409. */
  410. static int rdma_rw_init_iova_wrs_bvec(struct rdma_rw_ctx *ctx,
  411. struct ib_qp *qp, const struct bio_vec *bvec,
  412. struct bvec_iter *iter, u64 remote_addr, u32 rkey,
  413. enum dma_data_direction dir)
  414. {
  415. struct ib_device *dev = qp->pd->device;
  416. struct device *dma_dev = dev->dma_device;
  417. size_t total_len = iter->bi_size;
  418. struct bio_vec first_bv;
  419. size_t mapped_len = 0;
  420. int ret;
  421. /* Virtual DMA devices cannot support IOVA allocators */
  422. if (ib_uses_virt_dma(dev))
  423. return -EOPNOTSUPP;
  424. /* Try to allocate contiguous IOVA space */
  425. first_bv = mp_bvec_iter_bvec(bvec, *iter);
  426. if (!dma_iova_try_alloc(dma_dev, &ctx->iova.state,
  427. bvec_phys(&first_bv), total_len))
  428. return -EOPNOTSUPP;
  429. /* Link all bvecs into the IOVA space */
  430. while (iter->bi_size) {
  431. struct bio_vec bv = mp_bvec_iter_bvec(bvec, *iter);
  432. ret = dma_iova_link(dma_dev, &ctx->iova.state, bvec_phys(&bv),
  433. mapped_len, bv.bv_len, dir, 0);
  434. if (ret)
  435. goto out_destroy;
  436. mapped_len += bv.bv_len;
  437. bvec_iter_advance(bvec, iter, bv.bv_len);
  438. }
  439. /* Sync the IOTLB once for all linked pages */
  440. ret = dma_iova_sync(dma_dev, &ctx->iova.state, 0, mapped_len);
  441. if (ret)
  442. goto out_destroy;
  443. ctx->iova.mapped_len = mapped_len;
  444. /* Single SGE covers the entire contiguous IOVA range */
  445. ctx->iova.sge.addr = ctx->iova.state.addr;
  446. ctx->iova.sge.length = mapped_len;
  447. ctx->iova.sge.lkey = qp->pd->local_dma_lkey;
  448. /* Single WR for the whole transfer */
  449. memset(&ctx->iova.wr, 0, sizeof(ctx->iova.wr));
  450. if (dir == DMA_TO_DEVICE)
  451. ctx->iova.wr.wr.opcode = IB_WR_RDMA_WRITE;
  452. else
  453. ctx->iova.wr.wr.opcode = IB_WR_RDMA_READ;
  454. ctx->iova.wr.wr.num_sge = 1;
  455. ctx->iova.wr.wr.sg_list = &ctx->iova.sge;
  456. ctx->iova.wr.remote_addr = remote_addr;
  457. ctx->iova.wr.rkey = rkey;
  458. ctx->type = RDMA_RW_IOVA;
  459. ctx->nr_ops = 1;
  460. return 1;
  461. out_destroy:
  462. /*
  463. * dma_iova_destroy() expects the actual mapped length, not the
  464. * total allocation size. It unlinks only the successfully linked
  465. * range and frees the entire IOVA allocation.
  466. */
  467. dma_iova_destroy(dma_dev, &ctx->iova.state, mapped_len, dir, 0);
  468. return ret;
  469. }
  470. /**
  471. * rdma_rw_ctx_init - initialize a RDMA READ/WRITE context
  472. * @ctx: context to initialize
  473. * @qp: queue pair to operate on
  474. * @port_num: port num to which the connection is bound
  475. * @sg: scatterlist to READ/WRITE from/to
  476. * @sg_cnt: number of entries in @sg
  477. * @sg_offset: current byte offset into @sg
  478. * @remote_addr:remote address to read/write (relative to @rkey)
  479. * @rkey: remote key to operate on
  480. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  481. *
  482. * Returns the number of WQEs that will be needed on the workqueue if
  483. * successful, or a negative error code.
  484. */
  485. int rdma_rw_ctx_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u32 port_num,
  486. struct scatterlist *sg, u32 sg_cnt, u32 sg_offset,
  487. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  488. {
  489. struct ib_device *dev = qp->pd->device;
  490. struct sg_table sgt = {
  491. .sgl = sg,
  492. .orig_nents = sg_cnt,
  493. };
  494. int ret;
  495. ret = ib_dma_map_sgtable_attrs(dev, &sgt, dir, 0);
  496. if (ret)
  497. return ret;
  498. sg_cnt = sgt.nents;
  499. /*
  500. * Skip to the S/G entry that sg_offset falls into:
  501. */
  502. for (;;) {
  503. u32 len = sg_dma_len(sg);
  504. if (sg_offset < len)
  505. break;
  506. sg = sg_next(sg);
  507. sg_offset -= len;
  508. sg_cnt--;
  509. }
  510. ret = -EIO;
  511. if (WARN_ON_ONCE(sg_cnt == 0))
  512. goto out_unmap_sg;
  513. if (rdma_rw_io_needs_mr(qp->device, port_num, dir, sg_cnt)) {
  514. ret = rdma_rw_init_mr_wrs(ctx, qp, port_num, sg, sg_cnt,
  515. sg_offset, remote_addr, rkey, dir);
  516. /*
  517. * If MR init succeeded or failed for a reason other
  518. * than pool exhaustion, that result is final.
  519. *
  520. * Pool exhaustion (-EAGAIN) from the max_sgl_rd
  521. * optimization is recoverable: fall back to
  522. * direct SGE posting. iWARP and force_mr require
  523. * MRs unconditionally, so -EAGAIN is terminal.
  524. */
  525. if (ret != -EAGAIN ||
  526. rdma_protocol_iwarp(qp->device, port_num) ||
  527. unlikely(rdma_rw_force_mr))
  528. goto out;
  529. }
  530. if (sg_cnt > 1)
  531. ret = rdma_rw_init_map_wrs(ctx, qp, sg, sg_cnt, sg_offset,
  532. remote_addr, rkey, dir);
  533. else
  534. ret = rdma_rw_init_single_wr(ctx, qp, sg, sg_offset,
  535. remote_addr, rkey, dir);
  536. out:
  537. if (ret < 0)
  538. goto out_unmap_sg;
  539. return ret;
  540. out_unmap_sg:
  541. ib_dma_unmap_sgtable_attrs(dev, &sgt, dir, 0);
  542. return ret;
  543. }
  544. EXPORT_SYMBOL(rdma_rw_ctx_init);
  545. /**
  546. * rdma_rw_ctx_init_bvec - initialize a RDMA READ/WRITE context from bio_vec
  547. * @ctx: context to initialize
  548. * @qp: queue pair to operate on
  549. * @port_num: port num to which the connection is bound
  550. * @bvecs: bio_vec array to READ/WRITE from/to
  551. * @nr_bvec: number of entries in @bvecs
  552. * @iter: bvec iterator describing offset and length
  553. * @remote_addr: remote address to read/write (relative to @rkey)
  554. * @rkey: remote key to operate on
  555. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  556. *
  557. * Maps the bio_vec array directly, avoiding intermediate scatterlist
  558. * conversion. Supports MR registration for iWARP devices and force_mr mode.
  559. *
  560. * Returns the number of WQEs that will be needed on the workqueue if
  561. * successful, or a negative error code:
  562. *
  563. * * -EINVAL - @nr_bvec is zero or @iter.bi_size is zero
  564. * * -ENOMEM - DMA mapping or memory allocation failed
  565. */
  566. int rdma_rw_ctx_init_bvec(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  567. u32 port_num, const struct bio_vec *bvecs, u32 nr_bvec,
  568. struct bvec_iter iter, u64 remote_addr, u32 rkey,
  569. enum dma_data_direction dir)
  570. {
  571. struct ib_device *dev = qp->pd->device;
  572. int ret;
  573. if (nr_bvec == 0 || iter.bi_size == 0)
  574. return -EINVAL;
  575. /*
  576. * iWARP requires MR registration for all RDMA READs. The force_mr
  577. * debug option also mandates MR usage.
  578. */
  579. if (dir == DMA_FROM_DEVICE && rdma_protocol_iwarp(dev, port_num))
  580. return rdma_rw_init_mr_wrs_bvec(ctx, qp, port_num, bvecs,
  581. nr_bvec, &iter, remote_addr,
  582. rkey, dir);
  583. if (unlikely(rdma_rw_force_mr))
  584. return rdma_rw_init_mr_wrs_bvec(ctx, qp, port_num, bvecs,
  585. nr_bvec, &iter, remote_addr,
  586. rkey, dir);
  587. if (nr_bvec == 1)
  588. return rdma_rw_init_single_wr_bvec(ctx, qp, bvecs, &iter,
  589. remote_addr, rkey, dir);
  590. /*
  591. * Try IOVA-based mapping first for multi-bvec transfers.
  592. * IOVA coalesces bvecs into a single DMA-contiguous region,
  593. * reducing the number of WRs needed and avoiding MR overhead.
  594. */
  595. ret = rdma_rw_init_iova_wrs_bvec(ctx, qp, bvecs, &iter, remote_addr,
  596. rkey, dir);
  597. if (ret != -EOPNOTSUPP)
  598. return ret;
  599. /*
  600. * IOVA not available; fall back to the map_wrs path, which maps
  601. * each bvec as a direct SGE. This is always correct: the MR path
  602. * is a throughput optimization, not a correctness requirement.
  603. * (iWARP, which does require MRs, is handled by the check above.)
  604. *
  605. * The rdma_rw_io_needs_mr() gate is not used here because nr_bvec
  606. * is a raw page count that overstates DMA entry demand -- the bvec
  607. * caller has no post-DMA-coalescing segment count, and feeding the
  608. * inflated count into the MR path exhausts the pool on RDMA READs.
  609. */
  610. return rdma_rw_init_map_wrs_bvec(ctx, qp, bvecs, nr_bvec, &iter,
  611. remote_addr, rkey, dir);
  612. }
  613. EXPORT_SYMBOL(rdma_rw_ctx_init_bvec);
  614. /**
  615. * rdma_rw_ctx_signature_init - initialize a RW context with signature offload
  616. * @ctx: context to initialize
  617. * @qp: queue pair to operate on
  618. * @port_num: port num to which the connection is bound
  619. * @sg: scatterlist to READ/WRITE from/to
  620. * @sg_cnt: number of entries in @sg
  621. * @prot_sg: scatterlist to READ/WRITE protection information from/to
  622. * @prot_sg_cnt: number of entries in @prot_sg
  623. * @sig_attrs: signature offloading algorithms
  624. * @remote_addr:remote address to read/write (relative to @rkey)
  625. * @rkey: remote key to operate on
  626. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  627. *
  628. * Returns the number of WQEs that will be needed on the workqueue if
  629. * successful, or a negative error code.
  630. */
  631. int rdma_rw_ctx_signature_init(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  632. u32 port_num, struct scatterlist *sg, u32 sg_cnt,
  633. struct scatterlist *prot_sg, u32 prot_sg_cnt,
  634. struct ib_sig_attrs *sig_attrs,
  635. u64 remote_addr, u32 rkey, enum dma_data_direction dir)
  636. {
  637. struct ib_device *dev = qp->pd->device;
  638. u32 pages_per_mr = rdma_rw_fr_page_list_len(qp->pd->device,
  639. qp->integrity_en);
  640. struct sg_table sgt = {
  641. .sgl = sg,
  642. .orig_nents = sg_cnt,
  643. };
  644. struct sg_table prot_sgt = {
  645. .sgl = prot_sg,
  646. .orig_nents = prot_sg_cnt,
  647. };
  648. struct ib_rdma_wr *rdma_wr;
  649. int count = 0, ret;
  650. if (sg_cnt > pages_per_mr || prot_sg_cnt > pages_per_mr) {
  651. pr_err("SG count too large: sg_cnt=%u, prot_sg_cnt=%u, pages_per_mr=%u\n",
  652. sg_cnt, prot_sg_cnt, pages_per_mr);
  653. return -EINVAL;
  654. }
  655. ret = ib_dma_map_sgtable_attrs(dev, &sgt, dir, 0);
  656. if (ret)
  657. return ret;
  658. if (prot_sg_cnt) {
  659. ret = ib_dma_map_sgtable_attrs(dev, &prot_sgt, dir, 0);
  660. if (ret)
  661. goto out_unmap_sg;
  662. }
  663. ctx->type = RDMA_RW_SIG_MR;
  664. ctx->nr_ops = 1;
  665. ctx->reg = kzalloc_obj(*ctx->reg);
  666. if (!ctx->reg) {
  667. ret = -ENOMEM;
  668. goto out_unmap_prot_sg;
  669. }
  670. ctx->reg->mr = ib_mr_pool_get(qp, &qp->sig_mrs);
  671. if (!ctx->reg->mr) {
  672. ret = -EAGAIN;
  673. goto out_free_ctx;
  674. }
  675. count += rdma_rw_inv_key(ctx->reg);
  676. memcpy(ctx->reg->mr->sig_attrs, sig_attrs, sizeof(struct ib_sig_attrs));
  677. ret = ib_map_mr_sg_pi(ctx->reg->mr, sg, sgt.nents, NULL, prot_sg,
  678. prot_sgt.nents, NULL, SZ_4K);
  679. if (unlikely(ret)) {
  680. pr_err("failed to map PI sg (%u)\n",
  681. sgt.nents + prot_sgt.nents);
  682. goto out_destroy_sig_mr;
  683. }
  684. ctx->reg->reg_wr.wr.opcode = IB_WR_REG_MR_INTEGRITY;
  685. ctx->reg->reg_wr.wr.wr_cqe = NULL;
  686. ctx->reg->reg_wr.wr.num_sge = 0;
  687. ctx->reg->reg_wr.wr.send_flags = 0;
  688. ctx->reg->reg_wr.access = IB_ACCESS_LOCAL_WRITE;
  689. if (rdma_protocol_iwarp(qp->device, port_num))
  690. ctx->reg->reg_wr.access |= IB_ACCESS_REMOTE_WRITE;
  691. ctx->reg->reg_wr.mr = ctx->reg->mr;
  692. ctx->reg->reg_wr.key = ctx->reg->mr->lkey;
  693. count++;
  694. ctx->reg->sge.addr = ctx->reg->mr->iova;
  695. ctx->reg->sge.length = ctx->reg->mr->length;
  696. if (sig_attrs->wire.sig_type == IB_SIG_TYPE_NONE)
  697. ctx->reg->sge.length -= ctx->reg->mr->sig_attrs->meta_length;
  698. rdma_wr = &ctx->reg->wr;
  699. rdma_wr->wr.sg_list = &ctx->reg->sge;
  700. rdma_wr->wr.num_sge = 1;
  701. rdma_wr->remote_addr = remote_addr;
  702. rdma_wr->rkey = rkey;
  703. if (dir == DMA_TO_DEVICE)
  704. rdma_wr->wr.opcode = IB_WR_RDMA_WRITE;
  705. else
  706. rdma_wr->wr.opcode = IB_WR_RDMA_READ;
  707. ctx->reg->reg_wr.wr.next = &rdma_wr->wr;
  708. count++;
  709. return count;
  710. out_destroy_sig_mr:
  711. ib_mr_pool_put(qp, &qp->sig_mrs, ctx->reg->mr);
  712. out_free_ctx:
  713. kfree(ctx->reg);
  714. out_unmap_prot_sg:
  715. if (prot_sgt.nents)
  716. ib_dma_unmap_sgtable_attrs(dev, &prot_sgt, dir, 0);
  717. out_unmap_sg:
  718. ib_dma_unmap_sgtable_attrs(dev, &sgt, dir, 0);
  719. return ret;
  720. }
  721. EXPORT_SYMBOL(rdma_rw_ctx_signature_init);
  722. /*
  723. * Now that we are going to post the WRs we can update the lkey and need_inval
  724. * state on the MRs. If we were doing this at init time, we would get double
  725. * or missing invalidations if a context was initialized but not actually
  726. * posted.
  727. */
  728. static void rdma_rw_update_lkey(struct rdma_rw_reg_ctx *reg, bool need_inval)
  729. {
  730. reg->mr->need_inval = need_inval;
  731. ib_update_fast_reg_key(reg->mr, ib_inc_rkey(reg->mr->lkey));
  732. reg->reg_wr.key = reg->mr->lkey;
  733. reg->sge.lkey = reg->mr->lkey;
  734. }
  735. /**
  736. * rdma_rw_ctx_wrs - return chain of WRs for a RDMA READ or WRITE operation
  737. * @ctx: context to operate on
  738. * @qp: queue pair to operate on
  739. * @port_num: port num to which the connection is bound
  740. * @cqe: completion queue entry for the last WR
  741. * @chain_wr: WR to append to the posted chain
  742. *
  743. * Return the WR chain for the set of RDMA READ/WRITE operations described by
  744. * @ctx, as well as any memory registration operations needed. If @chain_wr
  745. * is non-NULL the WR it points to will be appended to the chain of WRs posted.
  746. * If @chain_wr is not set @cqe must be set so that the caller gets a
  747. * completion notification.
  748. */
  749. struct ib_send_wr *rdma_rw_ctx_wrs(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  750. u32 port_num, struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
  751. {
  752. struct ib_send_wr *first_wr, *last_wr;
  753. int i;
  754. switch (ctx->type) {
  755. case RDMA_RW_SIG_MR:
  756. case RDMA_RW_MR:
  757. for (i = 0; i < ctx->nr_ops; i++) {
  758. rdma_rw_update_lkey(&ctx->reg[i],
  759. ctx->reg[i].wr.wr.opcode !=
  760. IB_WR_RDMA_READ_WITH_INV);
  761. }
  762. if (ctx->reg[0].inv_wr.next)
  763. first_wr = &ctx->reg[0].inv_wr;
  764. else
  765. first_wr = &ctx->reg[0].reg_wr.wr;
  766. last_wr = &ctx->reg[ctx->nr_ops - 1].wr.wr;
  767. break;
  768. case RDMA_RW_IOVA:
  769. first_wr = &ctx->iova.wr.wr;
  770. last_wr = &ctx->iova.wr.wr;
  771. break;
  772. case RDMA_RW_MULTI_WR:
  773. first_wr = &ctx->map.wrs[0].wr;
  774. last_wr = &ctx->map.wrs[ctx->nr_ops - 1].wr;
  775. break;
  776. case RDMA_RW_SINGLE_WR:
  777. first_wr = &ctx->single.wr.wr;
  778. last_wr = &ctx->single.wr.wr;
  779. break;
  780. default:
  781. BUG();
  782. }
  783. if (chain_wr) {
  784. last_wr->next = chain_wr;
  785. } else {
  786. last_wr->wr_cqe = cqe;
  787. last_wr->send_flags |= IB_SEND_SIGNALED;
  788. }
  789. return first_wr;
  790. }
  791. EXPORT_SYMBOL(rdma_rw_ctx_wrs);
  792. /**
  793. * rdma_rw_ctx_post - post a RDMA READ or RDMA WRITE operation
  794. * @ctx: context to operate on
  795. * @qp: queue pair to operate on
  796. * @port_num: port num to which the connection is bound
  797. * @cqe: completion queue entry for the last WR
  798. * @chain_wr: WR to append to the posted chain
  799. *
  800. * Post the set of RDMA READ/WRITE operations described by @ctx, as well as
  801. * any memory registration operations needed. If @chain_wr is non-NULL the
  802. * WR it points to will be appended to the chain of WRs posted. If @chain_wr
  803. * is not set @cqe must be set so that the caller gets a completion
  804. * notification.
  805. */
  806. int rdma_rw_ctx_post(struct rdma_rw_ctx *ctx, struct ib_qp *qp, u32 port_num,
  807. struct ib_cqe *cqe, struct ib_send_wr *chain_wr)
  808. {
  809. struct ib_send_wr *first_wr;
  810. first_wr = rdma_rw_ctx_wrs(ctx, qp, port_num, cqe, chain_wr);
  811. return ib_post_send(qp, first_wr, NULL);
  812. }
  813. EXPORT_SYMBOL(rdma_rw_ctx_post);
  814. /**
  815. * rdma_rw_ctx_destroy - release all resources allocated by rdma_rw_ctx_init
  816. * @ctx: context to release
  817. * @qp: queue pair to operate on
  818. * @port_num: port num to which the connection is bound
  819. * @sg: scatterlist that was used for the READ/WRITE
  820. * @sg_cnt: number of entries in @sg
  821. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  822. */
  823. void rdma_rw_ctx_destroy(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  824. u32 port_num, struct scatterlist *sg, u32 sg_cnt,
  825. enum dma_data_direction dir)
  826. {
  827. int i;
  828. switch (ctx->type) {
  829. case RDMA_RW_MR:
  830. /* Bvec MR contexts must use rdma_rw_ctx_destroy_bvec() */
  831. WARN_ON_ONCE(ctx->reg[0].sgt.sgl);
  832. for (i = 0; i < ctx->nr_ops; i++)
  833. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  834. kfree(ctx->reg);
  835. break;
  836. case RDMA_RW_MULTI_WR:
  837. kfree(ctx->map.wrs);
  838. kfree(ctx->map.sges);
  839. break;
  840. case RDMA_RW_SINGLE_WR:
  841. break;
  842. case RDMA_RW_IOVA:
  843. /* IOVA contexts must use rdma_rw_ctx_destroy_bvec() */
  844. WARN_ON_ONCE(1);
  845. return;
  846. default:
  847. BUG();
  848. break;
  849. }
  850. ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
  851. }
  852. EXPORT_SYMBOL(rdma_rw_ctx_destroy);
  853. /**
  854. * rdma_rw_ctx_destroy_bvec - release resources from rdma_rw_ctx_init_bvec
  855. * @ctx: context to release
  856. * @qp: queue pair to operate on
  857. * @port_num: port num to which the connection is bound (unused)
  858. * @bvecs: bio_vec array that was used for the READ/WRITE (unused)
  859. * @nr_bvec: number of entries in @bvecs
  860. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  861. *
  862. * Releases all resources allocated by a successful rdma_rw_ctx_init_bvec()
  863. * call. Must not be called if rdma_rw_ctx_init_bvec() returned an error.
  864. *
  865. * The @port_num and @bvecs parameters are unused but present for API
  866. * symmetry with rdma_rw_ctx_destroy().
  867. */
  868. void rdma_rw_ctx_destroy_bvec(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  869. u32 __maybe_unused port_num,
  870. const struct bio_vec __maybe_unused *bvecs,
  871. u32 nr_bvec, enum dma_data_direction dir)
  872. {
  873. struct ib_device *dev = qp->pd->device;
  874. u32 i;
  875. switch (ctx->type) {
  876. case RDMA_RW_MR:
  877. for (i = 0; i < ctx->nr_ops; i++)
  878. ib_mr_pool_put(qp, &qp->rdma_mrs, ctx->reg[i].mr);
  879. ib_dma_unmap_sgtable_attrs(dev, &ctx->reg[0].sgt, dir, 0);
  880. kfree(ctx->reg[0].sgt.sgl);
  881. kfree(ctx->reg);
  882. break;
  883. case RDMA_RW_IOVA:
  884. dma_iova_destroy(dev->dma_device, &ctx->iova.state,
  885. ctx->iova.mapped_len, dir, 0);
  886. break;
  887. case RDMA_RW_MULTI_WR:
  888. for (i = 0; i < nr_bvec; i++)
  889. ib_dma_unmap_bvec(dev, ctx->map.sges[i].addr,
  890. ctx->map.sges[i].length, dir);
  891. kfree(ctx->map.sges);
  892. break;
  893. case RDMA_RW_SINGLE_WR:
  894. ib_dma_unmap_bvec(dev, ctx->single.sge.addr,
  895. ctx->single.sge.length, dir);
  896. break;
  897. default:
  898. WARN_ON_ONCE(1);
  899. return;
  900. }
  901. }
  902. EXPORT_SYMBOL(rdma_rw_ctx_destroy_bvec);
  903. /**
  904. * rdma_rw_ctx_destroy_signature - release all resources allocated by
  905. * rdma_rw_ctx_signature_init
  906. * @ctx: context to release
  907. * @qp: queue pair to operate on
  908. * @port_num: port num to which the connection is bound
  909. * @sg: scatterlist that was used for the READ/WRITE
  910. * @sg_cnt: number of entries in @sg
  911. * @prot_sg: scatterlist that was used for the READ/WRITE of the PI
  912. * @prot_sg_cnt: number of entries in @prot_sg
  913. * @dir: %DMA_TO_DEVICE for RDMA WRITE, %DMA_FROM_DEVICE for RDMA READ
  914. */
  915. void rdma_rw_ctx_destroy_signature(struct rdma_rw_ctx *ctx, struct ib_qp *qp,
  916. u32 port_num, struct scatterlist *sg, u32 sg_cnt,
  917. struct scatterlist *prot_sg, u32 prot_sg_cnt,
  918. enum dma_data_direction dir)
  919. {
  920. if (WARN_ON_ONCE(ctx->type != RDMA_RW_SIG_MR))
  921. return;
  922. ib_mr_pool_put(qp, &qp->sig_mrs, ctx->reg->mr);
  923. kfree(ctx->reg);
  924. if (prot_sg_cnt)
  925. ib_dma_unmap_sg(qp->pd->device, prot_sg, prot_sg_cnt, dir);
  926. ib_dma_unmap_sg(qp->pd->device, sg, sg_cnt, dir);
  927. }
  928. EXPORT_SYMBOL(rdma_rw_ctx_destroy_signature);
  929. /**
  930. * rdma_rw_mr_factor - return number of MRs required for a payload
  931. * @device: device handling the connection
  932. * @port_num: port num to which the connection is bound
  933. * @maxpages: maximum payload pages per rdma_rw_ctx
  934. *
  935. * Returns the number of MRs the device requires to move @maxpayload
  936. * bytes. The returned value is used during transport creation to
  937. * compute max_rdma_ctxts and the size of the transport's Send and
  938. * Send Completion Queues.
  939. */
  940. unsigned int rdma_rw_mr_factor(struct ib_device *device, u32 port_num,
  941. unsigned int maxpages)
  942. {
  943. unsigned int mr_pages;
  944. if (rdma_rw_can_use_mr(device, port_num))
  945. mr_pages = rdma_rw_fr_page_list_len(device, false);
  946. else
  947. mr_pages = device->attrs.max_sge_rd;
  948. return DIV_ROUND_UP(maxpages, mr_pages);
  949. }
  950. EXPORT_SYMBOL(rdma_rw_mr_factor);
  951. /**
  952. * rdma_rw_max_send_wr - compute max Send WRs needed for RDMA R/W contexts
  953. * @dev: RDMA device
  954. * @port_num: port number
  955. * @max_rdma_ctxs: number of rdma_rw_ctx structures
  956. * @create_flags: QP create flags (pass IB_QP_CREATE_INTEGRITY_EN if
  957. * data integrity will be enabled on the QP)
  958. *
  959. * Returns the total number of Send Queue entries needed for
  960. * @max_rdma_ctxs. The result accounts for memory registration and
  961. * invalidation work requests when the device requires them.
  962. *
  963. * ULPs use this to size Send Queues and Send CQs before creating a
  964. * Queue Pair.
  965. */
  966. unsigned int rdma_rw_max_send_wr(struct ib_device *dev, u32 port_num,
  967. unsigned int max_rdma_ctxs, u32 create_flags)
  968. {
  969. unsigned int factor = 1;
  970. unsigned int result;
  971. if (create_flags & IB_QP_CREATE_INTEGRITY_EN ||
  972. rdma_rw_can_use_mr(dev, port_num))
  973. factor += 2; /* reg + inv */
  974. if (check_mul_overflow(factor, max_rdma_ctxs, &result))
  975. return UINT_MAX;
  976. return result;
  977. }
  978. EXPORT_SYMBOL(rdma_rw_max_send_wr);
  979. void rdma_rw_init_qp(struct ib_device *dev, struct ib_qp_init_attr *attr)
  980. {
  981. unsigned int factor = 1;
  982. WARN_ON_ONCE(attr->port_num == 0);
  983. /*
  984. * If the device uses MRs to perform RDMA READ or WRITE operations,
  985. * or if data integrity is enabled, account for registration and
  986. * invalidation work requests.
  987. */
  988. if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN ||
  989. rdma_rw_can_use_mr(dev, attr->port_num))
  990. factor += 2; /* reg + inv */
  991. attr->cap.max_send_wr += factor * attr->cap.max_rdma_ctxs;
  992. /*
  993. * The device might not support all we need, and we'll have to
  994. * live with what we get.
  995. */
  996. attr->cap.max_send_wr =
  997. min_t(u32, attr->cap.max_send_wr, dev->attrs.max_qp_wr);
  998. }
  999. int rdma_rw_init_mrs(struct ib_qp *qp, struct ib_qp_init_attr *attr)
  1000. {
  1001. struct ib_device *dev = qp->pd->device;
  1002. u32 nr_mrs = 0, nr_sig_mrs = 0, max_num_sg = 0;
  1003. int ret = 0;
  1004. if (attr->create_flags & IB_QP_CREATE_INTEGRITY_EN) {
  1005. nr_sig_mrs = attr->cap.max_rdma_ctxs;
  1006. nr_mrs = attr->cap.max_rdma_ctxs;
  1007. max_num_sg = rdma_rw_fr_page_list_len(dev, true);
  1008. } else if (rdma_rw_can_use_mr(dev, attr->port_num)) {
  1009. nr_mrs = attr->cap.max_rdma_ctxs;
  1010. max_num_sg = rdma_rw_fr_page_list_len(dev, false);
  1011. }
  1012. if (nr_mrs) {
  1013. ret = ib_mr_pool_init(qp, &qp->rdma_mrs, nr_mrs,
  1014. IB_MR_TYPE_MEM_REG,
  1015. max_num_sg, 0);
  1016. if (ret) {
  1017. pr_err("%s: failed to allocated %u MRs\n",
  1018. __func__, nr_mrs);
  1019. return ret;
  1020. }
  1021. }
  1022. if (nr_sig_mrs) {
  1023. ret = ib_mr_pool_init(qp, &qp->sig_mrs, nr_sig_mrs,
  1024. IB_MR_TYPE_INTEGRITY, max_num_sg, max_num_sg);
  1025. if (ret) {
  1026. pr_err("%s: failed to allocated %u SIG MRs\n",
  1027. __func__, nr_sig_mrs);
  1028. goto out_free_rdma_mrs;
  1029. }
  1030. }
  1031. return 0;
  1032. out_free_rdma_mrs:
  1033. ib_mr_pool_destroy(qp, &qp->rdma_mrs);
  1034. return ret;
  1035. }
  1036. void rdma_rw_cleanup_mrs(struct ib_qp *qp)
  1037. {
  1038. ib_mr_pool_destroy(qp, &qp->sig_mrs);
  1039. ib_mr_pool_destroy(qp, &qp->rdma_mrs);
  1040. }