mcp4131.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Industrial I/O driver for Microchip digital potentiometers
  4. *
  5. * Copyright (c) 2016 Slawomir Stepien
  6. * Based on: Peter Rosin's code from mcp4531.c
  7. *
  8. * Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22060b.pdf
  9. *
  10. * DEVID #Wipers #Positions Resistor Opts (kOhm)
  11. * mcp4131 1 129 5, 10, 50, 100
  12. * mcp4132 1 129 5, 10, 50, 100
  13. * mcp4141 1 129 5, 10, 50, 100
  14. * mcp4142 1 129 5, 10, 50, 100
  15. * mcp4151 1 257 5, 10, 50, 100
  16. * mcp4152 1 257 5, 10, 50, 100
  17. * mcp4161 1 257 5, 10, 50, 100
  18. * mcp4162 1 257 5, 10, 50, 100
  19. * mcp4231 2 129 5, 10, 50, 100
  20. * mcp4232 2 129 5, 10, 50, 100
  21. * mcp4241 2 129 5, 10, 50, 100
  22. * mcp4242 2 129 5, 10, 50, 100
  23. * mcp4251 2 257 5, 10, 50, 100
  24. * mcp4252 2 257 5, 10, 50, 100
  25. * mcp4261 2 257 5, 10, 50, 100
  26. * mcp4262 2 257 5, 10, 50, 100
  27. */
  28. /*
  29. * TODO:
  30. * 1. Write wiper setting to EEPROM for EEPROM capable models.
  31. */
  32. #include <linux/cache.h>
  33. #include <linux/err.h>
  34. #include <linux/iio/iio.h>
  35. #include <linux/iio/types.h>
  36. #include <linux/module.h>
  37. #include <linux/mod_devicetable.h>
  38. #include <linux/mutex.h>
  39. #include <linux/property.h>
  40. #include <linux/spi/spi.h>
  41. #define MCP4131_WRITE (0x00 << 2)
  42. #define MCP4131_READ (0x03 << 2)
  43. #define MCP4131_WIPER_SHIFT 4
  44. #define MCP4131_CMDERR(r) ((r[0]) & 0x02)
  45. #define MCP4131_RAW(r) ((r[0]) == 0xff ? 0x100 : (r[1]))
  46. struct mcp4131_cfg {
  47. int wipers;
  48. int max_pos;
  49. int kohms;
  50. };
  51. enum mcp4131_type {
  52. MCP413x_502 = 0,
  53. MCP413x_103,
  54. MCP413x_503,
  55. MCP413x_104,
  56. MCP414x_502,
  57. MCP414x_103,
  58. MCP414x_503,
  59. MCP414x_104,
  60. MCP415x_502,
  61. MCP415x_103,
  62. MCP415x_503,
  63. MCP415x_104,
  64. MCP416x_502,
  65. MCP416x_103,
  66. MCP416x_503,
  67. MCP416x_104,
  68. MCP423x_502,
  69. MCP423x_103,
  70. MCP423x_503,
  71. MCP423x_104,
  72. MCP424x_502,
  73. MCP424x_103,
  74. MCP424x_503,
  75. MCP424x_104,
  76. MCP425x_502,
  77. MCP425x_103,
  78. MCP425x_503,
  79. MCP425x_104,
  80. MCP426x_502,
  81. MCP426x_103,
  82. MCP426x_503,
  83. MCP426x_104,
  84. };
  85. static const struct mcp4131_cfg mcp4131_cfg[] = {
  86. [MCP413x_502] = { .wipers = 1, .max_pos = 128, .kohms = 5, },
  87. [MCP413x_103] = { .wipers = 1, .max_pos = 128, .kohms = 10, },
  88. [MCP413x_503] = { .wipers = 1, .max_pos = 128, .kohms = 50, },
  89. [MCP413x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
  90. [MCP414x_502] = { .wipers = 1, .max_pos = 128, .kohms = 5, },
  91. [MCP414x_103] = { .wipers = 1, .max_pos = 128, .kohms = 10, },
  92. [MCP414x_503] = { .wipers = 1, .max_pos = 128, .kohms = 50, },
  93. [MCP414x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
  94. [MCP415x_502] = { .wipers = 1, .max_pos = 256, .kohms = 5, },
  95. [MCP415x_103] = { .wipers = 1, .max_pos = 256, .kohms = 10, },
  96. [MCP415x_503] = { .wipers = 1, .max_pos = 256, .kohms = 50, },
  97. [MCP415x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
  98. [MCP416x_502] = { .wipers = 1, .max_pos = 256, .kohms = 5, },
  99. [MCP416x_103] = { .wipers = 1, .max_pos = 256, .kohms = 10, },
  100. [MCP416x_503] = { .wipers = 1, .max_pos = 256, .kohms = 50, },
  101. [MCP416x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
  102. [MCP423x_502] = { .wipers = 2, .max_pos = 128, .kohms = 5, },
  103. [MCP423x_103] = { .wipers = 2, .max_pos = 128, .kohms = 10, },
  104. [MCP423x_503] = { .wipers = 2, .max_pos = 128, .kohms = 50, },
  105. [MCP423x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
  106. [MCP424x_502] = { .wipers = 2, .max_pos = 128, .kohms = 5, },
  107. [MCP424x_103] = { .wipers = 2, .max_pos = 128, .kohms = 10, },
  108. [MCP424x_503] = { .wipers = 2, .max_pos = 128, .kohms = 50, },
  109. [MCP424x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
  110. [MCP425x_502] = { .wipers = 2, .max_pos = 256, .kohms = 5, },
  111. [MCP425x_103] = { .wipers = 2, .max_pos = 256, .kohms = 10, },
  112. [MCP425x_503] = { .wipers = 2, .max_pos = 256, .kohms = 50, },
  113. [MCP425x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
  114. [MCP426x_502] = { .wipers = 2, .max_pos = 256, .kohms = 5, },
  115. [MCP426x_103] = { .wipers = 2, .max_pos = 256, .kohms = 10, },
  116. [MCP426x_503] = { .wipers = 2, .max_pos = 256, .kohms = 50, },
  117. [MCP426x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
  118. };
  119. struct mcp4131_data {
  120. struct spi_device *spi;
  121. const struct mcp4131_cfg *cfg;
  122. struct mutex lock;
  123. u8 buf[2] __aligned(IIO_DMA_MINALIGN);
  124. };
  125. #define MCP4131_CHANNEL(ch) { \
  126. .type = IIO_RESISTANCE, \
  127. .indexed = 1, \
  128. .output = 1, \
  129. .channel = (ch), \
  130. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  131. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  132. }
  133. static const struct iio_chan_spec mcp4131_channels[] = {
  134. MCP4131_CHANNEL(0),
  135. MCP4131_CHANNEL(1),
  136. };
  137. static int mcp4131_read(struct spi_device *spi, void *buf, size_t len)
  138. {
  139. struct spi_transfer t = {
  140. .tx_buf = buf, /* We need to send addr, cmd and 12 bits */
  141. .rx_buf = buf,
  142. .len = len,
  143. };
  144. struct spi_message m;
  145. spi_message_init(&m);
  146. spi_message_add_tail(&t, &m);
  147. return spi_sync(spi, &m);
  148. }
  149. static int mcp4131_read_raw(struct iio_dev *indio_dev,
  150. struct iio_chan_spec const *chan,
  151. int *val, int *val2, long mask)
  152. {
  153. int err;
  154. struct mcp4131_data *data = iio_priv(indio_dev);
  155. int address = chan->channel;
  156. switch (mask) {
  157. case IIO_CHAN_INFO_RAW:
  158. mutex_lock(&data->lock);
  159. data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ;
  160. data->buf[1] = 0;
  161. err = mcp4131_read(data->spi, data->buf, 2);
  162. if (err) {
  163. mutex_unlock(&data->lock);
  164. return err;
  165. }
  166. /* Error, bad address/command combination */
  167. if (!MCP4131_CMDERR(data->buf)) {
  168. mutex_unlock(&data->lock);
  169. return -EIO;
  170. }
  171. *val = MCP4131_RAW(data->buf);
  172. mutex_unlock(&data->lock);
  173. return IIO_VAL_INT;
  174. case IIO_CHAN_INFO_SCALE:
  175. *val = 1000 * data->cfg->kohms;
  176. *val2 = data->cfg->max_pos;
  177. return IIO_VAL_FRACTIONAL;
  178. }
  179. return -EINVAL;
  180. }
  181. static int mcp4131_write_raw(struct iio_dev *indio_dev,
  182. struct iio_chan_spec const *chan,
  183. int val, int val2, long mask)
  184. {
  185. int err;
  186. struct mcp4131_data *data = iio_priv(indio_dev);
  187. int address = chan->channel << MCP4131_WIPER_SHIFT;
  188. switch (mask) {
  189. case IIO_CHAN_INFO_RAW:
  190. if (val > data->cfg->max_pos || val < 0)
  191. return -EINVAL;
  192. break;
  193. default:
  194. return -EINVAL;
  195. }
  196. mutex_lock(&data->lock);
  197. data->buf[0] = address;
  198. data->buf[0] |= MCP4131_WRITE | (val >> 8);
  199. data->buf[1] = val & 0xFF; /* 8 bits here */
  200. err = spi_write(data->spi, data->buf, 2);
  201. mutex_unlock(&data->lock);
  202. return err;
  203. }
  204. static const struct iio_info mcp4131_info = {
  205. .read_raw = mcp4131_read_raw,
  206. .write_raw = mcp4131_write_raw,
  207. };
  208. static int mcp4131_probe(struct spi_device *spi)
  209. {
  210. int err;
  211. struct device *dev = &spi->dev;
  212. unsigned long devid;
  213. struct mcp4131_data *data;
  214. struct iio_dev *indio_dev;
  215. indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
  216. if (!indio_dev)
  217. return -ENOMEM;
  218. data = iio_priv(indio_dev);
  219. spi_set_drvdata(spi, indio_dev);
  220. data->spi = spi;
  221. data->cfg = device_get_match_data(&spi->dev);
  222. if (!data->cfg) {
  223. devid = spi_get_device_id(spi)->driver_data;
  224. data->cfg = &mcp4131_cfg[devid];
  225. }
  226. mutex_init(&data->lock);
  227. indio_dev->info = &mcp4131_info;
  228. indio_dev->channels = mcp4131_channels;
  229. indio_dev->num_channels = data->cfg->wipers;
  230. indio_dev->name = spi_get_device_id(spi)->name;
  231. err = devm_iio_device_register(dev, indio_dev);
  232. if (err) {
  233. dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name);
  234. return err;
  235. }
  236. return 0;
  237. }
  238. static const struct of_device_id mcp4131_dt_ids[] = {
  239. { .compatible = "microchip,mcp4131-502",
  240. .data = &mcp4131_cfg[MCP413x_502] },
  241. { .compatible = "microchip,mcp4131-103",
  242. .data = &mcp4131_cfg[MCP413x_103] },
  243. { .compatible = "microchip,mcp4131-503",
  244. .data = &mcp4131_cfg[MCP413x_503] },
  245. { .compatible = "microchip,mcp4131-104",
  246. .data = &mcp4131_cfg[MCP413x_104] },
  247. { .compatible = "microchip,mcp4132-502",
  248. .data = &mcp4131_cfg[MCP413x_502] },
  249. { .compatible = "microchip,mcp4132-103",
  250. .data = &mcp4131_cfg[MCP413x_103] },
  251. { .compatible = "microchip,mcp4132-503",
  252. .data = &mcp4131_cfg[MCP413x_503] },
  253. { .compatible = "microchip,mcp4132-104",
  254. .data = &mcp4131_cfg[MCP413x_104] },
  255. { .compatible = "microchip,mcp4141-502",
  256. .data = &mcp4131_cfg[MCP414x_502] },
  257. { .compatible = "microchip,mcp4141-103",
  258. .data = &mcp4131_cfg[MCP414x_103] },
  259. { .compatible = "microchip,mcp4141-503",
  260. .data = &mcp4131_cfg[MCP414x_503] },
  261. { .compatible = "microchip,mcp4141-104",
  262. .data = &mcp4131_cfg[MCP414x_104] },
  263. { .compatible = "microchip,mcp4142-502",
  264. .data = &mcp4131_cfg[MCP414x_502] },
  265. { .compatible = "microchip,mcp4142-103",
  266. .data = &mcp4131_cfg[MCP414x_103] },
  267. { .compatible = "microchip,mcp4142-503",
  268. .data = &mcp4131_cfg[MCP414x_503] },
  269. { .compatible = "microchip,mcp4142-104",
  270. .data = &mcp4131_cfg[MCP414x_104] },
  271. { .compatible = "microchip,mcp4151-502",
  272. .data = &mcp4131_cfg[MCP415x_502] },
  273. { .compatible = "microchip,mcp4151-103",
  274. .data = &mcp4131_cfg[MCP415x_103] },
  275. { .compatible = "microchip,mcp4151-503",
  276. .data = &mcp4131_cfg[MCP415x_503] },
  277. { .compatible = "microchip,mcp4151-104",
  278. .data = &mcp4131_cfg[MCP415x_104] },
  279. { .compatible = "microchip,mcp4152-502",
  280. .data = &mcp4131_cfg[MCP415x_502] },
  281. { .compatible = "microchip,mcp4152-103",
  282. .data = &mcp4131_cfg[MCP415x_103] },
  283. { .compatible = "microchip,mcp4152-503",
  284. .data = &mcp4131_cfg[MCP415x_503] },
  285. { .compatible = "microchip,mcp4152-104",
  286. .data = &mcp4131_cfg[MCP415x_104] },
  287. { .compatible = "microchip,mcp4161-502",
  288. .data = &mcp4131_cfg[MCP416x_502] },
  289. { .compatible = "microchip,mcp4161-103",
  290. .data = &mcp4131_cfg[MCP416x_103] },
  291. { .compatible = "microchip,mcp4161-503",
  292. .data = &mcp4131_cfg[MCP416x_503] },
  293. { .compatible = "microchip,mcp4161-104",
  294. .data = &mcp4131_cfg[MCP416x_104] },
  295. { .compatible = "microchip,mcp4162-502",
  296. .data = &mcp4131_cfg[MCP416x_502] },
  297. { .compatible = "microchip,mcp4162-103",
  298. .data = &mcp4131_cfg[MCP416x_103] },
  299. { .compatible = "microchip,mcp4162-503",
  300. .data = &mcp4131_cfg[MCP416x_503] },
  301. { .compatible = "microchip,mcp4162-104",
  302. .data = &mcp4131_cfg[MCP416x_104] },
  303. { .compatible = "microchip,mcp4231-502",
  304. .data = &mcp4131_cfg[MCP423x_502] },
  305. { .compatible = "microchip,mcp4231-103",
  306. .data = &mcp4131_cfg[MCP423x_103] },
  307. { .compatible = "microchip,mcp4231-503",
  308. .data = &mcp4131_cfg[MCP423x_503] },
  309. { .compatible = "microchip,mcp4231-104",
  310. .data = &mcp4131_cfg[MCP423x_104] },
  311. { .compatible = "microchip,mcp4232-502",
  312. .data = &mcp4131_cfg[MCP423x_502] },
  313. { .compatible = "microchip,mcp4232-103",
  314. .data = &mcp4131_cfg[MCP423x_103] },
  315. { .compatible = "microchip,mcp4232-503",
  316. .data = &mcp4131_cfg[MCP423x_503] },
  317. { .compatible = "microchip,mcp4232-104",
  318. .data = &mcp4131_cfg[MCP423x_104] },
  319. { .compatible = "microchip,mcp4241-502",
  320. .data = &mcp4131_cfg[MCP424x_502] },
  321. { .compatible = "microchip,mcp4241-103",
  322. .data = &mcp4131_cfg[MCP424x_103] },
  323. { .compatible = "microchip,mcp4241-503",
  324. .data = &mcp4131_cfg[MCP424x_503] },
  325. { .compatible = "microchip,mcp4241-104",
  326. .data = &mcp4131_cfg[MCP424x_104] },
  327. { .compatible = "microchip,mcp4242-502",
  328. .data = &mcp4131_cfg[MCP424x_502] },
  329. { .compatible = "microchip,mcp4242-103",
  330. .data = &mcp4131_cfg[MCP424x_103] },
  331. { .compatible = "microchip,mcp4242-503",
  332. .data = &mcp4131_cfg[MCP424x_503] },
  333. { .compatible = "microchip,mcp4242-104",
  334. .data = &mcp4131_cfg[MCP424x_104] },
  335. { .compatible = "microchip,mcp4251-502",
  336. .data = &mcp4131_cfg[MCP425x_502] },
  337. { .compatible = "microchip,mcp4251-103",
  338. .data = &mcp4131_cfg[MCP425x_103] },
  339. { .compatible = "microchip,mcp4251-503",
  340. .data = &mcp4131_cfg[MCP425x_503] },
  341. { .compatible = "microchip,mcp4251-104",
  342. .data = &mcp4131_cfg[MCP425x_104] },
  343. { .compatible = "microchip,mcp4252-502",
  344. .data = &mcp4131_cfg[MCP425x_502] },
  345. { .compatible = "microchip,mcp4252-103",
  346. .data = &mcp4131_cfg[MCP425x_103] },
  347. { .compatible = "microchip,mcp4252-503",
  348. .data = &mcp4131_cfg[MCP425x_503] },
  349. { .compatible = "microchip,mcp4252-104",
  350. .data = &mcp4131_cfg[MCP425x_104] },
  351. { .compatible = "microchip,mcp4261-502",
  352. .data = &mcp4131_cfg[MCP426x_502] },
  353. { .compatible = "microchip,mcp4261-103",
  354. .data = &mcp4131_cfg[MCP426x_103] },
  355. { .compatible = "microchip,mcp4261-503",
  356. .data = &mcp4131_cfg[MCP426x_503] },
  357. { .compatible = "microchip,mcp4261-104",
  358. .data = &mcp4131_cfg[MCP426x_104] },
  359. { .compatible = "microchip,mcp4262-502",
  360. .data = &mcp4131_cfg[MCP426x_502] },
  361. { .compatible = "microchip,mcp4262-103",
  362. .data = &mcp4131_cfg[MCP426x_103] },
  363. { .compatible = "microchip,mcp4262-503",
  364. .data = &mcp4131_cfg[MCP426x_503] },
  365. { .compatible = "microchip,mcp4262-104",
  366. .data = &mcp4131_cfg[MCP426x_104] },
  367. { }
  368. };
  369. MODULE_DEVICE_TABLE(of, mcp4131_dt_ids);
  370. static const struct spi_device_id mcp4131_id[] = {
  371. { "mcp4131-502", MCP413x_502 },
  372. { "mcp4131-103", MCP413x_103 },
  373. { "mcp4131-503", MCP413x_503 },
  374. { "mcp4131-104", MCP413x_104 },
  375. { "mcp4132-502", MCP413x_502 },
  376. { "mcp4132-103", MCP413x_103 },
  377. { "mcp4132-503", MCP413x_503 },
  378. { "mcp4132-104", MCP413x_104 },
  379. { "mcp4141-502", MCP414x_502 },
  380. { "mcp4141-103", MCP414x_103 },
  381. { "mcp4141-503", MCP414x_503 },
  382. { "mcp4141-104", MCP414x_104 },
  383. { "mcp4142-502", MCP414x_502 },
  384. { "mcp4142-103", MCP414x_103 },
  385. { "mcp4142-503", MCP414x_503 },
  386. { "mcp4142-104", MCP414x_104 },
  387. { "mcp4151-502", MCP415x_502 },
  388. { "mcp4151-103", MCP415x_103 },
  389. { "mcp4151-503", MCP415x_503 },
  390. { "mcp4151-104", MCP415x_104 },
  391. { "mcp4152-502", MCP415x_502 },
  392. { "mcp4152-103", MCP415x_103 },
  393. { "mcp4152-503", MCP415x_503 },
  394. { "mcp4152-104", MCP415x_104 },
  395. { "mcp4161-502", MCP416x_502 },
  396. { "mcp4161-103", MCP416x_103 },
  397. { "mcp4161-503", MCP416x_503 },
  398. { "mcp4161-104", MCP416x_104 },
  399. { "mcp4162-502", MCP416x_502 },
  400. { "mcp4162-103", MCP416x_103 },
  401. { "mcp4162-503", MCP416x_503 },
  402. { "mcp4162-104", MCP416x_104 },
  403. { "mcp4231-502", MCP423x_502 },
  404. { "mcp4231-103", MCP423x_103 },
  405. { "mcp4231-503", MCP423x_503 },
  406. { "mcp4231-104", MCP423x_104 },
  407. { "mcp4232-502", MCP423x_502 },
  408. { "mcp4232-103", MCP423x_103 },
  409. { "mcp4232-503", MCP423x_503 },
  410. { "mcp4232-104", MCP423x_104 },
  411. { "mcp4241-502", MCP424x_502 },
  412. { "mcp4241-103", MCP424x_103 },
  413. { "mcp4241-503", MCP424x_503 },
  414. { "mcp4241-104", MCP424x_104 },
  415. { "mcp4242-502", MCP424x_502 },
  416. { "mcp4242-103", MCP424x_103 },
  417. { "mcp4242-503", MCP424x_503 },
  418. { "mcp4242-104", MCP424x_104 },
  419. { "mcp4251-502", MCP425x_502 },
  420. { "mcp4251-103", MCP425x_103 },
  421. { "mcp4251-503", MCP425x_503 },
  422. { "mcp4251-104", MCP425x_104 },
  423. { "mcp4252-502", MCP425x_502 },
  424. { "mcp4252-103", MCP425x_103 },
  425. { "mcp4252-503", MCP425x_503 },
  426. { "mcp4252-104", MCP425x_104 },
  427. { "mcp4261-502", MCP426x_502 },
  428. { "mcp4261-103", MCP426x_103 },
  429. { "mcp4261-503", MCP426x_503 },
  430. { "mcp4261-104", MCP426x_104 },
  431. { "mcp4262-502", MCP426x_502 },
  432. { "mcp4262-103", MCP426x_103 },
  433. { "mcp4262-503", MCP426x_503 },
  434. { "mcp4262-104", MCP426x_104 },
  435. { }
  436. };
  437. MODULE_DEVICE_TABLE(spi, mcp4131_id);
  438. static struct spi_driver mcp4131_driver = {
  439. .driver = {
  440. .name = "mcp4131",
  441. .of_match_table = mcp4131_dt_ids,
  442. },
  443. .probe = mcp4131_probe,
  444. .id_table = mcp4131_id,
  445. };
  446. module_spi_driver(mcp4131_driver);
  447. MODULE_AUTHOR("Slawomir Stepien <sst@poczta.fm>");
  448. MODULE_DESCRIPTION("MCP4131 digital potentiometer");
  449. MODULE_LICENSE("GPL v2");