ad5791.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD5760, AD5780, AD5781, AD5790, AD5791 Voltage Output Digital to Analog
  4. * Converter
  5. *
  6. * Copyright 2011 Analog Devices Inc.
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/delay.h>
  10. #include <linux/device.h>
  11. #include <linux/fs.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/regulator/consumer.h>
  16. #include <linux/slab.h>
  17. #include <linux/spi/offload/consumer.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/sysfs.h>
  20. #include <linux/units.h>
  21. #include <linux/iio/buffer-dmaengine.h>
  22. #include <linux/iio/dac/ad5791.h>
  23. #include <linux/iio/iio.h>
  24. #include <linux/iio/sysfs.h>
  25. #define AD5791_DAC_MASK GENMASK(19, 0)
  26. #define AD5791_CMD_READ BIT(23)
  27. #define AD5791_CMD_WRITE 0
  28. #define AD5791_ADDR(addr) ((addr) << 20)
  29. /* Registers */
  30. #define AD5791_ADDR_NOOP 0
  31. #define AD5791_ADDR_DAC0 1
  32. #define AD5791_ADDR_CTRL 2
  33. #define AD5791_ADDR_CLRCODE 3
  34. #define AD5791_ADDR_SW_CTRL 4
  35. /* Control Register */
  36. #define AD5791_CTRL_RBUF BIT(1)
  37. #define AD5791_CTRL_OPGND BIT(2)
  38. #define AD5791_CTRL_DACTRI BIT(3)
  39. #define AD5791_CTRL_BIN2SC BIT(4)
  40. #define AD5791_CTRL_SDODIS BIT(5)
  41. #define AD5761_CTRL_LINCOMP(x) ((x) << 6)
  42. #define AD5791_LINCOMP_0_10 0
  43. #define AD5791_LINCOMP_10_12 1
  44. #define AD5791_LINCOMP_12_16 2
  45. #define AD5791_LINCOMP_16_19 3
  46. #define AD5791_LINCOMP_19_20 12
  47. #define AD5780_LINCOMP_0_10 0
  48. #define AD5780_LINCOMP_10_20 12
  49. /* Software Control Register */
  50. #define AD5791_SWCTRL_LDAC BIT(0)
  51. #define AD5791_SWCTRL_CLR BIT(1)
  52. #define AD5791_SWCTRL_RESET BIT(2)
  53. #define AD5791_DAC_PWRDN_6K 0
  54. #define AD5791_DAC_PWRDN_3STATE 1
  55. /**
  56. * struct ad5791_chip_info - chip specific information
  57. * @name: name of the dac chip
  58. * @channel: channel specification
  59. * @channel_offload: channel specification for offload
  60. * @get_lin_comp: function pointer to the device specific function
  61. */
  62. struct ad5791_chip_info {
  63. const char *name;
  64. const struct iio_chan_spec channel;
  65. const struct iio_chan_spec channel_offload;
  66. int (*get_lin_comp)(unsigned int span);
  67. };
  68. /**
  69. * struct ad5791_state - driver instance specific data
  70. * @spi: spi_device
  71. * @gpio_reset: reset gpio
  72. * @gpio_clear: clear gpio
  73. * @gpio_ldac: load dac gpio
  74. * @chip_info: chip model specific constants
  75. * @offload_msg: spi message used for offload
  76. * @offload_xfer: spi transfer used for offload
  77. * @offload: offload device
  78. * @offload_trigger: offload trigger
  79. * @offload_trigger_hz: offload sample rate
  80. * @vref_mv: actual reference voltage used
  81. * @vref_neg_mv: voltage of the negative supply
  82. * @ctrl: control register cache
  83. * @pwr_down_mode: current power down mode
  84. * @pwr_down: true if device is powered down
  85. * @data: spi transfer buffers
  86. */
  87. struct ad5791_state {
  88. struct spi_device *spi;
  89. struct gpio_desc *gpio_reset;
  90. struct gpio_desc *gpio_clear;
  91. struct gpio_desc *gpio_ldac;
  92. const struct ad5791_chip_info *chip_info;
  93. struct spi_message offload_msg;
  94. struct spi_transfer offload_xfer;
  95. struct spi_offload *offload;
  96. struct spi_offload_trigger *offload_trigger;
  97. unsigned int offload_trigger_hz;
  98. unsigned short vref_mv;
  99. unsigned int vref_neg_mv;
  100. unsigned ctrl;
  101. unsigned pwr_down_mode;
  102. bool pwr_down;
  103. union {
  104. __be32 d32;
  105. u8 d8[4];
  106. } data[3] __aligned(IIO_DMA_MINALIGN);
  107. };
  108. static int ad5791_spi_write(struct ad5791_state *st, u8 addr, u32 val)
  109. {
  110. st->data[0].d32 = cpu_to_be32(AD5791_CMD_WRITE |
  111. AD5791_ADDR(addr) |
  112. (val & AD5791_DAC_MASK));
  113. return spi_write(st->spi, &st->data[0].d8[1], 3);
  114. }
  115. static int ad5791_spi_read(struct ad5791_state *st, u8 addr, u32 *val)
  116. {
  117. int ret;
  118. struct spi_transfer xfers[] = {
  119. {
  120. .tx_buf = &st->data[0].d8[1],
  121. .len = 3,
  122. .cs_change = 1,
  123. }, {
  124. .tx_buf = &st->data[1].d8[1],
  125. .rx_buf = &st->data[2].d8[1],
  126. .len = 3,
  127. },
  128. };
  129. st->data[0].d32 = cpu_to_be32(AD5791_CMD_READ |
  130. AD5791_ADDR(addr));
  131. st->data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP));
  132. ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
  133. *val = be32_to_cpu(st->data[2].d32);
  134. return ret;
  135. }
  136. static const char * const ad5791_powerdown_modes[] = {
  137. "6kohm_to_gnd",
  138. "three_state",
  139. };
  140. static int ad5791_get_powerdown_mode(struct iio_dev *indio_dev,
  141. const struct iio_chan_spec *chan)
  142. {
  143. struct ad5791_state *st = iio_priv(indio_dev);
  144. return st->pwr_down_mode;
  145. }
  146. static int ad5791_set_powerdown_mode(struct iio_dev *indio_dev,
  147. const struct iio_chan_spec *chan, unsigned int mode)
  148. {
  149. struct ad5791_state *st = iio_priv(indio_dev);
  150. st->pwr_down_mode = mode;
  151. return 0;
  152. }
  153. static const struct iio_enum ad5791_powerdown_mode_enum = {
  154. .items = ad5791_powerdown_modes,
  155. .num_items = ARRAY_SIZE(ad5791_powerdown_modes),
  156. .get = ad5791_get_powerdown_mode,
  157. .set = ad5791_set_powerdown_mode,
  158. };
  159. static ssize_t ad5791_read_dac_powerdown(struct iio_dev *indio_dev,
  160. uintptr_t private, const struct iio_chan_spec *chan, char *buf)
  161. {
  162. struct ad5791_state *st = iio_priv(indio_dev);
  163. return sysfs_emit(buf, "%d\n", st->pwr_down);
  164. }
  165. static ssize_t ad5791_write_dac_powerdown(struct iio_dev *indio_dev,
  166. uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
  167. size_t len)
  168. {
  169. bool pwr_down;
  170. int ret;
  171. struct ad5791_state *st = iio_priv(indio_dev);
  172. ret = kstrtobool(buf, &pwr_down);
  173. if (ret)
  174. return ret;
  175. if (!pwr_down) {
  176. st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
  177. } else {
  178. if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K)
  179. st->ctrl |= AD5791_CTRL_OPGND;
  180. else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE)
  181. st->ctrl |= AD5791_CTRL_DACTRI;
  182. }
  183. st->pwr_down = pwr_down;
  184. ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl);
  185. return ret ? ret : len;
  186. }
  187. static int ad5791_get_lin_comp(unsigned int span)
  188. {
  189. if (span <= 10000)
  190. return AD5791_LINCOMP_0_10;
  191. else if (span <= 12000)
  192. return AD5791_LINCOMP_10_12;
  193. else if (span <= 16000)
  194. return AD5791_LINCOMP_12_16;
  195. else if (span <= 19000)
  196. return AD5791_LINCOMP_16_19;
  197. else
  198. return AD5791_LINCOMP_19_20;
  199. }
  200. static int ad5780_get_lin_comp(unsigned int span)
  201. {
  202. if (span <= 10000)
  203. return AD5780_LINCOMP_0_10;
  204. else
  205. return AD5780_LINCOMP_10_20;
  206. }
  207. static int ad5791_set_sample_freq(struct ad5791_state *st, int val)
  208. {
  209. struct spi_offload_trigger_config config = {
  210. .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
  211. .periodic = {
  212. .frequency_hz = val,
  213. },
  214. };
  215. int ret;
  216. ret = spi_offload_trigger_validate(st->offload_trigger, &config);
  217. if (ret)
  218. return ret;
  219. st->offload_trigger_hz = config.periodic.frequency_hz;
  220. return 0;
  221. }
  222. static int ad5791_read_raw(struct iio_dev *indio_dev,
  223. struct iio_chan_spec const *chan,
  224. int *val,
  225. int *val2,
  226. long m)
  227. {
  228. struct ad5791_state *st = iio_priv(indio_dev);
  229. u64 val64;
  230. int ret;
  231. switch (m) {
  232. case IIO_CHAN_INFO_RAW:
  233. ret = ad5791_spi_read(st, chan->address, val);
  234. if (ret)
  235. return ret;
  236. *val &= AD5791_DAC_MASK;
  237. *val >>= chan->scan_type.shift;
  238. return IIO_VAL_INT;
  239. case IIO_CHAN_INFO_SCALE:
  240. *val = st->vref_mv;
  241. *val2 = (1 << chan->scan_type.realbits) - 1;
  242. return IIO_VAL_FRACTIONAL;
  243. case IIO_CHAN_INFO_OFFSET:
  244. val64 = (((u64)st->vref_neg_mv) << chan->scan_type.realbits);
  245. do_div(val64, st->vref_mv);
  246. *val = -val64;
  247. return IIO_VAL_INT;
  248. case IIO_CHAN_INFO_SAMP_FREQ:
  249. *val = st->offload_trigger_hz;
  250. return IIO_VAL_INT;
  251. default:
  252. return -EINVAL;
  253. }
  254. };
  255. static const struct iio_chan_spec_ext_info ad5791_ext_info[] = {
  256. {
  257. .name = "powerdown",
  258. .shared = IIO_SHARED_BY_TYPE,
  259. .read = ad5791_read_dac_powerdown,
  260. .write = ad5791_write_dac_powerdown,
  261. },
  262. IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
  263. &ad5791_powerdown_mode_enum),
  264. IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &ad5791_powerdown_mode_enum),
  265. { }
  266. };
  267. #define AD5791_DEFINE_CHIP_INFO(_name, bits, _shift, _lin_comp) \
  268. static const struct ad5791_chip_info _name##_chip_info = { \
  269. .name = #_name, \
  270. .get_lin_comp = &(_lin_comp), \
  271. .channel = { \
  272. .type = IIO_VOLTAGE, \
  273. .output = 1, \
  274. .indexed = 1, \
  275. .address = AD5791_ADDR_DAC0, \
  276. .channel = 0, \
  277. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  278. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  279. BIT(IIO_CHAN_INFO_OFFSET), \
  280. .scan_type = { \
  281. .sign = 'u', \
  282. .realbits = (bits), \
  283. .storagebits = 32, \
  284. .shift = (_shift), \
  285. }, \
  286. .ext_info = ad5791_ext_info, \
  287. }, \
  288. .channel_offload = { \
  289. .type = IIO_VOLTAGE, \
  290. .output = 1, \
  291. .indexed = 1, \
  292. .address = AD5791_ADDR_DAC0, \
  293. .channel = 0, \
  294. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  295. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  296. BIT(IIO_CHAN_INFO_OFFSET), \
  297. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  298. .scan_type = { \
  299. .sign = 'u', \
  300. .realbits = (bits), \
  301. .storagebits = 32, \
  302. .shift = (_shift), \
  303. }, \
  304. .ext_info = ad5791_ext_info, \
  305. }, \
  306. }
  307. AD5791_DEFINE_CHIP_INFO(ad5760, 16, 4, ad5780_get_lin_comp);
  308. AD5791_DEFINE_CHIP_INFO(ad5780, 18, 2, ad5780_get_lin_comp);
  309. AD5791_DEFINE_CHIP_INFO(ad5781, 18, 2, ad5791_get_lin_comp);
  310. AD5791_DEFINE_CHIP_INFO(ad5790, 20, 0, ad5791_get_lin_comp);
  311. AD5791_DEFINE_CHIP_INFO(ad5791, 20, 0, ad5791_get_lin_comp);
  312. static int ad5791_write_raw(struct iio_dev *indio_dev,
  313. struct iio_chan_spec const *chan,
  314. int val,
  315. int val2,
  316. long mask)
  317. {
  318. struct ad5791_state *st = iio_priv(indio_dev);
  319. switch (mask) {
  320. case IIO_CHAN_INFO_RAW:
  321. val &= GENMASK(chan->scan_type.realbits - 1, 0);
  322. val <<= chan->scan_type.shift;
  323. return ad5791_spi_write(st, chan->address, val);
  324. case IIO_CHAN_INFO_SAMP_FREQ:
  325. if (val < 1)
  326. return -EINVAL;
  327. return ad5791_set_sample_freq(st, val);
  328. default:
  329. return -EINVAL;
  330. }
  331. }
  332. static int ad5791_write_raw_get_fmt(struct iio_dev *indio_dev,
  333. struct iio_chan_spec const *chan,
  334. long mask)
  335. {
  336. switch (mask) {
  337. case IIO_CHAN_INFO_SAMP_FREQ:
  338. return IIO_VAL_INT;
  339. default:
  340. return IIO_VAL_INT_PLUS_MICRO;
  341. }
  342. }
  343. static int ad5791_buffer_preenable(struct iio_dev *indio_dev)
  344. {
  345. struct ad5791_state *st = iio_priv(indio_dev);
  346. struct spi_offload_trigger_config config = {
  347. .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
  348. .periodic = {
  349. .frequency_hz = st->offload_trigger_hz,
  350. },
  351. };
  352. if (st->pwr_down)
  353. return -EINVAL;
  354. return spi_offload_trigger_enable(st->offload, st->offload_trigger,
  355. &config);
  356. }
  357. static int ad5791_buffer_postdisable(struct iio_dev *indio_dev)
  358. {
  359. struct ad5791_state *st = iio_priv(indio_dev);
  360. spi_offload_trigger_disable(st->offload, st->offload_trigger);
  361. return 0;
  362. }
  363. static const struct iio_buffer_setup_ops ad5791_buffer_setup_ops = {
  364. .preenable = &ad5791_buffer_preenable,
  365. .postdisable = &ad5791_buffer_postdisable,
  366. };
  367. static int ad5791_offload_setup(struct iio_dev *indio_dev)
  368. {
  369. struct ad5791_state *st = iio_priv(indio_dev);
  370. struct spi_device *spi = st->spi;
  371. struct dma_chan *tx_dma;
  372. int ret;
  373. st->offload_trigger = devm_spi_offload_trigger_get(&spi->dev,
  374. st->offload, SPI_OFFLOAD_TRIGGER_PERIODIC);
  375. if (IS_ERR(st->offload_trigger))
  376. return dev_err_probe(&spi->dev, PTR_ERR(st->offload_trigger),
  377. "failed to get offload trigger\n");
  378. ret = ad5791_set_sample_freq(st, 1 * MEGA);
  379. if (ret)
  380. return dev_err_probe(&spi->dev, ret,
  381. "failed to init sample rate\n");
  382. tx_dma = devm_spi_offload_tx_stream_request_dma_chan(&spi->dev,
  383. st->offload);
  384. if (IS_ERR(tx_dma))
  385. return dev_err_probe(&spi->dev, PTR_ERR(tx_dma),
  386. "failed to get offload TX DMA\n");
  387. ret = devm_iio_dmaengine_buffer_setup_with_handle(&spi->dev,
  388. indio_dev, tx_dma, IIO_BUFFER_DIRECTION_OUT);
  389. if (ret)
  390. return ret;
  391. st->offload_xfer.len = 4;
  392. st->offload_xfer.bits_per_word = 24;
  393. st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_TX_STREAM;
  394. spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1);
  395. st->offload_msg.offload = st->offload;
  396. return devm_spi_optimize_message(&spi->dev, st->spi, &st->offload_msg);
  397. }
  398. static const struct iio_info ad5791_info = {
  399. .read_raw = &ad5791_read_raw,
  400. .write_raw = &ad5791_write_raw,
  401. .write_raw_get_fmt = &ad5791_write_raw_get_fmt,
  402. };
  403. static const struct spi_offload_config ad5791_offload_config = {
  404. .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
  405. SPI_OFFLOAD_CAP_TX_STREAM_DMA,
  406. };
  407. static int ad5791_probe(struct spi_device *spi)
  408. {
  409. const struct ad5791_platform_data *pdata = dev_get_platdata(&spi->dev);
  410. struct iio_dev *indio_dev;
  411. struct ad5791_state *st;
  412. int ret, pos_voltage_uv = 0, neg_voltage_uv = 0;
  413. bool use_rbuf_gain2;
  414. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  415. if (!indio_dev)
  416. return -ENOMEM;
  417. st = iio_priv(indio_dev);
  418. st->gpio_reset = devm_gpiod_get_optional(&spi->dev, "reset",
  419. GPIOD_OUT_HIGH);
  420. if (IS_ERR(st->gpio_reset))
  421. return PTR_ERR(st->gpio_reset);
  422. st->gpio_clear = devm_gpiod_get_optional(&spi->dev, "clear",
  423. GPIOD_OUT_LOW);
  424. if (IS_ERR(st->gpio_clear))
  425. return PTR_ERR(st->gpio_clear);
  426. st->gpio_ldac = devm_gpiod_get_optional(&spi->dev, "ldac",
  427. GPIOD_OUT_HIGH);
  428. if (IS_ERR(st->gpio_ldac))
  429. return PTR_ERR(st->gpio_ldac);
  430. st->pwr_down = true;
  431. st->spi = spi;
  432. if (pdata)
  433. use_rbuf_gain2 = pdata->use_rbuf_gain2;
  434. else
  435. use_rbuf_gain2 = device_property_read_bool(&spi->dev,
  436. "adi,rbuf-gain2-en");
  437. pos_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vdd");
  438. if (pos_voltage_uv < 0 && pos_voltage_uv != -ENODEV)
  439. return dev_err_probe(&spi->dev, pos_voltage_uv,
  440. "failed to get vdd voltage\n");
  441. neg_voltage_uv = devm_regulator_get_enable_read_voltage(&spi->dev, "vss");
  442. if (neg_voltage_uv < 0 && neg_voltage_uv != -ENODEV)
  443. return dev_err_probe(&spi->dev, neg_voltage_uv,
  444. "failed to get vss voltage\n");
  445. if (neg_voltage_uv >= 0 && pos_voltage_uv >= 0) {
  446. st->vref_mv = (pos_voltage_uv + neg_voltage_uv) / 1000;
  447. st->vref_neg_mv = neg_voltage_uv / 1000;
  448. } else if (pdata) {
  449. st->vref_mv = pdata->vref_pos_mv + pdata->vref_neg_mv;
  450. st->vref_neg_mv = pdata->vref_neg_mv;
  451. } else {
  452. dev_warn(&spi->dev, "reference voltage unspecified\n");
  453. }
  454. if (st->gpio_reset) {
  455. fsleep(20);
  456. gpiod_set_value_cansleep(st->gpio_reset, 0);
  457. } else {
  458. ret = ad5791_spi_write(st, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET);
  459. if (ret)
  460. return dev_err_probe(&spi->dev, ret, "fail to reset\n");
  461. }
  462. st->chip_info = spi_get_device_match_data(spi);
  463. if (!st->chip_info)
  464. return dev_err_probe(&spi->dev, -EINVAL, "no chip info\n");
  465. st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv))
  466. | (use_rbuf_gain2 ? 0 : AD5791_CTRL_RBUF) |
  467. AD5791_CTRL_BIN2SC;
  468. ret = ad5791_spi_write(st, AD5791_ADDR_CTRL, st->ctrl |
  469. AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
  470. if (ret)
  471. return dev_err_probe(&spi->dev, ret, "fail to write ctrl register\n");
  472. indio_dev->info = &ad5791_info;
  473. indio_dev->modes = INDIO_DIRECT_MODE;
  474. indio_dev->channels = &st->chip_info->channel;
  475. indio_dev->num_channels = 1;
  476. indio_dev->name = st->chip_info->name;
  477. st->offload = devm_spi_offload_get(&spi->dev, spi, &ad5791_offload_config);
  478. ret = PTR_ERR_OR_ZERO(st->offload);
  479. if (ret && ret != -ENODEV)
  480. return dev_err_probe(&spi->dev, ret, "failed to get offload\n");
  481. if (ret != -ENODEV) {
  482. indio_dev->channels = &st->chip_info->channel_offload;
  483. indio_dev->setup_ops = &ad5791_buffer_setup_ops;
  484. ret = ad5791_offload_setup(indio_dev);
  485. if (ret)
  486. return dev_err_probe(&spi->dev, ret,
  487. "fail to setup offload\n");
  488. }
  489. return devm_iio_device_register(&spi->dev, indio_dev);
  490. }
  491. static const struct of_device_id ad5791_of_match[] = {
  492. { .compatible = "adi,ad5760", .data = &ad5760_chip_info },
  493. { .compatible = "adi,ad5780", .data = &ad5780_chip_info },
  494. { .compatible = "adi,ad5781", .data = &ad5781_chip_info },
  495. { .compatible = "adi,ad5790", .data = &ad5790_chip_info },
  496. { .compatible = "adi,ad5791", .data = &ad5791_chip_info },
  497. { }
  498. };
  499. MODULE_DEVICE_TABLE(of, ad5791_of_match);
  500. static const struct spi_device_id ad5791_id[] = {
  501. { "ad5760", (kernel_ulong_t)&ad5760_chip_info },
  502. { "ad5780", (kernel_ulong_t)&ad5780_chip_info },
  503. { "ad5781", (kernel_ulong_t)&ad5781_chip_info },
  504. { "ad5790", (kernel_ulong_t)&ad5790_chip_info },
  505. { "ad5791", (kernel_ulong_t)&ad5791_chip_info },
  506. { }
  507. };
  508. MODULE_DEVICE_TABLE(spi, ad5791_id);
  509. static struct spi_driver ad5791_driver = {
  510. .driver = {
  511. .name = "ad5791",
  512. .of_match_table = ad5791_of_match,
  513. },
  514. .probe = ad5791_probe,
  515. .id_table = ad5791_id,
  516. };
  517. module_spi_driver(ad5791_driver);
  518. MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
  519. MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5790/AD5791 DAC");
  520. MODULE_LICENSE("GPL v2");
  521. MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");