kxcjk-1013.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * KXCJK-1013 3-axis accelerometer driver
  4. * Copyright (c) 2014, Intel Corporation.
  5. */
  6. #include <linux/i2c.h>
  7. #include <linux/interrupt.h>
  8. #include <linux/delay.h>
  9. #include <linux/bitops.h>
  10. #include <linux/mod_devicetable.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/string.h>
  14. #include <linux/types.h>
  15. #include <linux/acpi.h>
  16. #include <linux/pm.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/iio/iio.h>
  20. #include <linux/iio/sysfs.h>
  21. #include <linux/iio/buffer.h>
  22. #include <linux/iio/trigger.h>
  23. #include <linux/iio/events.h>
  24. #include <linux/iio/trigger_consumer.h>
  25. #include <linux/iio/triggered_buffer.h>
  26. #include <linux/iio/accel/kxcjk_1013.h>
  27. #define KXTF9_REG_HP_XOUT_L 0x00
  28. #define KXTF9_REG_HP_XOUT_H 0x01
  29. #define KXTF9_REG_HP_YOUT_L 0x02
  30. #define KXTF9_REG_HP_YOUT_H 0x03
  31. #define KXTF9_REG_HP_ZOUT_L 0x04
  32. #define KXTF9_REG_HP_ZOUT_H 0x05
  33. #define KXCJK1013_REG_XOUT_L 0x06
  34. /*
  35. * From low byte X axis register, all the other addresses of Y and Z can be
  36. * obtained by just applying axis offset. The following axis defines are just
  37. * provide clarity, but not used.
  38. */
  39. #define KXCJK1013_REG_XOUT_H 0x07
  40. #define KXCJK1013_REG_YOUT_L 0x08
  41. #define KXCJK1013_REG_YOUT_H 0x09
  42. #define KXCJK1013_REG_ZOUT_L 0x0A
  43. #define KXCJK1013_REG_ZOUT_H 0x0B
  44. #define KXCJK1013_REG_DCST_RESP 0x0C
  45. #define KXCJK1013_REG_WHO_AM_I 0x0F
  46. #define KXTF9_REG_TILT_POS_CUR 0x10
  47. #define KXTF9_REG_TILT_POS_PREV 0x11
  48. #define KXTF9_REG_INT_SRC1 0x15
  49. #define KXTF9_REG_INT_SRC2 0x16
  50. #define KXCJK1013_REG_INT_SRC1 0x16
  51. #define KXCJK1013_REG_INT_SRC2 0x17
  52. #define KXCJK1013_REG_STATUS_REG 0x18
  53. #define KXCJK1013_REG_INT_REL 0x1A
  54. #define KXCJK1013_REG_CTRL1 0x1B
  55. #define KXTF9_REG_CTRL2 0x1C
  56. #define KXTF9_REG_CTRL3 0x1D
  57. #define KXCJK1013_REG_CTRL2 0x1D
  58. #define KXCJK1013_REG_INT_CTRL1 0x1E
  59. #define KXCJK1013_REG_INT_CTRL2 0x1F
  60. #define KXTF9_REG_INT_CTRL3 0x20
  61. #define KXCJK1013_REG_DATA_CTRL 0x21
  62. #define KXTF9_REG_TILT_TIMER 0x28
  63. #define KXCJK1013_REG_WAKE_TIMER 0x29
  64. #define KXTF9_REG_TDT_TIMER 0x2B
  65. #define KXTF9_REG_TDT_THRESH_H 0x2C
  66. #define KXTF9_REG_TDT_THRESH_L 0x2D
  67. #define KXTF9_REG_TDT_TAP_TIMER 0x2E
  68. #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
  69. #define KXTF9_REG_TDT_LATENCY_TIMER 0x30
  70. #define KXTF9_REG_TDT_WINDOW_TIMER 0x31
  71. #define KXCJK1013_REG_SELF_TEST 0x3A
  72. #define KXTF9_REG_WAKE_THRESH 0x5A
  73. #define KXTF9_REG_TILT_ANGLE 0x5C
  74. #define KXTF9_REG_HYST_SET 0x5F
  75. #define KXCJK1013_REG_WAKE_THRES 0x6A
  76. /* Everything up to 0x11 is equal to KXCJK1013/KXTF9 above */
  77. #define KX023_REG_INS1 0x12
  78. #define KX023_REG_INS2 0x13
  79. #define KX023_REG_INS3 0x14
  80. #define KX023_REG_STAT 0x15
  81. #define KX023_REG_INT_REL 0x17
  82. #define KX023_REG_CNTL1 0x18
  83. #define KX023_REG_CNTL2 0x19
  84. #define KX023_REG_CNTL3 0x1A
  85. #define KX023_REG_ODCNTL 0x1B
  86. #define KX023_REG_INC1 0x1C
  87. #define KX023_REG_INC2 0x1D
  88. #define KX023_REG_INC3 0x1E
  89. #define KX023_REG_INC4 0x1F
  90. #define KX023_REG_INC5 0x20
  91. #define KX023_REG_INC6 0x21
  92. #define KX023_REG_TILT_TIMER 0x22
  93. #define KX023_REG_WUFC 0x23
  94. #define KX023_REG_TDTRC 0x24
  95. #define KX023_REG_TDTC 0x25
  96. #define KX023_REG_TTH 0x26
  97. #define KX023_REG_TTL 0x27
  98. #define KX023_REG_FTD 0x28
  99. #define KX023_REG_STD 0x29
  100. #define KX023_REG_TLT 0x2A
  101. #define KX023_REG_TWS 0x2B
  102. #define KX023_REG_ATH 0x30
  103. #define KX023_REG_TILT_ANGLE_LL 0x32
  104. #define KX023_REG_TILT_ANGLE_HL 0x33
  105. #define KX023_REG_HYST_SET 0x34
  106. #define KX023_REG_LP_CNTL 0x35
  107. #define KX023_REG_BUF_CNTL1 0x3A
  108. #define KX023_REG_BUF_CNTL2 0x3B
  109. #define KX023_REG_BUF_STATUS_1 0x3C
  110. #define KX023_REG_BUF_STATUS_2 0x3D
  111. #define KX023_REG_BUF_CLEAR 0x3E
  112. #define KX023_REG_BUF_READ 0x3F
  113. #define KX023_REG_SELF_TEST 0x60
  114. #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
  115. #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
  116. #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
  117. #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
  118. #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
  119. #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
  120. #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
  121. #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
  122. #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
  123. #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
  124. #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
  125. #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
  126. #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
  127. #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
  128. #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
  129. #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
  130. #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
  131. #define KXCJK1013_MAX_STARTUP_TIME_US 100000
  132. #define KXCJK1013_SLEEP_DELAY_MS 2000
  133. #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
  134. #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
  135. #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
  136. #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
  137. #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
  138. #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
  139. #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
  140. /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
  141. #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
  142. #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
  143. #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
  144. #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
  145. #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
  146. #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
  147. /* KX023 interrupt routing to INT1. INT2 can be configured with INC6 */
  148. #define KX023_REG_INC4_BFI1 BIT(6)
  149. #define KX023_REG_INC4_WMI1 BIT(5)
  150. #define KX023_REG_INC4_DRDY1 BIT(4)
  151. #define KX023_REG_INC4_TDTI1 BIT(2)
  152. #define KX023_REG_INC4_WUFI1 BIT(1)
  153. #define KX023_REG_INC4_TPI1 BIT(0)
  154. #define KXCJK1013_DEFAULT_WAKE_THRES 1
  155. /* Refer to section 4 of the specification */
  156. struct kx_odr_start_up_time {
  157. int odr_bits;
  158. int usec;
  159. };
  160. /* KXCJK-1013 */
  161. static const struct kx_odr_start_up_time kxcjk1013_odr_start_up_times[] = {
  162. { 0x08, 100000 },
  163. { 0x09, 100000 },
  164. { 0x0A, 100000 },
  165. { 0x0B, 100000 },
  166. { 0x00, 80000 },
  167. { 0x01, 41000 },
  168. { 0x02, 21000 },
  169. { 0x03, 11000 },
  170. { 0x04, 6400 },
  171. { 0x05, 3900 },
  172. { 0x06, 2700 },
  173. { 0x07, 2100 },
  174. { }
  175. };
  176. /* KXCTJ2-1009 */
  177. static const struct kx_odr_start_up_time kxtj21009_odr_start_up_times[] = {
  178. { 0x08, 1240000 },
  179. { 0x09, 621000 },
  180. { 0x0A, 309000 },
  181. { 0x0B, 151000 },
  182. { 0x00, 80000 },
  183. { 0x01, 41000 },
  184. { 0x02, 21000 },
  185. { 0x03, 11000 },
  186. { 0x04, 6000 },
  187. { 0x05, 4000 },
  188. { 0x06, 3000 },
  189. { 0x07, 2000 },
  190. { }
  191. };
  192. /* KXTF9 */
  193. static const struct kx_odr_start_up_time kxtf9_odr_start_up_times[] = {
  194. { 0x01, 81000 },
  195. { 0x02, 41000 },
  196. { 0x03, 21000 },
  197. { 0x04, 11000 },
  198. { 0x05, 5100 },
  199. { 0x06, 2700 },
  200. { }
  201. };
  202. /* KX023-1025 */
  203. static const struct kx_odr_start_up_time kx0231025_odr_start_up_times[] = {
  204. /* First 4 are not in datasheet, taken from KXCTJ2-1009 */
  205. { 0x08, 1240000 },
  206. { 0x09, 621000 },
  207. { 0x0A, 309000 },
  208. { 0x0B, 151000 },
  209. { 0x00, 81000 },
  210. { 0x01, 40000 },
  211. { 0x02, 22000 },
  212. { 0x03, 12000 },
  213. { 0x04, 7000 },
  214. { 0x05, 4400 },
  215. { 0x06, 3000 },
  216. { 0x07, 3000 },
  217. { }
  218. };
  219. enum kx_acpi_type {
  220. ACPI_GENERIC,
  221. ACPI_SMO8500,
  222. ACPI_KIOX010A,
  223. };
  224. struct kx_chipset_regs {
  225. u8 int_src1;
  226. u8 int_src2;
  227. u8 int_rel;
  228. u8 ctrl1;
  229. u8 wuf_ctrl;
  230. u8 int_ctrl1;
  231. u8 data_ctrl;
  232. u8 wake_timer;
  233. u8 wake_thres;
  234. };
  235. static const struct kx_chipset_regs kxcjk1013_regs = {
  236. .int_src1 = KXCJK1013_REG_INT_SRC1,
  237. .int_src2 = KXCJK1013_REG_INT_SRC2,
  238. .int_rel = KXCJK1013_REG_INT_REL,
  239. .ctrl1 = KXCJK1013_REG_CTRL1,
  240. .wuf_ctrl = KXCJK1013_REG_CTRL2,
  241. .int_ctrl1 = KXCJK1013_REG_INT_CTRL1,
  242. .data_ctrl = KXCJK1013_REG_DATA_CTRL,
  243. .wake_timer = KXCJK1013_REG_WAKE_TIMER,
  244. .wake_thres = KXCJK1013_REG_WAKE_THRES,
  245. };
  246. static const struct kx_chipset_regs kxtf9_regs = {
  247. /* .int_src1 was moved to INT_SRC2 on KXTF9 */
  248. .int_src1 = KXTF9_REG_INT_SRC2,
  249. /* .int_src2 is not available */
  250. .int_rel = KXCJK1013_REG_INT_REL,
  251. .ctrl1 = KXCJK1013_REG_CTRL1,
  252. .wuf_ctrl = KXTF9_REG_CTRL3,
  253. .int_ctrl1 = KXCJK1013_REG_INT_CTRL1,
  254. .data_ctrl = KXCJK1013_REG_DATA_CTRL,
  255. .wake_timer = KXCJK1013_REG_WAKE_TIMER,
  256. .wake_thres = KXTF9_REG_WAKE_THRESH,
  257. };
  258. /* The registers have totally different names but the bits are compatible */
  259. static const struct kx_chipset_regs kx0231025_regs = {
  260. .int_src1 = KX023_REG_INS2,
  261. .int_src2 = KX023_REG_INS3,
  262. .int_rel = KX023_REG_INT_REL,
  263. .ctrl1 = KX023_REG_CNTL1,
  264. .wuf_ctrl = KX023_REG_CNTL3,
  265. .int_ctrl1 = KX023_REG_INC1,
  266. .data_ctrl = KX023_REG_ODCNTL,
  267. .wake_timer = KX023_REG_WUFC,
  268. .wake_thres = KX023_REG_ATH,
  269. };
  270. struct kx_chipset_info {
  271. const struct kx_chipset_regs *regs;
  272. const struct kx_odr_start_up_time *times;
  273. enum kx_acpi_type acpi_type;
  274. };
  275. static const struct kx_chipset_info kxcjk1013_info = {
  276. .regs = &kxcjk1013_regs,
  277. .times = pm_ptr(kxcjk1013_odr_start_up_times),
  278. };
  279. static const struct kx_chipset_info kxcj91008_info = {
  280. .regs = &kxcjk1013_regs,
  281. .times = pm_ptr(kxcjk1013_odr_start_up_times),
  282. };
  283. static const struct kx_chipset_info kxcj91008_kiox010a_info = {
  284. .regs = &kxcjk1013_regs,
  285. .times = pm_ptr(kxcjk1013_odr_start_up_times),
  286. .acpi_type = ACPI_KIOX010A,
  287. };
  288. static const struct kx_chipset_info kxcj91008_kiox020a_info = {
  289. .regs = &kxcjk1013_regs,
  290. .times = pm_ptr(kxcjk1013_odr_start_up_times),
  291. .acpi_type = ACPI_GENERIC,
  292. };
  293. static const struct kx_chipset_info kxcj91008_smo8500_info = {
  294. .regs = &kxcjk1013_regs,
  295. .times = pm_ptr(kxcjk1013_odr_start_up_times),
  296. .acpi_type = ACPI_SMO8500,
  297. };
  298. static const struct kx_chipset_info kxtj21009_info = {
  299. .regs = &kxcjk1013_regs,
  300. .times = pm_ptr(kxtj21009_odr_start_up_times),
  301. };
  302. static const struct kx_chipset_info kxtf9_info = {
  303. .regs = &kxtf9_regs,
  304. .times = pm_ptr(kxtf9_odr_start_up_times),
  305. };
  306. static const struct kx_chipset_info kx0231025_info = {
  307. .regs = &kx0231025_regs,
  308. .times = pm_ptr(kx0231025_odr_start_up_times),
  309. };
  310. enum kxcjk1013_axis {
  311. AXIS_X,
  312. AXIS_Y,
  313. AXIS_Z,
  314. AXIS_MAX
  315. };
  316. struct kxcjk1013_data {
  317. struct i2c_client *client;
  318. struct iio_trigger *dready_trig;
  319. struct iio_trigger *motion_trig;
  320. struct iio_mount_matrix orientation;
  321. struct mutex mutex;
  322. /* Ensure timestamp naturally aligned */
  323. struct {
  324. s16 chans[AXIS_MAX];
  325. aligned_s64 timestamp;
  326. } scan;
  327. u8 odr_bits;
  328. u8 range;
  329. int wake_thres;
  330. int wake_dur;
  331. bool active_high_intr;
  332. bool dready_trigger_on;
  333. int ev_enable_state;
  334. bool motion_trigger_on;
  335. int64_t timestamp;
  336. const struct kx_chipset_info *info;
  337. };
  338. enum kxcjk1013_mode {
  339. STANDBY,
  340. OPERATION,
  341. };
  342. enum kxcjk1013_range {
  343. KXCJK1013_RANGE_2G,
  344. KXCJK1013_RANGE_4G,
  345. KXCJK1013_RANGE_8G,
  346. };
  347. struct kx_odr_map {
  348. int val;
  349. int val2;
  350. int odr_bits;
  351. int wuf_bits;
  352. };
  353. static const struct kx_odr_map samp_freq_table[] = {
  354. { 0, 781000, 0x08, 0x00 },
  355. { 1, 563000, 0x09, 0x01 },
  356. { 3, 125000, 0x0A, 0x02 },
  357. { 6, 250000, 0x0B, 0x03 },
  358. { 12, 500000, 0x00, 0x04 },
  359. { 25, 0, 0x01, 0x05 },
  360. { 50, 0, 0x02, 0x06 },
  361. { 100, 0, 0x03, 0x06 },
  362. { 200, 0, 0x04, 0x06 },
  363. { 400, 0, 0x05, 0x06 },
  364. { 800, 0, 0x06, 0x06 },
  365. { 1600, 0, 0x07, 0x06 },
  366. };
  367. static const char *const kxcjk1013_samp_freq_avail =
  368. "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
  369. static const struct kx_odr_map kxtf9_samp_freq_table[] = {
  370. { 25, 0, 0x01, 0x00 },
  371. { 50, 0, 0x02, 0x01 },
  372. { 100, 0, 0x03, 0x01 },
  373. { 200, 0, 0x04, 0x01 },
  374. { 400, 0, 0x05, 0x01 },
  375. { 800, 0, 0x06, 0x01 },
  376. };
  377. static const char *const kxtf9_samp_freq_avail =
  378. "25 50 100 200 400 800";
  379. static const struct {
  380. u16 scale;
  381. u8 gsel_0;
  382. u8 gsel_1;
  383. } KXCJK1013_scale_table[] = { {9582, 0, 0},
  384. {19163, 1, 0},
  385. {38326, 0, 1} };
  386. #ifdef CONFIG_ACPI
  387. enum kiox010a_fn_index {
  388. KIOX010A_SET_LAPTOP_MODE = 1,
  389. KIOX010A_SET_TABLET_MODE = 2,
  390. };
  391. static int kiox010a_dsm(struct device *dev, int fn_index)
  392. {
  393. acpi_handle handle = ACPI_HANDLE(dev);
  394. guid_t kiox010a_dsm_guid;
  395. union acpi_object *obj;
  396. if (!handle)
  397. return -ENODEV;
  398. guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid);
  399. obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL);
  400. if (!obj)
  401. return -EIO;
  402. ACPI_FREE(obj);
  403. return 0;
  404. }
  405. #endif
  406. static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
  407. enum kxcjk1013_mode mode)
  408. {
  409. const struct kx_chipset_regs *regs = data->info->regs;
  410. int ret;
  411. ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1);
  412. if (ret < 0) {
  413. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  414. return ret;
  415. }
  416. if (mode == STANDBY)
  417. ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
  418. else
  419. ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
  420. ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret);
  421. if (ret < 0) {
  422. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  423. return ret;
  424. }
  425. return 0;
  426. }
  427. static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
  428. enum kxcjk1013_mode *mode)
  429. {
  430. const struct kx_chipset_regs *regs = data->info->regs;
  431. int ret;
  432. ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1);
  433. if (ret < 0) {
  434. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  435. return ret;
  436. }
  437. if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
  438. *mode = OPERATION;
  439. else
  440. *mode = STANDBY;
  441. return 0;
  442. }
  443. static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
  444. {
  445. const struct kx_chipset_regs *regs = data->info->regs;
  446. int ret;
  447. ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1);
  448. if (ret < 0) {
  449. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  450. return ret;
  451. }
  452. ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
  453. KXCJK1013_REG_CTRL1_BIT_GSEL1);
  454. ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
  455. ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
  456. ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret);
  457. if (ret < 0) {
  458. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  459. return ret;
  460. }
  461. data->range = range_index;
  462. return 0;
  463. }
  464. static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
  465. {
  466. const struct kx_chipset_regs *regs = data->info->regs;
  467. int ret;
  468. #ifdef CONFIG_ACPI
  469. if (data->info->acpi_type == ACPI_KIOX010A) {
  470. /* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */
  471. kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);
  472. }
  473. #endif
  474. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
  475. if (ret < 0) {
  476. dev_err(&data->client->dev, "Error reading who_am_i\n");
  477. return ret;
  478. }
  479. dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
  480. ret = kxcjk1013_set_mode(data, STANDBY);
  481. if (ret < 0)
  482. return ret;
  483. ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1);
  484. if (ret < 0) {
  485. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  486. return ret;
  487. }
  488. /* Set 12 bit mode */
  489. ret |= KXCJK1013_REG_CTRL1_BIT_RES;
  490. ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret);
  491. if (ret < 0) {
  492. dev_err(&data->client->dev, "Error reading reg_ctrl\n");
  493. return ret;
  494. }
  495. /* Setting range to 4G */
  496. ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
  497. if (ret < 0)
  498. return ret;
  499. ret = i2c_smbus_read_byte_data(data->client, regs->data_ctrl);
  500. if (ret < 0) {
  501. dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
  502. return ret;
  503. }
  504. data->odr_bits = ret;
  505. /* Set up INT polarity */
  506. ret = i2c_smbus_read_byte_data(data->client, regs->int_ctrl1);
  507. if (ret < 0) {
  508. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  509. return ret;
  510. }
  511. if (data->active_high_intr)
  512. ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;
  513. else
  514. ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;
  515. ret = i2c_smbus_write_byte_data(data->client, regs->int_ctrl1, ret);
  516. if (ret < 0) {
  517. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  518. return ret;
  519. }
  520. /* On KX023, route all used interrupts to INT1 for now */
  521. if (data->info == &kx0231025_info && data->client->irq > 0) {
  522. ret = i2c_smbus_write_byte_data(data->client, KX023_REG_INC4,
  523. KX023_REG_INC4_DRDY1 |
  524. KX023_REG_INC4_WUFI1);
  525. if (ret < 0) {
  526. dev_err(&data->client->dev, "Error writing reg_inc4\n");
  527. return ret;
  528. }
  529. }
  530. ret = kxcjk1013_set_mode(data, OPERATION);
  531. if (ret < 0)
  532. return ret;
  533. data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
  534. return 0;
  535. }
  536. static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
  537. {
  538. const struct kx_odr_start_up_time *times;
  539. for (times = data->info->times; times->usec; times++) {
  540. if (times->odr_bits == data->odr_bits)
  541. return times->usec;
  542. }
  543. return KXCJK1013_MAX_STARTUP_TIME_US;
  544. }
  545. static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
  546. {
  547. #ifdef CONFIG_PM
  548. int ret;
  549. if (on)
  550. ret = pm_runtime_resume_and_get(&data->client->dev);
  551. else
  552. ret = pm_runtime_put_autosuspend(&data->client->dev);
  553. if (ret < 0) {
  554. dev_err(&data->client->dev,
  555. "Failed: %s for %d\n", __func__, on);
  556. return ret;
  557. }
  558. #endif
  559. return 0;
  560. }
  561. static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
  562. {
  563. const struct kx_chipset_regs *regs = data->info->regs;
  564. int ret;
  565. ret = i2c_smbus_write_byte_data(data->client, regs->wake_timer, data->wake_dur);
  566. if (ret < 0) {
  567. dev_err(&data->client->dev,
  568. "Error writing reg_wake_timer\n");
  569. return ret;
  570. }
  571. ret = i2c_smbus_write_byte_data(data->client, regs->wake_thres, data->wake_thres);
  572. if (ret < 0) {
  573. dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
  574. return ret;
  575. }
  576. return 0;
  577. }
  578. static int kxcjk1013_setup_interrupt(struct kxcjk1013_data *data,
  579. bool status, bool is_new_data)
  580. {
  581. const struct kx_chipset_regs *regs = data->info->regs;
  582. int ret;
  583. enum kxcjk1013_mode store_mode;
  584. ret = kxcjk1013_get_mode(data, &store_mode);
  585. if (ret < 0)
  586. return ret;
  587. /* This is requirement by spec to change state to STANDBY */
  588. ret = kxcjk1013_set_mode(data, STANDBY);
  589. if (ret < 0)
  590. return ret;
  591. if (is_new_data == true) {
  592. ret = kxcjk1013_chip_update_thresholds(data);
  593. if (ret < 0)
  594. return ret;
  595. }
  596. ret = i2c_smbus_read_byte_data(data->client, regs->int_ctrl1);
  597. if (ret < 0) {
  598. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  599. return ret;
  600. }
  601. if (status)
  602. ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  603. else
  604. ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
  605. ret = i2c_smbus_write_byte_data(data->client, regs->int_ctrl1, ret);
  606. if (ret < 0) {
  607. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  608. return ret;
  609. }
  610. ret = i2c_smbus_read_byte_data(data->client, regs->ctrl1);
  611. if (ret < 0) {
  612. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  613. return ret;
  614. }
  615. if (is_new_data) {
  616. if (status)
  617. ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
  618. else
  619. ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
  620. } else {
  621. if (status)
  622. ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
  623. else
  624. ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
  625. }
  626. ret = i2c_smbus_write_byte_data(data->client, regs->ctrl1, ret);
  627. if (ret < 0) {
  628. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  629. return ret;
  630. }
  631. if (store_mode == OPERATION) {
  632. ret = kxcjk1013_set_mode(data, OPERATION);
  633. if (ret < 0)
  634. return ret;
  635. }
  636. return 0;
  637. }
  638. static const struct kx_odr_map *kxcjk1013_find_odr_value(
  639. const struct kx_odr_map *map, size_t map_size, int val, int val2)
  640. {
  641. int i;
  642. for (i = 0; i < map_size; ++i) {
  643. if (map[i].val == val && map[i].val2 == val2)
  644. return &map[i];
  645. }
  646. return ERR_PTR(-EINVAL);
  647. }
  648. static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map,
  649. size_t map_size, int odr_bits,
  650. int *val, int *val2)
  651. {
  652. int i;
  653. for (i = 0; i < map_size; ++i) {
  654. if (map[i].odr_bits == odr_bits) {
  655. *val = map[i].val;
  656. *val2 = map[i].val2;
  657. return IIO_VAL_INT_PLUS_MICRO;
  658. }
  659. }
  660. return -EINVAL;
  661. }
  662. static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
  663. {
  664. const struct kx_chipset_regs *regs = data->info->regs;
  665. int ret;
  666. enum kxcjk1013_mode store_mode;
  667. const struct kx_odr_map *odr_setting;
  668. ret = kxcjk1013_get_mode(data, &store_mode);
  669. if (ret < 0)
  670. return ret;
  671. if (data->info == &kxtf9_info)
  672. odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
  673. ARRAY_SIZE(kxtf9_samp_freq_table),
  674. val, val2);
  675. else
  676. odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
  677. ARRAY_SIZE(samp_freq_table),
  678. val, val2);
  679. if (IS_ERR(odr_setting))
  680. return PTR_ERR(odr_setting);
  681. /* To change ODR, the chip must be set to STANDBY as per spec */
  682. ret = kxcjk1013_set_mode(data, STANDBY);
  683. if (ret < 0)
  684. return ret;
  685. ret = i2c_smbus_write_byte_data(data->client, regs->data_ctrl,
  686. odr_setting->odr_bits);
  687. if (ret < 0) {
  688. dev_err(&data->client->dev, "Error writing data_ctrl\n");
  689. return ret;
  690. }
  691. data->odr_bits = odr_setting->odr_bits;
  692. ret = i2c_smbus_write_byte_data(data->client, regs->wuf_ctrl,
  693. odr_setting->wuf_bits);
  694. if (ret < 0) {
  695. dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
  696. return ret;
  697. }
  698. if (store_mode == OPERATION) {
  699. ret = kxcjk1013_set_mode(data, OPERATION);
  700. if (ret < 0)
  701. return ret;
  702. }
  703. return 0;
  704. }
  705. static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
  706. {
  707. if (data->info == &kxtf9_info)
  708. return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
  709. ARRAY_SIZE(kxtf9_samp_freq_table),
  710. data->odr_bits, val, val2);
  711. else
  712. return kxcjk1013_convert_odr_value(samp_freq_table,
  713. ARRAY_SIZE(samp_freq_table),
  714. data->odr_bits, val, val2);
  715. }
  716. static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
  717. {
  718. u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
  719. int ret;
  720. ret = i2c_smbus_read_word_data(data->client, reg);
  721. if (ret < 0) {
  722. dev_err(&data->client->dev,
  723. "failed to read accel_%c registers\n", 'x' + axis);
  724. return ret;
  725. }
  726. return ret;
  727. }
  728. static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
  729. {
  730. int ret, i;
  731. enum kxcjk1013_mode store_mode;
  732. for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
  733. if (KXCJK1013_scale_table[i].scale == val) {
  734. ret = kxcjk1013_get_mode(data, &store_mode);
  735. if (ret < 0)
  736. return ret;
  737. ret = kxcjk1013_set_mode(data, STANDBY);
  738. if (ret < 0)
  739. return ret;
  740. ret = kxcjk1013_set_range(data, i);
  741. if (ret < 0)
  742. return ret;
  743. if (store_mode == OPERATION) {
  744. ret = kxcjk1013_set_mode(data, OPERATION);
  745. if (ret)
  746. return ret;
  747. }
  748. return 0;
  749. }
  750. }
  751. return -EINVAL;
  752. }
  753. static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
  754. struct iio_chan_spec const *chan, int *val,
  755. int *val2, long mask)
  756. {
  757. struct kxcjk1013_data *data = iio_priv(indio_dev);
  758. int ret;
  759. switch (mask) {
  760. case IIO_CHAN_INFO_RAW:
  761. mutex_lock(&data->mutex);
  762. if (iio_buffer_enabled(indio_dev))
  763. ret = -EBUSY;
  764. else {
  765. ret = kxcjk1013_set_power_state(data, true);
  766. if (ret < 0) {
  767. mutex_unlock(&data->mutex);
  768. return ret;
  769. }
  770. ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
  771. if (ret < 0) {
  772. kxcjk1013_set_power_state(data, false);
  773. mutex_unlock(&data->mutex);
  774. return ret;
  775. }
  776. *val = sign_extend32(ret >> chan->scan_type.shift,
  777. chan->scan_type.realbits - 1);
  778. ret = kxcjk1013_set_power_state(data, false);
  779. }
  780. mutex_unlock(&data->mutex);
  781. if (ret < 0)
  782. return ret;
  783. return IIO_VAL_INT;
  784. case IIO_CHAN_INFO_SCALE:
  785. *val = 0;
  786. *val2 = KXCJK1013_scale_table[data->range].scale;
  787. return IIO_VAL_INT_PLUS_MICRO;
  788. case IIO_CHAN_INFO_SAMP_FREQ:
  789. mutex_lock(&data->mutex);
  790. ret = kxcjk1013_get_odr(data, val, val2);
  791. mutex_unlock(&data->mutex);
  792. return ret;
  793. default:
  794. return -EINVAL;
  795. }
  796. }
  797. static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
  798. struct iio_chan_spec const *chan, int val,
  799. int val2, long mask)
  800. {
  801. struct kxcjk1013_data *data = iio_priv(indio_dev);
  802. int ret;
  803. switch (mask) {
  804. case IIO_CHAN_INFO_SAMP_FREQ:
  805. mutex_lock(&data->mutex);
  806. ret = kxcjk1013_set_odr(data, val, val2);
  807. mutex_unlock(&data->mutex);
  808. break;
  809. case IIO_CHAN_INFO_SCALE:
  810. if (val)
  811. return -EINVAL;
  812. mutex_lock(&data->mutex);
  813. ret = kxcjk1013_set_scale(data, val2);
  814. mutex_unlock(&data->mutex);
  815. break;
  816. default:
  817. ret = -EINVAL;
  818. }
  819. return ret;
  820. }
  821. static int kxcjk1013_read_event(struct iio_dev *indio_dev,
  822. const struct iio_chan_spec *chan,
  823. enum iio_event_type type,
  824. enum iio_event_direction dir,
  825. enum iio_event_info info,
  826. int *val, int *val2)
  827. {
  828. struct kxcjk1013_data *data = iio_priv(indio_dev);
  829. *val2 = 0;
  830. switch (info) {
  831. case IIO_EV_INFO_VALUE:
  832. *val = data->wake_thres;
  833. break;
  834. case IIO_EV_INFO_PERIOD:
  835. *val = data->wake_dur;
  836. break;
  837. default:
  838. return -EINVAL;
  839. }
  840. return IIO_VAL_INT;
  841. }
  842. static int kxcjk1013_write_event(struct iio_dev *indio_dev,
  843. const struct iio_chan_spec *chan,
  844. enum iio_event_type type,
  845. enum iio_event_direction dir,
  846. enum iio_event_info info,
  847. int val, int val2)
  848. {
  849. struct kxcjk1013_data *data = iio_priv(indio_dev);
  850. if (data->ev_enable_state)
  851. return -EBUSY;
  852. switch (info) {
  853. case IIO_EV_INFO_VALUE:
  854. data->wake_thres = val;
  855. break;
  856. case IIO_EV_INFO_PERIOD:
  857. data->wake_dur = val;
  858. break;
  859. default:
  860. return -EINVAL;
  861. }
  862. return 0;
  863. }
  864. static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
  865. const struct iio_chan_spec *chan,
  866. enum iio_event_type type,
  867. enum iio_event_direction dir)
  868. {
  869. struct kxcjk1013_data *data = iio_priv(indio_dev);
  870. return data->ev_enable_state;
  871. }
  872. static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
  873. const struct iio_chan_spec *chan,
  874. enum iio_event_type type,
  875. enum iio_event_direction dir,
  876. bool state)
  877. {
  878. struct kxcjk1013_data *data = iio_priv(indio_dev);
  879. int ret;
  880. if (state && data->ev_enable_state)
  881. return 0;
  882. mutex_lock(&data->mutex);
  883. if (!state && data->motion_trigger_on) {
  884. data->ev_enable_state = 0;
  885. mutex_unlock(&data->mutex);
  886. return 0;
  887. }
  888. /*
  889. * We will expect the enable and disable to do operation in
  890. * reverse order. This will happen here anyway as our
  891. * resume operation uses sync mode runtime pm calls, the
  892. * suspend operation will be delayed by autosuspend delay
  893. * So the disable operation will still happen in reverse of
  894. * enable operation. When runtime pm is disabled the mode
  895. * is always on so sequence doesn't matter
  896. */
  897. ret = kxcjk1013_set_power_state(data, state);
  898. if (ret < 0) {
  899. mutex_unlock(&data->mutex);
  900. return ret;
  901. }
  902. ret = kxcjk1013_setup_interrupt(data, state, false);
  903. if (ret < 0) {
  904. kxcjk1013_set_power_state(data, false);
  905. data->ev_enable_state = 0;
  906. mutex_unlock(&data->mutex);
  907. return ret;
  908. }
  909. data->ev_enable_state = state;
  910. mutex_unlock(&data->mutex);
  911. return 0;
  912. }
  913. static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
  914. {
  915. struct kxcjk1013_data *data = iio_priv(indio_dev);
  916. return kxcjk1013_set_power_state(data, true);
  917. }
  918. static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
  919. {
  920. struct kxcjk1013_data *data = iio_priv(indio_dev);
  921. return kxcjk1013_set_power_state(data, false);
  922. }
  923. static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
  924. struct device_attribute *attr,
  925. char *buf)
  926. {
  927. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  928. struct kxcjk1013_data *data = iio_priv(indio_dev);
  929. const char *str;
  930. if (data->info == &kxtf9_info)
  931. str = kxtf9_samp_freq_avail;
  932. else
  933. str = kxcjk1013_samp_freq_avail;
  934. return sprintf(buf, "%s\n", str);
  935. }
  936. static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
  937. kxcjk1013_get_samp_freq_avail, NULL, 0);
  938. static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
  939. static struct attribute *kxcjk1013_attributes[] = {
  940. &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr,
  941. &iio_const_attr_in_accel_scale_available.dev_attr.attr,
  942. NULL,
  943. };
  944. static const struct attribute_group kxcjk1013_attrs_group = {
  945. .attrs = kxcjk1013_attributes,
  946. };
  947. static const struct iio_event_spec kxcjk1013_event = {
  948. .type = IIO_EV_TYPE_THRESH,
  949. .dir = IIO_EV_DIR_EITHER,
  950. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  951. BIT(IIO_EV_INFO_ENABLE) |
  952. BIT(IIO_EV_INFO_PERIOD)
  953. };
  954. static const struct iio_mount_matrix *
  955. kxcjk1013_get_mount_matrix(const struct iio_dev *indio_dev,
  956. const struct iio_chan_spec *chan)
  957. {
  958. struct kxcjk1013_data *data = iio_priv(indio_dev);
  959. return &data->orientation;
  960. }
  961. static const struct iio_chan_spec_ext_info kxcjk1013_ext_info[] = {
  962. IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxcjk1013_get_mount_matrix),
  963. { }
  964. };
  965. #define KXCJK1013_CHANNEL(_axis) { \
  966. .type = IIO_ACCEL, \
  967. .modified = 1, \
  968. .channel2 = IIO_MOD_##_axis, \
  969. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  970. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  971. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  972. .scan_index = AXIS_##_axis, \
  973. .scan_type = { \
  974. .sign = 's', \
  975. .realbits = 12, \
  976. .storagebits = 16, \
  977. .shift = 4, \
  978. .endianness = IIO_LE, \
  979. }, \
  980. .event_spec = &kxcjk1013_event, \
  981. .ext_info = kxcjk1013_ext_info, \
  982. .num_event_specs = 1 \
  983. }
  984. static const struct iio_chan_spec kxcjk1013_channels[] = {
  985. KXCJK1013_CHANNEL(X),
  986. KXCJK1013_CHANNEL(Y),
  987. KXCJK1013_CHANNEL(Z),
  988. IIO_CHAN_SOFT_TIMESTAMP(3),
  989. };
  990. static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
  991. .preenable = kxcjk1013_buffer_preenable,
  992. .postdisable = kxcjk1013_buffer_postdisable,
  993. };
  994. static const struct iio_info kxcjk1013_iio_info = {
  995. .attrs = &kxcjk1013_attrs_group,
  996. .read_raw = kxcjk1013_read_raw,
  997. .write_raw = kxcjk1013_write_raw,
  998. .read_event_value = kxcjk1013_read_event,
  999. .write_event_value = kxcjk1013_write_event,
  1000. .write_event_config = kxcjk1013_write_event_config,
  1001. .read_event_config = kxcjk1013_read_event_config,
  1002. };
  1003. static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0};
  1004. static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
  1005. {
  1006. struct iio_poll_func *pf = p;
  1007. struct iio_dev *indio_dev = pf->indio_dev;
  1008. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1009. int ret;
  1010. mutex_lock(&data->mutex);
  1011. ret = i2c_smbus_read_i2c_block_data_or_emulated(data->client,
  1012. KXCJK1013_REG_XOUT_L,
  1013. AXIS_MAX * 2,
  1014. (u8 *)data->scan.chans);
  1015. mutex_unlock(&data->mutex);
  1016. if (ret < 0)
  1017. goto err;
  1018. iio_push_to_buffers_with_ts(indio_dev, &data->scan, sizeof(data->scan),
  1019. data->timestamp);
  1020. err:
  1021. iio_trigger_notify_done(indio_dev->trig);
  1022. return IRQ_HANDLED;
  1023. }
  1024. static void kxcjk1013_trig_reen(struct iio_trigger *trig)
  1025. {
  1026. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  1027. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1028. const struct kx_chipset_regs *regs = data->info->regs;
  1029. int ret;
  1030. ret = i2c_smbus_read_byte_data(data->client, regs->int_rel);
  1031. if (ret < 0)
  1032. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  1033. }
  1034. static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
  1035. bool state)
  1036. {
  1037. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  1038. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1039. int ret;
  1040. mutex_lock(&data->mutex);
  1041. if (!state && data->ev_enable_state && data->motion_trigger_on) {
  1042. data->motion_trigger_on = false;
  1043. mutex_unlock(&data->mutex);
  1044. return 0;
  1045. }
  1046. ret = kxcjk1013_set_power_state(data, state);
  1047. if (ret < 0) {
  1048. mutex_unlock(&data->mutex);
  1049. return ret;
  1050. }
  1051. ret = kxcjk1013_setup_interrupt(data, state, data->motion_trig != trig);
  1052. if (ret < 0) {
  1053. kxcjk1013_set_power_state(data, false);
  1054. mutex_unlock(&data->mutex);
  1055. return ret;
  1056. }
  1057. if (data->motion_trig == trig)
  1058. data->motion_trigger_on = state;
  1059. else
  1060. data->dready_trigger_on = state;
  1061. mutex_unlock(&data->mutex);
  1062. return 0;
  1063. }
  1064. static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
  1065. .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
  1066. .reenable = kxcjk1013_trig_reen,
  1067. };
  1068. static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev)
  1069. {
  1070. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1071. const struct kx_chipset_regs *regs = data->info->regs;
  1072. int ret = i2c_smbus_read_byte_data(data->client, regs->int_src2);
  1073. if (ret < 0) {
  1074. dev_err(&data->client->dev, "Error reading reg_int_src2\n");
  1075. return;
  1076. }
  1077. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
  1078. iio_push_event(indio_dev,
  1079. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1080. 0,
  1081. IIO_MOD_X,
  1082. IIO_EV_TYPE_THRESH,
  1083. IIO_EV_DIR_FALLING),
  1084. data->timestamp);
  1085. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
  1086. iio_push_event(indio_dev,
  1087. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1088. 0,
  1089. IIO_MOD_X,
  1090. IIO_EV_TYPE_THRESH,
  1091. IIO_EV_DIR_RISING),
  1092. data->timestamp);
  1093. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
  1094. iio_push_event(indio_dev,
  1095. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1096. 0,
  1097. IIO_MOD_Y,
  1098. IIO_EV_TYPE_THRESH,
  1099. IIO_EV_DIR_FALLING),
  1100. data->timestamp);
  1101. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
  1102. iio_push_event(indio_dev,
  1103. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1104. 0,
  1105. IIO_MOD_Y,
  1106. IIO_EV_TYPE_THRESH,
  1107. IIO_EV_DIR_RISING),
  1108. data->timestamp);
  1109. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
  1110. iio_push_event(indio_dev,
  1111. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1112. 0,
  1113. IIO_MOD_Z,
  1114. IIO_EV_TYPE_THRESH,
  1115. IIO_EV_DIR_FALLING),
  1116. data->timestamp);
  1117. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
  1118. iio_push_event(indio_dev,
  1119. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1120. 0,
  1121. IIO_MOD_Z,
  1122. IIO_EV_TYPE_THRESH,
  1123. IIO_EV_DIR_RISING),
  1124. data->timestamp);
  1125. }
  1126. static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
  1127. {
  1128. struct iio_dev *indio_dev = private;
  1129. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1130. const struct kx_chipset_regs *regs = data->info->regs;
  1131. int ret;
  1132. ret = i2c_smbus_read_byte_data(data->client, regs->int_src1);
  1133. if (ret < 0) {
  1134. dev_err(&data->client->dev, "Error reading reg_int_src1\n");
  1135. goto ack_intr;
  1136. }
  1137. if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
  1138. if (data->info == &kxtf9_info)
  1139. iio_push_event(indio_dev,
  1140. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  1141. 0,
  1142. IIO_MOD_X_AND_Y_AND_Z,
  1143. IIO_EV_TYPE_THRESH,
  1144. IIO_EV_DIR_RISING),
  1145. data->timestamp);
  1146. else
  1147. kxcjk1013_report_motion_event(indio_dev);
  1148. }
  1149. ack_intr:
  1150. if (data->dready_trigger_on)
  1151. return IRQ_HANDLED;
  1152. ret = i2c_smbus_read_byte_data(data->client, regs->int_rel);
  1153. if (ret < 0)
  1154. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  1155. return IRQ_HANDLED;
  1156. }
  1157. static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
  1158. {
  1159. struct iio_dev *indio_dev = private;
  1160. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1161. data->timestamp = iio_get_time_ns(indio_dev);
  1162. if (data->dready_trigger_on)
  1163. iio_trigger_poll(data->dready_trig);
  1164. else if (data->motion_trigger_on)
  1165. iio_trigger_poll(data->motion_trig);
  1166. if (data->ev_enable_state)
  1167. return IRQ_WAKE_THREAD;
  1168. else
  1169. return IRQ_HANDLED;
  1170. }
  1171. static int kxcjk1013_probe(struct i2c_client *client)
  1172. {
  1173. const struct i2c_device_id *id = i2c_client_get_device_id(client);
  1174. static const char * const regulator_names[] = { "vdd", "vddio" };
  1175. struct kxcjk1013_data *data;
  1176. struct iio_dev *indio_dev;
  1177. struct kxcjk_1013_platform_data *pdata;
  1178. const void *ddata = NULL;
  1179. const char *name;
  1180. int ret;
  1181. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  1182. if (!indio_dev)
  1183. return -ENOMEM;
  1184. data = iio_priv(indio_dev);
  1185. i2c_set_clientdata(client, indio_dev);
  1186. data->client = client;
  1187. pdata = dev_get_platdata(&client->dev);
  1188. if (pdata) {
  1189. data->active_high_intr = pdata->active_high_intr;
  1190. data->orientation = pdata->orientation;
  1191. } else {
  1192. data->active_high_intr = true; /* default polarity */
  1193. if (!iio_read_acpi_mount_matrix(&client->dev, &data->orientation, "ROTM")) {
  1194. ret = iio_read_mount_matrix(&client->dev, &data->orientation);
  1195. if (ret)
  1196. return ret;
  1197. }
  1198. }
  1199. ret = devm_regulator_bulk_get_enable(&client->dev,
  1200. ARRAY_SIZE(regulator_names),
  1201. regulator_names);
  1202. if (ret)
  1203. return dev_err_probe(&client->dev, ret, "Failed to get regulators\n");
  1204. /*
  1205. * A typical delay of 10ms is required for powering up
  1206. * according to the data sheets of supported chips.
  1207. * Hence double that to play safe.
  1208. */
  1209. msleep(20);
  1210. if (id) {
  1211. name = id->name;
  1212. data->info = (const struct kx_chipset_info *)(id->driver_data);
  1213. } else {
  1214. name = iio_get_acpi_device_name_and_data(&client->dev, &ddata);
  1215. data->info = ddata;
  1216. if (data->info == &kxcj91008_kiox010a_info)
  1217. indio_dev->label = "accel-display";
  1218. else if (data->info == &kxcj91008_kiox020a_info)
  1219. indio_dev->label = "accel-base";
  1220. }
  1221. if (!name)
  1222. return -ENODEV;
  1223. ret = kxcjk1013_chip_init(data);
  1224. if (ret < 0)
  1225. return ret;
  1226. mutex_init(&data->mutex);
  1227. indio_dev->channels = kxcjk1013_channels;
  1228. indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
  1229. indio_dev->available_scan_masks = kxcjk1013_scan_masks;
  1230. indio_dev->name = name;
  1231. indio_dev->modes = INDIO_DIRECT_MODE;
  1232. indio_dev->info = &kxcjk1013_iio_info;
  1233. if (client->irq > 0 && data->info->acpi_type != ACPI_SMO8500) {
  1234. ret = devm_request_threaded_irq(&client->dev, client->irq,
  1235. kxcjk1013_data_rdy_trig_poll,
  1236. kxcjk1013_event_handler,
  1237. IRQF_TRIGGER_RISING,
  1238. "kxcjk1013_event",
  1239. indio_dev);
  1240. if (ret)
  1241. goto err_poweroff;
  1242. data->dready_trig = devm_iio_trigger_alloc(&client->dev,
  1243. "%s-dev%d",
  1244. indio_dev->name,
  1245. iio_device_id(indio_dev));
  1246. if (!data->dready_trig) {
  1247. ret = -ENOMEM;
  1248. goto err_poweroff;
  1249. }
  1250. data->motion_trig = devm_iio_trigger_alloc(&client->dev,
  1251. "%s-any-motion-dev%d",
  1252. indio_dev->name,
  1253. iio_device_id(indio_dev));
  1254. if (!data->motion_trig) {
  1255. ret = -ENOMEM;
  1256. goto err_poweroff;
  1257. }
  1258. data->dready_trig->ops = &kxcjk1013_trigger_ops;
  1259. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  1260. ret = iio_trigger_register(data->dready_trig);
  1261. if (ret)
  1262. goto err_poweroff;
  1263. indio_dev->trig = iio_trigger_get(data->dready_trig);
  1264. data->motion_trig->ops = &kxcjk1013_trigger_ops;
  1265. iio_trigger_set_drvdata(data->motion_trig, indio_dev);
  1266. ret = iio_trigger_register(data->motion_trig);
  1267. if (ret) {
  1268. data->motion_trig = NULL;
  1269. goto err_trigger_unregister;
  1270. }
  1271. }
  1272. ret = iio_triggered_buffer_setup(indio_dev,
  1273. &iio_pollfunc_store_time,
  1274. kxcjk1013_trigger_handler,
  1275. &kxcjk1013_buffer_setup_ops);
  1276. if (ret < 0) {
  1277. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  1278. goto err_trigger_unregister;
  1279. }
  1280. ret = pm_runtime_set_active(&client->dev);
  1281. if (ret)
  1282. goto err_buffer_cleanup;
  1283. pm_runtime_enable(&client->dev);
  1284. pm_runtime_set_autosuspend_delay(&client->dev,
  1285. KXCJK1013_SLEEP_DELAY_MS);
  1286. pm_runtime_use_autosuspend(&client->dev);
  1287. ret = iio_device_register(indio_dev);
  1288. if (ret < 0) {
  1289. dev_err(&client->dev, "unable to register iio device\n");
  1290. goto err_pm_cleanup;
  1291. }
  1292. return 0;
  1293. err_pm_cleanup:
  1294. pm_runtime_dont_use_autosuspend(&client->dev);
  1295. pm_runtime_disable(&client->dev);
  1296. err_buffer_cleanup:
  1297. iio_triggered_buffer_cleanup(indio_dev);
  1298. err_trigger_unregister:
  1299. if (data->dready_trig)
  1300. iio_trigger_unregister(data->dready_trig);
  1301. if (data->motion_trig)
  1302. iio_trigger_unregister(data->motion_trig);
  1303. err_poweroff:
  1304. kxcjk1013_set_mode(data, STANDBY);
  1305. return ret;
  1306. }
  1307. static void kxcjk1013_remove(struct i2c_client *client)
  1308. {
  1309. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  1310. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1311. iio_device_unregister(indio_dev);
  1312. pm_runtime_disable(&client->dev);
  1313. pm_runtime_set_suspended(&client->dev);
  1314. iio_triggered_buffer_cleanup(indio_dev);
  1315. if (data->dready_trig) {
  1316. iio_trigger_unregister(data->dready_trig);
  1317. iio_trigger_unregister(data->motion_trig);
  1318. }
  1319. mutex_lock(&data->mutex);
  1320. kxcjk1013_set_mode(data, STANDBY);
  1321. mutex_unlock(&data->mutex);
  1322. }
  1323. static int kxcjk1013_suspend(struct device *dev)
  1324. {
  1325. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1326. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1327. int ret;
  1328. mutex_lock(&data->mutex);
  1329. ret = kxcjk1013_set_mode(data, STANDBY);
  1330. mutex_unlock(&data->mutex);
  1331. return ret;
  1332. }
  1333. static int kxcjk1013_resume(struct device *dev)
  1334. {
  1335. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1336. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1337. int ret = 0;
  1338. mutex_lock(&data->mutex);
  1339. ret = kxcjk1013_set_mode(data, OPERATION);
  1340. if (ret == 0)
  1341. ret = kxcjk1013_set_range(data, data->range);
  1342. mutex_unlock(&data->mutex);
  1343. return ret;
  1344. }
  1345. static int kxcjk1013_runtime_suspend(struct device *dev)
  1346. {
  1347. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1348. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1349. int ret;
  1350. ret = kxcjk1013_set_mode(data, STANDBY);
  1351. if (ret < 0) {
  1352. dev_err(&data->client->dev, "powering off device failed\n");
  1353. return -EAGAIN;
  1354. }
  1355. return 0;
  1356. }
  1357. static int kxcjk1013_runtime_resume(struct device *dev)
  1358. {
  1359. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1360. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1361. int ret;
  1362. int sleep_val;
  1363. ret = kxcjk1013_set_mode(data, OPERATION);
  1364. if (ret < 0)
  1365. return ret;
  1366. sleep_val = kxcjk1013_get_startup_times(data);
  1367. if (sleep_val < 20000)
  1368. usleep_range(sleep_val, 20000);
  1369. else
  1370. msleep_interruptible(sleep_val/1000);
  1371. return 0;
  1372. }
  1373. static const struct dev_pm_ops kxcjk1013_pm_ops = {
  1374. SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
  1375. RUNTIME_PM_OPS(kxcjk1013_runtime_suspend, kxcjk1013_runtime_resume, NULL)
  1376. };
  1377. static const struct i2c_device_id kxcjk1013_id[] = {
  1378. { "kxcjk1013", (kernel_ulong_t)&kxcjk1013_info },
  1379. { "kxcj91008", (kernel_ulong_t)&kxcj91008_info },
  1380. { "kxtj21009", (kernel_ulong_t)&kxtj21009_info },
  1381. { "kxtf9", (kernel_ulong_t)&kxtf9_info },
  1382. { "kx023-1025", (kernel_ulong_t)&kx0231025_info },
  1383. { }
  1384. };
  1385. MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
  1386. static const struct of_device_id kxcjk1013_of_match[] = {
  1387. { .compatible = "kionix,kxcjk1013", &kxcjk1013_info },
  1388. { .compatible = "kionix,kxcj91008", &kxcj91008_info },
  1389. { .compatible = "kionix,kxtj21009", &kxtj21009_info },
  1390. { .compatible = "kionix,kxtf9", &kxtf9_info },
  1391. { .compatible = "kionix,kx023-1025", &kx0231025_info },
  1392. { }
  1393. };
  1394. MODULE_DEVICE_TABLE(of, kxcjk1013_of_match);
  1395. static const struct acpi_device_id kx_acpi_match[] = {
  1396. { "KIOX0008", (kernel_ulong_t)&kxcj91008_info },
  1397. { "KIOX0009", (kernel_ulong_t)&kxtj21009_info },
  1398. { "KIOX000A", (kernel_ulong_t)&kxcj91008_info },
  1399. /* KXCJ91008 in the display of a yoga 2-in-1 */
  1400. { "KIOX010A", (kernel_ulong_t)&kxcj91008_kiox010a_info },
  1401. /* KXCJ91008 in the base of a yoga 2-in-1 */
  1402. { "KIOX020A", (kernel_ulong_t)&kxcj91008_kiox020a_info },
  1403. { "KXCJ1008", (kernel_ulong_t)&kxcj91008_info },
  1404. { "KXCJ1013", (kernel_ulong_t)&kxcjk1013_info },
  1405. { "KXCJ9000", (kernel_ulong_t)&kxcj91008_info },
  1406. { "KXJ2109", (kernel_ulong_t)&kxtj21009_info },
  1407. { "KXTJ1009", (kernel_ulong_t)&kxtj21009_info },
  1408. { "SMO8500", (kernel_ulong_t)&kxcj91008_smo8500_info },
  1409. { }
  1410. };
  1411. MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
  1412. static struct i2c_driver kxcjk1013_driver = {
  1413. .driver = {
  1414. .name = "kxcjk1013",
  1415. .acpi_match_table = kx_acpi_match,
  1416. .of_match_table = kxcjk1013_of_match,
  1417. .pm = pm_ptr(&kxcjk1013_pm_ops),
  1418. },
  1419. .probe = kxcjk1013_probe,
  1420. .remove = kxcjk1013_remove,
  1421. .id_table = kxcjk1013_id,
  1422. };
  1423. module_i2c_driver(kxcjk1013_driver);
  1424. MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
  1425. MODULE_LICENSE("GPL v2");
  1426. MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");