sfctemp.c 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
  4. * Copyright (C) 2021 Samin Guo <samin.guo@starfivetech.com>
  5. */
  6. #include <linux/bits.h>
  7. #include <linux/clk.h>
  8. #include <linux/delay.h>
  9. #include <linux/hwmon.h>
  10. #include <linux/io.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/reset.h>
  15. /*
  16. * TempSensor reset. The RSTN can be de-asserted once the analog core has
  17. * powered up. Trst(min 100ns)
  18. * 0:reset 1:de-assert
  19. */
  20. #define SFCTEMP_RSTN BIT(0)
  21. /*
  22. * TempSensor analog core power down. The analog core will be powered up
  23. * Tpu(min 50us) after PD is de-asserted. RSTN should be held low until the
  24. * analog core is powered up.
  25. * 0:power up 1:power down
  26. */
  27. #define SFCTEMP_PD BIT(1)
  28. /*
  29. * TempSensor start conversion enable.
  30. * 0:disable 1:enable
  31. */
  32. #define SFCTEMP_RUN BIT(2)
  33. /*
  34. * TempSensor conversion value output.
  35. * Temp(C)=DOUT*Y/4094 - K
  36. */
  37. #define SFCTEMP_DOUT_POS 16
  38. #define SFCTEMP_DOUT_MSK GENMASK(27, 16)
  39. /* DOUT to Celcius conversion constants */
  40. #define SFCTEMP_Y1000 237500L
  41. #define SFCTEMP_Z 4094L
  42. #define SFCTEMP_K1000 81100L
  43. struct sfctemp {
  44. void __iomem *regs;
  45. struct clk *clk_sense;
  46. struct clk *clk_bus;
  47. struct reset_control *rst_sense;
  48. struct reset_control *rst_bus;
  49. bool enabled;
  50. };
  51. static void sfctemp_power_up(struct sfctemp *sfctemp)
  52. {
  53. /* make sure we're powered down first */
  54. writel(SFCTEMP_PD, sfctemp->regs);
  55. udelay(1);
  56. writel(0, sfctemp->regs);
  57. /* wait t_pu(50us) + t_rst(100ns) */
  58. usleep_range(60, 200);
  59. /* de-assert reset */
  60. writel(SFCTEMP_RSTN, sfctemp->regs);
  61. udelay(1); /* wait t_su(500ps) */
  62. }
  63. static void sfctemp_power_down(struct sfctemp *sfctemp)
  64. {
  65. writel(SFCTEMP_PD, sfctemp->regs);
  66. }
  67. static void sfctemp_run(struct sfctemp *sfctemp)
  68. {
  69. writel(SFCTEMP_RSTN | SFCTEMP_RUN, sfctemp->regs);
  70. udelay(1);
  71. }
  72. static void sfctemp_stop(struct sfctemp *sfctemp)
  73. {
  74. writel(SFCTEMP_RSTN, sfctemp->regs);
  75. }
  76. static int sfctemp_enable(struct sfctemp *sfctemp)
  77. {
  78. int ret;
  79. if (sfctemp->enabled)
  80. return 0;
  81. ret = clk_prepare_enable(sfctemp->clk_bus);
  82. if (ret)
  83. return ret;
  84. ret = reset_control_deassert(sfctemp->rst_bus);
  85. if (ret)
  86. goto err_disable_bus;
  87. ret = clk_prepare_enable(sfctemp->clk_sense);
  88. if (ret)
  89. goto err_assert_bus;
  90. ret = reset_control_deassert(sfctemp->rst_sense);
  91. if (ret)
  92. goto err_disable_sense;
  93. sfctemp_power_up(sfctemp);
  94. sfctemp_run(sfctemp);
  95. sfctemp->enabled = true;
  96. return 0;
  97. err_disable_sense:
  98. clk_disable_unprepare(sfctemp->clk_sense);
  99. err_assert_bus:
  100. reset_control_assert(sfctemp->rst_bus);
  101. err_disable_bus:
  102. clk_disable_unprepare(sfctemp->clk_bus);
  103. return ret;
  104. }
  105. static int sfctemp_disable(struct sfctemp *sfctemp)
  106. {
  107. if (!sfctemp->enabled)
  108. return 0;
  109. sfctemp_stop(sfctemp);
  110. sfctemp_power_down(sfctemp);
  111. reset_control_assert(sfctemp->rst_sense);
  112. clk_disable_unprepare(sfctemp->clk_sense);
  113. reset_control_assert(sfctemp->rst_bus);
  114. clk_disable_unprepare(sfctemp->clk_bus);
  115. sfctemp->enabled = false;
  116. return 0;
  117. }
  118. static void sfctemp_disable_action(void *data)
  119. {
  120. sfctemp_disable(data);
  121. }
  122. static int sfctemp_convert(struct sfctemp *sfctemp, long *val)
  123. {
  124. if (!sfctemp->enabled)
  125. return -ENODATA;
  126. /* calculate temperature in milli Celcius */
  127. *val = (long)((readl(sfctemp->regs) & SFCTEMP_DOUT_MSK) >> SFCTEMP_DOUT_POS)
  128. * SFCTEMP_Y1000 / SFCTEMP_Z - SFCTEMP_K1000;
  129. return 0;
  130. }
  131. static umode_t sfctemp_is_visible(const void *data, enum hwmon_sensor_types type,
  132. u32 attr, int channel)
  133. {
  134. switch (type) {
  135. case hwmon_temp:
  136. switch (attr) {
  137. case hwmon_temp_enable:
  138. return 0644;
  139. case hwmon_temp_input:
  140. return 0444;
  141. default:
  142. return 0;
  143. }
  144. default:
  145. return 0;
  146. }
  147. }
  148. static int sfctemp_read(struct device *dev, enum hwmon_sensor_types type,
  149. u32 attr, int channel, long *val)
  150. {
  151. struct sfctemp *sfctemp = dev_get_drvdata(dev);
  152. switch (type) {
  153. case hwmon_temp:
  154. switch (attr) {
  155. case hwmon_temp_enable:
  156. *val = sfctemp->enabled;
  157. return 0;
  158. case hwmon_temp_input:
  159. return sfctemp_convert(sfctemp, val);
  160. default:
  161. return -EINVAL;
  162. }
  163. default:
  164. return -EINVAL;
  165. }
  166. }
  167. static int sfctemp_write(struct device *dev, enum hwmon_sensor_types type,
  168. u32 attr, int channel, long val)
  169. {
  170. struct sfctemp *sfctemp = dev_get_drvdata(dev);
  171. switch (type) {
  172. case hwmon_temp:
  173. switch (attr) {
  174. case hwmon_temp_enable:
  175. if (val == 0)
  176. return sfctemp_disable(sfctemp);
  177. if (val == 1)
  178. return sfctemp_enable(sfctemp);
  179. return -EINVAL;
  180. default:
  181. return -EINVAL;
  182. }
  183. default:
  184. return -EINVAL;
  185. }
  186. }
  187. static const struct hwmon_channel_info *sfctemp_info[] = {
  188. HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
  189. HWMON_CHANNEL_INFO(temp, HWMON_T_ENABLE | HWMON_T_INPUT),
  190. NULL
  191. };
  192. static const struct hwmon_ops sfctemp_hwmon_ops = {
  193. .is_visible = sfctemp_is_visible,
  194. .read = sfctemp_read,
  195. .write = sfctemp_write,
  196. };
  197. static const struct hwmon_chip_info sfctemp_chip_info = {
  198. .ops = &sfctemp_hwmon_ops,
  199. .info = sfctemp_info,
  200. };
  201. static int sfctemp_probe(struct platform_device *pdev)
  202. {
  203. struct device *dev = &pdev->dev;
  204. struct device *hwmon_dev;
  205. struct sfctemp *sfctemp;
  206. int ret;
  207. sfctemp = devm_kzalloc(dev, sizeof(*sfctemp), GFP_KERNEL);
  208. if (!sfctemp)
  209. return -ENOMEM;
  210. dev_set_drvdata(dev, sfctemp);
  211. sfctemp->regs = devm_platform_ioremap_resource(pdev, 0);
  212. if (IS_ERR(sfctemp->regs))
  213. return PTR_ERR(sfctemp->regs);
  214. sfctemp->clk_sense = devm_clk_get(dev, "sense");
  215. if (IS_ERR(sfctemp->clk_sense))
  216. return dev_err_probe(dev, PTR_ERR(sfctemp->clk_sense),
  217. "error getting sense clock\n");
  218. sfctemp->clk_bus = devm_clk_get(dev, "bus");
  219. if (IS_ERR(sfctemp->clk_bus))
  220. return dev_err_probe(dev, PTR_ERR(sfctemp->clk_bus),
  221. "error getting bus clock\n");
  222. sfctemp->rst_sense = devm_reset_control_get_exclusive(dev, "sense");
  223. if (IS_ERR(sfctemp->rst_sense))
  224. return dev_err_probe(dev, PTR_ERR(sfctemp->rst_sense),
  225. "error getting sense reset\n");
  226. sfctemp->rst_bus = devm_reset_control_get_exclusive(dev, "bus");
  227. if (IS_ERR(sfctemp->rst_bus))
  228. return dev_err_probe(dev, PTR_ERR(sfctemp->rst_bus),
  229. "error getting busreset\n");
  230. ret = reset_control_assert(sfctemp->rst_sense);
  231. if (ret)
  232. return dev_err_probe(dev, ret, "error asserting sense reset\n");
  233. ret = reset_control_assert(sfctemp->rst_bus);
  234. if (ret)
  235. return dev_err_probe(dev, ret, "error asserting bus reset\n");
  236. ret = devm_add_action(dev, sfctemp_disable_action, sfctemp);
  237. if (ret)
  238. return ret;
  239. ret = sfctemp_enable(sfctemp);
  240. if (ret)
  241. return dev_err_probe(dev, ret, "error enabling temperature sensor\n");
  242. hwmon_dev = devm_hwmon_device_register_with_info(dev, "sfctemp", sfctemp,
  243. &sfctemp_chip_info, NULL);
  244. return PTR_ERR_OR_ZERO(hwmon_dev);
  245. }
  246. static const struct of_device_id sfctemp_of_match[] = {
  247. { .compatible = "starfive,jh7100-temp" },
  248. { .compatible = "starfive,jh7110-temp" },
  249. { /* sentinel */ }
  250. };
  251. MODULE_DEVICE_TABLE(of, sfctemp_of_match);
  252. static struct platform_driver sfctemp_driver = {
  253. .probe = sfctemp_probe,
  254. .driver = {
  255. .name = "sfctemp",
  256. .of_match_table = sfctemp_of_match,
  257. },
  258. };
  259. module_platform_driver(sfctemp_driver);
  260. MODULE_AUTHOR("Emil Renner Berthing");
  261. MODULE_DESCRIPTION("StarFive JH71x0 temperature sensor driver");
  262. MODULE_LICENSE("GPL");