gsp.rs 1.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. use kernel::{
  3. io::poll::read_poll_timeout,
  4. prelude::*,
  5. time::Delta, //
  6. };
  7. use crate::{
  8. driver::Bar0,
  9. falcon::{
  10. Falcon,
  11. FalconEngine,
  12. PFalcon2Base,
  13. PFalconBase, //
  14. },
  15. regs::{
  16. self,
  17. macros::RegisterBase, //
  18. },
  19. };
  20. /// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
  21. pub(crate) struct Gsp(());
  22. impl RegisterBase<PFalconBase> for Gsp {
  23. const BASE: usize = 0x00110000;
  24. }
  25. impl RegisterBase<PFalcon2Base> for Gsp {
  26. const BASE: usize = 0x00111000;
  27. }
  28. impl FalconEngine for Gsp {
  29. const ID: Self = Gsp(());
  30. }
  31. impl Falcon<Gsp> {
  32. /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to
  33. /// allow GSP to signal CPU for processing new messages in message queue.
  34. pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
  35. regs::NV_PFALCON_FALCON_IRQSCLR::default()
  36. .set_swgen0(true)
  37. .write(bar, &Gsp::ID);
  38. }
  39. /// Checks if GSP reload/resume has completed during the boot process.
  40. pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> {
  41. read_poll_timeout(
  42. || Ok(regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar)),
  43. |val| val.boot_stage_3_handoff(),
  44. Delta::ZERO,
  45. timeout,
  46. )
  47. .map(|_| true)
  48. }
  49. }