debug_hw.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2010 Google, Inc.
  4. * Author: Erik Gilling <konkers@android.com>
  5. *
  6. * Copyright (C) 2011-2013 NVIDIA Corporation
  7. */
  8. #include "../dev.h"
  9. #include "../debug.h"
  10. #include "../cdma.h"
  11. #include "../channel.h"
  12. #define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400
  13. enum {
  14. HOST1X_OPCODE_SETCLASS = 0x00,
  15. HOST1X_OPCODE_INCR = 0x01,
  16. HOST1X_OPCODE_NONINCR = 0x02,
  17. HOST1X_OPCODE_MASK = 0x03,
  18. HOST1X_OPCODE_IMM = 0x04,
  19. HOST1X_OPCODE_RESTART = 0x05,
  20. HOST1X_OPCODE_GATHER = 0x06,
  21. HOST1X_OPCODE_SETSTRMID = 0x07,
  22. HOST1X_OPCODE_SETAPPID = 0x08,
  23. HOST1X_OPCODE_SETPYLD = 0x09,
  24. HOST1X_OPCODE_INCR_W = 0x0a,
  25. HOST1X_OPCODE_NONINCR_W = 0x0b,
  26. HOST1X_OPCODE_GATHER_W = 0x0c,
  27. HOST1X_OPCODE_RESTART_W = 0x0d,
  28. HOST1X_OPCODE_EXTEND = 0x0e,
  29. };
  30. enum {
  31. HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00,
  32. HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
  33. };
  34. #define INVALID_PAYLOAD 0xffffffff
  35. static unsigned int show_channel_command(struct output *o, u32 val,
  36. u32 *payload)
  37. {
  38. unsigned int mask, subop, num, opcode;
  39. opcode = val >> 28;
  40. switch (opcode) {
  41. case HOST1X_OPCODE_SETCLASS:
  42. mask = val & 0x3f;
  43. if (mask) {
  44. host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [",
  45. val >> 6 & 0x3ff,
  46. val >> 16 & 0xfff, mask);
  47. return hweight8(mask);
  48. }
  49. host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff);
  50. return 0;
  51. case HOST1X_OPCODE_INCR:
  52. num = val & 0xffff;
  53. host1x_debug_cont(o, "INCR(offset=%03x, [",
  54. val >> 16 & 0xfff);
  55. if (!num)
  56. host1x_debug_cont(o, "])\n");
  57. return num;
  58. case HOST1X_OPCODE_NONINCR:
  59. num = val & 0xffff;
  60. host1x_debug_cont(o, "NONINCR(offset=%03x, [",
  61. val >> 16 & 0xfff);
  62. if (!num)
  63. host1x_debug_cont(o, "])\n");
  64. return num;
  65. case HOST1X_OPCODE_MASK:
  66. mask = val & 0xffff;
  67. host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [",
  68. val >> 16 & 0xfff, mask);
  69. if (!mask)
  70. host1x_debug_cont(o, "])\n");
  71. return hweight16(mask);
  72. case HOST1X_OPCODE_IMM:
  73. host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n",
  74. val >> 16 & 0xfff, val & 0xffff);
  75. return 0;
  76. case HOST1X_OPCODE_RESTART:
  77. host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4);
  78. return 0;
  79. case HOST1X_OPCODE_GATHER:
  80. host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[",
  81. val >> 16 & 0xfff, val >> 15 & 0x1,
  82. val >> 14 & 0x1, val & 0x3fff);
  83. return 1;
  84. #if HOST1X_HW >= 6
  85. case HOST1X_OPCODE_SETSTRMID:
  86. host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
  87. val & 0x3fffff);
  88. return 0;
  89. case HOST1X_OPCODE_SETAPPID:
  90. host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
  91. return 0;
  92. case HOST1X_OPCODE_SETPYLD:
  93. *payload = val & 0xffff;
  94. host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
  95. return 0;
  96. case HOST1X_OPCODE_INCR_W:
  97. case HOST1X_OPCODE_NONINCR_W:
  98. host1x_debug_cont(o, "%s(offset=%06x, ",
  99. opcode == HOST1X_OPCODE_INCR_W ?
  100. "INCR_W" : "NONINCR_W",
  101. val & 0x3fffff);
  102. if (*payload == 0) {
  103. host1x_debug_cont(o, "[])\n");
  104. return 0;
  105. } else if (*payload == INVALID_PAYLOAD) {
  106. host1x_debug_cont(o, "unknown)\n");
  107. return 0;
  108. } else {
  109. host1x_debug_cont(o, "[");
  110. return *payload;
  111. }
  112. case HOST1X_OPCODE_GATHER_W:
  113. host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
  114. val & 0x3fff);
  115. return 2;
  116. #endif
  117. case HOST1X_OPCODE_EXTEND:
  118. subop = val >> 24 & 0xf;
  119. if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
  120. host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n",
  121. val & 0xff);
  122. else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK)
  123. host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n",
  124. val & 0xff);
  125. else
  126. host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val);
  127. return 0;
  128. default:
  129. host1x_debug_cont(o, "UNKNOWN\n");
  130. return 0;
  131. }
  132. }
  133. static void show_gather(struct output *o, dma_addr_t phys_addr,
  134. unsigned int words, struct host1x_cdma *cdma,
  135. dma_addr_t pin_addr, u32 *map_addr)
  136. {
  137. /* Map dmaget cursor to corresponding mem handle */
  138. u32 offset = phys_addr - pin_addr;
  139. unsigned int data_count = 0, i;
  140. u32 payload = INVALID_PAYLOAD;
  141. /*
  142. * Sometimes we're given different hardware address to the same
  143. * page - in these cases the offset will get an invalid number and
  144. * we just have to bail out.
  145. */
  146. if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) {
  147. host1x_debug_output(o, "[address mismatch]\n");
  148. return;
  149. }
  150. for (i = 0; i < words; i++) {
  151. dma_addr_t addr = phys_addr + i * 4;
  152. u32 voffset = offset + i * 4;
  153. u32 val;
  154. /* If we reach the RESTART opcode, continue at the beginning of pushbuffer */
  155. if (cdma && voffset >= cdma->push_buffer.size) {
  156. addr -= cdma->push_buffer.size;
  157. voffset -= cdma->push_buffer.size;
  158. }
  159. val = *(map_addr + voffset / 4);
  160. if (!data_count) {
  161. host1x_debug_output(o, " %pad: %08x: ", &addr, val);
  162. data_count = show_channel_command(o, val, &payload);
  163. } else {
  164. host1x_debug_cont(o, "%08x%s", val,
  165. data_count > 1 ? ", " : "])\n");
  166. data_count--;
  167. }
  168. }
  169. }
  170. static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma)
  171. {
  172. struct push_buffer *pb = &cdma->push_buffer;
  173. struct host1x_job *job;
  174. list_for_each_entry(job, &cdma->sync_queue, list) {
  175. unsigned int i;
  176. host1x_debug_output(o, "JOB, syncpt %u: %u timeout: %u num_slots: %u num_handles: %u\n",
  177. job->syncpt->id, job->syncpt_end, job->timeout,
  178. job->num_slots, job->num_unpins);
  179. show_gather(o, pb->dma + job->first_get, job->num_slots * 2, cdma,
  180. pb->dma, pb->mapped);
  181. for (i = 0; i < job->num_cmds; i++) {
  182. struct host1x_job_gather *g;
  183. u32 *mapped;
  184. if (job->cmds[i].is_wait)
  185. continue;
  186. g = &job->cmds[i].gather;
  187. if (job->gather_copy_mapped)
  188. mapped = (u32 *)job->gather_copy_mapped;
  189. else
  190. mapped = host1x_bo_mmap(g->bo);
  191. if (!mapped) {
  192. host1x_debug_output(o, "[could not mmap]\n");
  193. continue;
  194. }
  195. host1x_debug_output(o, " GATHER at %pad+%#x, %d words\n",
  196. &g->base, g->offset, g->words);
  197. show_gather(o, g->base + g->offset, g->words, NULL,
  198. g->base, mapped);
  199. if (!job->gather_copy_mapped)
  200. host1x_bo_munmap(g->bo, mapped);
  201. }
  202. }
  203. }
  204. #if HOST1X_HW >= 6
  205. #include "debug_hw_1x06.c"
  206. #else
  207. #include "debug_hw_1x01.c"
  208. #endif
  209. static const struct host1x_debug_ops host1x_debug_ops = {
  210. .show_channel_cdma = host1x_debug_show_channel_cdma,
  211. .show_channel_fifo = host1x_debug_show_channel_fifo,
  212. .show_mlocks = host1x_debug_show_mlocks,
  213. };