fb.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012-2013 Avionic Design GmbH
  4. * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
  5. *
  6. * Based on the KMS/FB DMA helpers
  7. * Copyright (C) 2012 Analog Devices Inc.
  8. */
  9. #include <linux/console.h>
  10. #include <drm/drm_fourcc.h>
  11. #include <drm/drm_framebuffer.h>
  12. #include <drm/drm_gem_framebuffer_helper.h>
  13. #include <drm/drm_modeset_helper.h>
  14. #include <drm/drm_print.h>
  15. #include "drm.h"
  16. #include "gem.h"
  17. struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
  18. unsigned int index)
  19. {
  20. return to_tegra_bo(drm_gem_fb_get_obj(framebuffer, index));
  21. }
  22. bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer)
  23. {
  24. struct tegra_bo *bo = tegra_fb_get_plane(framebuffer, 0);
  25. if (bo->flags & TEGRA_BO_BOTTOM_UP)
  26. return true;
  27. return false;
  28. }
  29. int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
  30. struct tegra_bo_tiling *tiling)
  31. {
  32. uint64_t modifier = framebuffer->modifier;
  33. if (fourcc_mod_is_vendor(modifier, NVIDIA)) {
  34. if ((modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) == 0)
  35. tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_TEGRA;
  36. else
  37. tiling->sector_layout = TEGRA_BO_SECTOR_LAYOUT_GPU;
  38. modifier &= ~DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT;
  39. }
  40. switch (modifier) {
  41. case DRM_FORMAT_MOD_LINEAR:
  42. tiling->mode = TEGRA_BO_TILING_MODE_PITCH;
  43. tiling->value = 0;
  44. break;
  45. case DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED:
  46. tiling->mode = TEGRA_BO_TILING_MODE_TILED;
  47. tiling->value = 0;
  48. break;
  49. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0):
  50. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  51. tiling->value = 0;
  52. break;
  53. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1):
  54. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  55. tiling->value = 1;
  56. break;
  57. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2):
  58. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  59. tiling->value = 2;
  60. break;
  61. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3):
  62. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  63. tiling->value = 3;
  64. break;
  65. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4):
  66. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  67. tiling->value = 4;
  68. break;
  69. case DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5):
  70. tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
  71. tiling->value = 5;
  72. break;
  73. default:
  74. DRM_DEBUG_KMS("unknown format modifier: %llx\n", modifier);
  75. return -EINVAL;
  76. }
  77. return 0;
  78. }
  79. static const struct drm_framebuffer_funcs tegra_fb_funcs = {
  80. .destroy = drm_gem_fb_destroy,
  81. .create_handle = drm_gem_fb_create_handle,
  82. };
  83. struct drm_framebuffer *tegra_fb_alloc(struct drm_device *drm,
  84. const struct drm_format_info *info,
  85. const struct drm_mode_fb_cmd2 *mode_cmd,
  86. struct tegra_bo **planes,
  87. unsigned int num_planes)
  88. {
  89. struct drm_framebuffer *fb;
  90. unsigned int i;
  91. int err;
  92. fb = kzalloc_obj(*fb);
  93. if (!fb)
  94. return ERR_PTR(-ENOMEM);
  95. drm_helper_mode_fill_fb_struct(drm, fb, info, mode_cmd);
  96. for (i = 0; i < fb->format->num_planes; i++)
  97. fb->obj[i] = &planes[i]->gem;
  98. err = drm_framebuffer_init(drm, fb, &tegra_fb_funcs);
  99. if (err < 0) {
  100. dev_err(drm->dev, "failed to initialize framebuffer: %d\n",
  101. err);
  102. kfree(fb);
  103. return ERR_PTR(err);
  104. }
  105. return fb;
  106. }
  107. struct drm_framebuffer *tegra_fb_create(struct drm_device *drm,
  108. struct drm_file *file,
  109. const struct drm_format_info *info,
  110. const struct drm_mode_fb_cmd2 *cmd)
  111. {
  112. struct tegra_bo *planes[4];
  113. struct drm_gem_object *gem;
  114. struct drm_framebuffer *fb;
  115. unsigned int i;
  116. int err;
  117. for (i = 0; i < info->num_planes; i++) {
  118. unsigned int width = cmd->width / (i ? info->hsub : 1);
  119. unsigned int height = cmd->height / (i ? info->vsub : 1);
  120. unsigned int size, bpp;
  121. gem = drm_gem_object_lookup(file, cmd->handles[i]);
  122. if (!gem) {
  123. err = -ENXIO;
  124. goto unreference;
  125. }
  126. bpp = info->cpp[i];
  127. size = (height - 1) * cmd->pitches[i] +
  128. width * bpp + cmd->offsets[i];
  129. if (gem->size < size) {
  130. err = -EINVAL;
  131. drm_gem_object_put(gem);
  132. goto unreference;
  133. }
  134. planes[i] = to_tegra_bo(gem);
  135. }
  136. fb = tegra_fb_alloc(drm, info, cmd, planes, i);
  137. if (IS_ERR(fb)) {
  138. err = PTR_ERR(fb);
  139. goto unreference;
  140. }
  141. return fb;
  142. unreference:
  143. while (i--)
  144. drm_gem_object_put(&planes[i]->gem);
  145. return ERR_PTR(err);
  146. }