radeon_agp.c 12 KB

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  1. /*
  2. * Copyright 2008 Red Hat Inc.
  3. * Copyright 2009 Jerome Glisse.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice shall be included in
  13. * all copies or substantial portions of the Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Dave Airlie
  25. * Jerome Glisse <glisse@freedesktop.org>
  26. */
  27. #include <linux/pci.h>
  28. #include <drm/drm_device.h>
  29. #include <drm/radeon_drm.h>
  30. #include "radeon.h"
  31. #if IS_ENABLED(CONFIG_AGP)
  32. struct radeon_agpmode_quirk {
  33. u32 hostbridge_vendor;
  34. u32 hostbridge_device;
  35. u32 chip_vendor;
  36. u32 chip_device;
  37. u32 subsys_vendor;
  38. u32 subsys_device;
  39. u32 default_mode;
  40. };
  41. static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
  42. /* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */
  43. { PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4},
  44. /* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */
  45. { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4},
  46. /* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */
  47. { PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964,
  48. 0x148c, 0x2073, 4},
  49. /* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */
  50. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59,
  51. PCI_VENDOR_ID_IBM, 0x052f, 1},
  52. /* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */
  53. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50,
  54. PCI_VENDOR_ID_IBM, 0x0550, 1},
  55. /* Intel 82855PM host bridge / RV250/M9 GL [Mobility FireGL 9000/Radeon 9000] needs AGPMode 1 (Thinkpad T40p) */
  56. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
  57. PCI_VENDOR_ID_IBM, 0x054d, 1},
  58. /* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */
  59. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57,
  60. PCI_VENDOR_ID_IBM, 0x0530, 1},
  61. /* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */
  62. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54,
  63. PCI_VENDOR_ID_IBM, 0x054f, 2},
  64. /* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */
  65. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
  66. PCI_VENDOR_ID_SONY, 0x816b, 2},
  67. /* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */
  68. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
  69. PCI_VENDOR_ID_SONY, 0x8195, 8},
  70. /* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
  71. { PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
  72. PCI_VENDOR_ID_DELL, 0x00e3, 2},
  73. /* Intel 82852/82855 host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 (lp #296617) */
  74. { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
  75. PCI_VENDOR_ID_DELL, 0x0149, 1},
  76. /* Intel 82855PM host bridge / Mobility FireGL 9000 RV250 Needs AGPMode 1 for suspend/resume */
  77. { PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c66,
  78. PCI_VENDOR_ID_IBM, 0x0531, 1},
  79. /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
  80. { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
  81. 0x1025, 0x0061, 1},
  82. /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */
  83. { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
  84. 0x1025, 0x0064, 1},
  85. /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */
  86. { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
  87. PCI_VENDOR_ID_ASUSTEK, 0x1942, 1},
  88. /* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */
  89. { PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
  90. 0x10cf, 0x127f, 1},
  91. /* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */
  92. { 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
  93. 0x1787, 0x5960, 4},
  94. /* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */
  95. { PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960,
  96. 0x17af, 0x2020, 4},
  97. /* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */
  98. { PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153,
  99. PCI_VENDOR_ID_ASUSTEK, 0x003c, 4},
  100. /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */
  101. { PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c,
  102. PCI_VENDOR_ID_ATI, 0x013a, 2},
  103. /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */
  104. { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
  105. PCI_VENDOR_ID_ASUSTEK, 0x004c, 2},
  106. /* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */
  107. { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
  108. PCI_VENDOR_ID_ASUSTEK, 0x0054, 2},
  109. /* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */
  110. { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d,
  111. 0x174b, 0x7149, 4},
  112. /* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */
  113. { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
  114. 0x1462, 0x0380, 4},
  115. /* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */
  116. { PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964,
  117. 0x148c, 0x2073, 4},
  118. /* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */
  119. { PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61,
  120. PCI_VENDOR_ID_SONY, 0x8175, 1},
  121. { 0, 0, 0, 0, 0, 0, 0 },
  122. };
  123. struct radeon_agp_head *radeon_agp_head_init(struct drm_device *dev)
  124. {
  125. struct pci_dev *pdev = to_pci_dev(dev->dev);
  126. struct radeon_agp_head *head;
  127. head = kzalloc_obj(*head);
  128. if (!head)
  129. return NULL;
  130. head->bridge = agp_find_bridge(pdev);
  131. if (!head->bridge) {
  132. head->bridge = agp_backend_acquire(pdev);
  133. if (!head->bridge) {
  134. kfree(head);
  135. return NULL;
  136. }
  137. agp_copy_info(head->bridge, &head->agp_info);
  138. agp_backend_release(head->bridge);
  139. } else {
  140. agp_copy_info(head->bridge, &head->agp_info);
  141. }
  142. if (head->agp_info.chipset == NOT_SUPPORTED) {
  143. kfree(head);
  144. return NULL;
  145. }
  146. INIT_LIST_HEAD(&head->memory);
  147. head->cant_use_aperture = head->agp_info.cant_use_aperture;
  148. head->page_mask = head->agp_info.page_mask;
  149. head->base = head->agp_info.aper_base;
  150. return head;
  151. }
  152. static int radeon_agp_head_acquire(struct radeon_device *rdev)
  153. {
  154. struct drm_device *dev = rdev_to_drm(rdev);
  155. struct pci_dev *pdev = to_pci_dev(dev->dev);
  156. if (!rdev->agp)
  157. return -ENODEV;
  158. if (rdev->agp->acquired)
  159. return -EBUSY;
  160. rdev->agp->bridge = agp_backend_acquire(pdev);
  161. if (!rdev->agp->bridge)
  162. return -ENODEV;
  163. rdev->agp->acquired = 1;
  164. return 0;
  165. }
  166. static int radeon_agp_head_release(struct radeon_device *rdev)
  167. {
  168. if (!rdev->agp || !rdev->agp->acquired)
  169. return -EINVAL;
  170. agp_backend_release(rdev->agp->bridge);
  171. rdev->agp->acquired = 0;
  172. return 0;
  173. }
  174. static int radeon_agp_head_enable(struct radeon_device *rdev, struct radeon_agp_mode mode)
  175. {
  176. if (!rdev->agp || !rdev->agp->acquired)
  177. return -EINVAL;
  178. rdev->agp->mode = mode.mode;
  179. agp_enable(rdev->agp->bridge, mode.mode);
  180. rdev->agp->enabled = 1;
  181. return 0;
  182. }
  183. static int radeon_agp_head_info(struct radeon_device *rdev, struct radeon_agp_info *info)
  184. {
  185. struct agp_kern_info *kern;
  186. if (!rdev->agp || !rdev->agp->acquired)
  187. return -EINVAL;
  188. kern = &rdev->agp->agp_info;
  189. info->agp_version_major = kern->version.major;
  190. info->agp_version_minor = kern->version.minor;
  191. info->mode = kern->mode;
  192. info->aperture_base = kern->aper_base;
  193. info->aperture_size = kern->aper_size * 1024 * 1024;
  194. info->memory_allowed = kern->max_memory << PAGE_SHIFT;
  195. info->memory_used = kern->current_memory << PAGE_SHIFT;
  196. info->id_vendor = kern->device->vendor;
  197. info->id_device = kern->device->device;
  198. return 0;
  199. }
  200. #endif
  201. int radeon_agp_init(struct radeon_device *rdev)
  202. {
  203. #if IS_ENABLED(CONFIG_AGP)
  204. struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
  205. struct radeon_agp_mode mode;
  206. struct radeon_agp_info info;
  207. uint32_t agp_status;
  208. int default_mode;
  209. bool is_v3;
  210. int ret;
  211. /* Acquire AGP. */
  212. ret = radeon_agp_head_acquire(rdev);
  213. if (ret) {
  214. DRM_ERROR("Unable to acquire AGP: %d\n", ret);
  215. return ret;
  216. }
  217. ret = radeon_agp_head_info(rdev, &info);
  218. if (ret) {
  219. radeon_agp_head_release(rdev);
  220. DRM_ERROR("Unable to get AGP info: %d\n", ret);
  221. return ret;
  222. }
  223. if (rdev->agp->agp_info.aper_size < 32) {
  224. radeon_agp_head_release(rdev);
  225. dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
  226. "need at least 32M, disabling AGP\n",
  227. rdev->agp->agp_info.aper_size);
  228. return -EINVAL;
  229. }
  230. mode.mode = info.mode;
  231. /* chips with the agp to pcie bridge don't have the AGP_STATUS register
  232. * Just use the whatever mode the host sets up.
  233. */
  234. if (rdev->family <= CHIP_RV350)
  235. agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
  236. else
  237. agp_status = mode.mode;
  238. is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
  239. if (is_v3) {
  240. default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
  241. } else {
  242. if (agp_status & RADEON_AGP_4X_MODE) {
  243. default_mode = 4;
  244. } else if (agp_status & RADEON_AGP_2X_MODE) {
  245. default_mode = 2;
  246. } else {
  247. default_mode = 1;
  248. }
  249. }
  250. /* Apply AGPMode Quirks */
  251. while (p && p->chip_device != 0) {
  252. if (info.id_vendor == p->hostbridge_vendor &&
  253. info.id_device == p->hostbridge_device &&
  254. rdev->pdev->vendor == p->chip_vendor &&
  255. rdev->pdev->device == p->chip_device &&
  256. rdev->pdev->subsystem_vendor == p->subsys_vendor &&
  257. rdev->pdev->subsystem_device == p->subsys_device) {
  258. default_mode = p->default_mode;
  259. }
  260. ++p;
  261. }
  262. if (radeon_agpmode > 0) {
  263. if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
  264. (radeon_agpmode > (is_v3 ? 8 : 4)) ||
  265. (radeon_agpmode & (radeon_agpmode - 1))) {
  266. DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
  267. radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
  268. default_mode);
  269. radeon_agpmode = default_mode;
  270. } else {
  271. DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
  272. }
  273. } else {
  274. radeon_agpmode = default_mode;
  275. }
  276. mode.mode &= ~RADEON_AGP_MODE_MASK;
  277. if (is_v3) {
  278. switch (radeon_agpmode) {
  279. case 8:
  280. mode.mode |= RADEON_AGPv3_8X_MODE;
  281. break;
  282. case 4:
  283. default:
  284. mode.mode |= RADEON_AGPv3_4X_MODE;
  285. break;
  286. }
  287. } else {
  288. switch (radeon_agpmode) {
  289. case 4:
  290. mode.mode |= RADEON_AGP_4X_MODE;
  291. break;
  292. case 2:
  293. mode.mode |= RADEON_AGP_2X_MODE;
  294. break;
  295. case 1:
  296. default:
  297. mode.mode |= RADEON_AGP_1X_MODE;
  298. break;
  299. }
  300. }
  301. mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
  302. ret = radeon_agp_head_enable(rdev, mode);
  303. if (ret) {
  304. DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
  305. radeon_agp_head_release(rdev);
  306. return ret;
  307. }
  308. rdev->mc.agp_base = rdev->agp->agp_info.aper_base;
  309. rdev->mc.gtt_size = rdev->agp->agp_info.aper_size << 20;
  310. rdev->mc.gtt_start = rdev->mc.agp_base;
  311. rdev->mc.gtt_end = rdev->mc.gtt_start + rdev->mc.gtt_size - 1;
  312. dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
  313. rdev->mc.gtt_size >> 20, rdev->mc.gtt_start, rdev->mc.gtt_end);
  314. /* workaround some hw issues */
  315. if (rdev->family < CHIP_R200) {
  316. WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
  317. }
  318. return 0;
  319. #else
  320. return 0;
  321. #endif
  322. }
  323. void radeon_agp_resume(struct radeon_device *rdev)
  324. {
  325. #if IS_ENABLED(CONFIG_AGP)
  326. int r;
  327. if (rdev->flags & RADEON_IS_AGP) {
  328. r = radeon_agp_init(rdev);
  329. if (r)
  330. dev_warn(rdev->dev, "radeon AGP reinit failed\n");
  331. }
  332. #endif
  333. }
  334. void radeon_agp_fini(struct radeon_device *rdev)
  335. {
  336. #if IS_ENABLED(CONFIG_AGP)
  337. if (rdev->agp && rdev->agp->acquired) {
  338. radeon_agp_head_release(rdev);
  339. }
  340. #endif
  341. }
  342. void radeon_agp_suspend(struct radeon_device *rdev)
  343. {
  344. radeon_agp_fini(rdev);
  345. }