hdmi5.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * HDMI driver for OMAP5
  4. *
  5. * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
  6. *
  7. * Authors:
  8. * Yong Zhi
  9. * Mythri pk
  10. * Archit Taneja <archit@ti.com>
  11. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  12. */
  13. #define DSS_SUBSYS_NAME "HDMI"
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/mutex.h>
  20. #include <linux/delay.h>
  21. #include <linux/string.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/clk.h>
  25. #include <linux/regulator/consumer.h>
  26. #include <linux/component.h>
  27. #include <linux/of.h>
  28. #include <linux/of_graph.h>
  29. #include <sound/omap-hdmi-audio.h>
  30. #include <drm/drm_atomic.h>
  31. #include <drm/drm_atomic_state_helper.h>
  32. #include <drm/drm_edid.h>
  33. #include "omapdss.h"
  34. #include "hdmi5_core.h"
  35. #include "dss.h"
  36. static int hdmi_runtime_get(struct omap_hdmi *hdmi)
  37. {
  38. int r;
  39. DSSDBG("hdmi_runtime_get\n");
  40. r = pm_runtime_get_sync(&hdmi->pdev->dev);
  41. if (WARN_ON(r < 0)) {
  42. pm_runtime_put_noidle(&hdmi->pdev->dev);
  43. return r;
  44. }
  45. return 0;
  46. }
  47. static void hdmi_runtime_put(struct omap_hdmi *hdmi)
  48. {
  49. int r;
  50. DSSDBG("hdmi_runtime_put\n");
  51. r = pm_runtime_put_sync(&hdmi->pdev->dev);
  52. WARN_ON(r < 0 && r != -ENOSYS);
  53. }
  54. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  55. {
  56. struct omap_hdmi *hdmi = data;
  57. struct hdmi_wp_data *wp = &hdmi->wp;
  58. u32 irqstatus;
  59. irqstatus = hdmi_wp_get_irqstatus(wp);
  60. hdmi_wp_set_irqstatus(wp, irqstatus);
  61. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  62. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  63. u32 v;
  64. /*
  65. * If we get both connect and disconnect interrupts at the same
  66. * time, turn off the PHY, clear interrupts, and restart, which
  67. * raises connect interrupt if a cable is connected, or nothing
  68. * if cable is not connected.
  69. */
  70. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  71. /*
  72. * We always get bogus CONNECT & DISCONNECT interrupts when
  73. * setting the PHY to LDOON. To ignore those, we force the RXDET
  74. * line to 0 until the PHY power state has been changed.
  75. */
  76. v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  77. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  78. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  79. hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  80. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  81. HDMI_IRQ_LINK_DISCONNECT);
  82. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  83. REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  84. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  85. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  86. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  87. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  88. }
  89. return IRQ_HANDLED;
  90. }
  91. static int hdmi_power_on_core(struct omap_hdmi *hdmi)
  92. {
  93. int r;
  94. r = regulator_enable(hdmi->vdda_reg);
  95. if (r)
  96. return r;
  97. r = hdmi_runtime_get(hdmi);
  98. if (r)
  99. goto err_runtime_get;
  100. /* Make selection of HDMI in DSS */
  101. dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
  102. hdmi->core_enabled = true;
  103. return 0;
  104. err_runtime_get:
  105. regulator_disable(hdmi->vdda_reg);
  106. return r;
  107. }
  108. static void hdmi_power_off_core(struct omap_hdmi *hdmi)
  109. {
  110. hdmi->core_enabled = false;
  111. hdmi_runtime_put(hdmi);
  112. regulator_disable(hdmi->vdda_reg);
  113. }
  114. static int hdmi_power_on_full(struct omap_hdmi *hdmi)
  115. {
  116. int r;
  117. const struct videomode *vm;
  118. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  119. unsigned int pc;
  120. r = hdmi_power_on_core(hdmi);
  121. if (r)
  122. return r;
  123. vm = &hdmi->cfg.vm;
  124. DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
  125. vm->vactive);
  126. pc = vm->pixelclock;
  127. if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
  128. pc *= 2;
  129. /* DSS_HDMI_TCLK is bitclk / 10 */
  130. pc *= 10;
  131. dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
  132. pc, &hdmi_cinfo);
  133. /* disable and clear irqs */
  134. hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
  135. hdmi_wp_set_irqstatus(&hdmi->wp,
  136. hdmi_wp_get_irqstatus(&hdmi->wp));
  137. r = dss_pll_enable(&hdmi->pll.pll);
  138. if (r) {
  139. DSSERR("Failed to enable PLL\n");
  140. goto err_pll_enable;
  141. }
  142. r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
  143. if (r) {
  144. DSSERR("Failed to configure PLL\n");
  145. goto err_pll_cfg;
  146. }
  147. r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
  148. hdmi_cinfo.clkout[0]);
  149. if (r) {
  150. DSSDBG("Failed to start PHY\n");
  151. goto err_phy_cfg;
  152. }
  153. r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);
  154. if (r)
  155. goto err_phy_pwr;
  156. hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
  157. r = dss_mgr_enable(&hdmi->output);
  158. if (r)
  159. goto err_mgr_enable;
  160. r = hdmi_wp_video_start(&hdmi->wp);
  161. if (r)
  162. goto err_vid_enable;
  163. hdmi_wp_set_irqenable(&hdmi->wp,
  164. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  165. return 0;
  166. err_vid_enable:
  167. dss_mgr_disable(&hdmi->output);
  168. err_mgr_enable:
  169. hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
  170. err_phy_pwr:
  171. err_phy_cfg:
  172. err_pll_cfg:
  173. dss_pll_disable(&hdmi->pll.pll);
  174. err_pll_enable:
  175. hdmi_power_off_core(hdmi);
  176. return -EIO;
  177. }
  178. static void hdmi_power_off_full(struct omap_hdmi *hdmi)
  179. {
  180. hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
  181. hdmi_wp_video_stop(&hdmi->wp);
  182. dss_mgr_disable(&hdmi->output);
  183. hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
  184. dss_pll_disable(&hdmi->pll.pll);
  185. hdmi_power_off_core(hdmi);
  186. }
  187. static int hdmi_dump_regs(struct seq_file *s, void *p)
  188. {
  189. struct omap_hdmi *hdmi = s->private;
  190. mutex_lock(&hdmi->lock);
  191. if (hdmi_runtime_get(hdmi)) {
  192. mutex_unlock(&hdmi->lock);
  193. return 0;
  194. }
  195. hdmi_wp_dump(&hdmi->wp, s);
  196. hdmi_pll_dump(&hdmi->pll, s);
  197. hdmi_phy_dump(&hdmi->phy, s);
  198. hdmi5_core_dump(&hdmi->core, s);
  199. hdmi_runtime_put(hdmi);
  200. mutex_unlock(&hdmi->lock);
  201. return 0;
  202. }
  203. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  204. {
  205. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  206. hdmi_wp_audio_enable(&hd->wp, true);
  207. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  208. }
  209. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  210. {
  211. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  212. hdmi_wp_audio_enable(&hd->wp, false);
  213. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  214. }
  215. static int hdmi_core_enable(struct omap_hdmi *hdmi)
  216. {
  217. int r = 0;
  218. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  219. mutex_lock(&hdmi->lock);
  220. r = hdmi_power_on_core(hdmi);
  221. if (r) {
  222. DSSERR("failed to power on device\n");
  223. goto err0;
  224. }
  225. mutex_unlock(&hdmi->lock);
  226. return 0;
  227. err0:
  228. mutex_unlock(&hdmi->lock);
  229. return r;
  230. }
  231. static void hdmi_core_disable(struct omap_hdmi *hdmi)
  232. {
  233. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  234. mutex_lock(&hdmi->lock);
  235. hdmi_power_off_core(hdmi);
  236. mutex_unlock(&hdmi->lock);
  237. }
  238. /* -----------------------------------------------------------------------------
  239. * DRM Bridge Operations
  240. */
  241. static int hdmi5_bridge_attach(struct drm_bridge *bridge,
  242. struct drm_encoder *encoder,
  243. enum drm_bridge_attach_flags flags)
  244. {
  245. struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge);
  246. if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
  247. return -EINVAL;
  248. return drm_bridge_attach(encoder, hdmi->output.next_bridge,
  249. bridge, flags);
  250. }
  251. static void hdmi5_bridge_mode_set(struct drm_bridge *bridge,
  252. const struct drm_display_mode *mode,
  253. const struct drm_display_mode *adjusted_mode)
  254. {
  255. struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge);
  256. mutex_lock(&hdmi->lock);
  257. drm_display_mode_to_videomode(adjusted_mode, &hdmi->cfg.vm);
  258. dispc_set_tv_pclk(hdmi->dss->dispc, adjusted_mode->clock * 1000);
  259. mutex_unlock(&hdmi->lock);
  260. }
  261. static void hdmi5_bridge_enable(struct drm_bridge *bridge,
  262. struct drm_atomic_state *state)
  263. {
  264. struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge);
  265. struct drm_connector_state *conn_state;
  266. struct drm_connector *connector;
  267. struct drm_crtc_state *crtc_state;
  268. unsigned long flags;
  269. int ret;
  270. /*
  271. * None of these should fail, as the bridge can't be enabled without a
  272. * valid CRTC to connector path with fully populated new states.
  273. */
  274. connector = drm_atomic_get_new_connector_for_encoder(state,
  275. bridge->encoder);
  276. if (WARN_ON(!connector))
  277. return;
  278. conn_state = drm_atomic_get_new_connector_state(state, connector);
  279. if (WARN_ON(!conn_state))
  280. return;
  281. crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
  282. if (WARN_ON(!crtc_state))
  283. return;
  284. hdmi->cfg.hdmi_dvi_mode = connector->display_info.is_hdmi
  285. ? HDMI_HDMI : HDMI_DVI;
  286. if (connector->display_info.is_hdmi) {
  287. const struct drm_display_mode *mode;
  288. struct hdmi_avi_infoframe avi;
  289. mode = &crtc_state->adjusted_mode;
  290. ret = drm_hdmi_avi_infoframe_from_display_mode(&avi, connector,
  291. mode);
  292. if (ret == 0)
  293. hdmi->cfg.infoframe = avi;
  294. }
  295. mutex_lock(&hdmi->lock);
  296. ret = hdmi_power_on_full(hdmi);
  297. if (ret) {
  298. DSSERR("failed to power on device\n");
  299. goto done;
  300. }
  301. if (hdmi->audio_configured) {
  302. ret = hdmi5_audio_config(&hdmi->core, &hdmi->wp,
  303. &hdmi->audio_config,
  304. hdmi->cfg.vm.pixelclock);
  305. if (ret) {
  306. DSSERR("Error restoring audio configuration: %d", ret);
  307. hdmi->audio_abort_cb(&hdmi->pdev->dev);
  308. hdmi->audio_configured = false;
  309. }
  310. }
  311. spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
  312. if (hdmi->audio_configured && hdmi->audio_playing)
  313. hdmi_start_audio_stream(hdmi);
  314. hdmi->display_enabled = true;
  315. spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
  316. done:
  317. mutex_unlock(&hdmi->lock);
  318. }
  319. static void hdmi5_bridge_disable(struct drm_bridge *bridge,
  320. struct drm_atomic_state *state)
  321. {
  322. struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge);
  323. unsigned long flags;
  324. mutex_lock(&hdmi->lock);
  325. spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
  326. hdmi_stop_audio_stream(hdmi);
  327. hdmi->display_enabled = false;
  328. spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
  329. hdmi_power_off_full(hdmi);
  330. mutex_unlock(&hdmi->lock);
  331. }
  332. static const struct drm_edid *hdmi5_bridge_edid_read(struct drm_bridge *bridge,
  333. struct drm_connector *connector)
  334. {
  335. struct omap_hdmi *hdmi = drm_bridge_to_hdmi(bridge);
  336. const struct drm_edid *drm_edid;
  337. bool need_enable;
  338. int idlemode;
  339. int r;
  340. need_enable = hdmi->core_enabled == false;
  341. if (need_enable) {
  342. r = hdmi_core_enable(hdmi);
  343. if (r)
  344. return NULL;
  345. }
  346. mutex_lock(&hdmi->lock);
  347. r = hdmi_runtime_get(hdmi);
  348. BUG_ON(r);
  349. idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  350. /* No-idle mode */
  351. REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  352. hdmi5_core_ddc_init(&hdmi->core);
  353. drm_edid = drm_edid_read_custom(connector, hdmi5_core_ddc_read, &hdmi->core);
  354. hdmi5_core_ddc_uninit(&hdmi->core);
  355. REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  356. hdmi_runtime_put(hdmi);
  357. mutex_unlock(&hdmi->lock);
  358. if (need_enable)
  359. hdmi_core_disable(hdmi);
  360. return drm_edid;
  361. }
  362. static const struct drm_bridge_funcs hdmi5_bridge_funcs = {
  363. .attach = hdmi5_bridge_attach,
  364. .mode_set = hdmi5_bridge_mode_set,
  365. .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
  366. .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
  367. .atomic_reset = drm_atomic_helper_bridge_reset,
  368. .atomic_enable = hdmi5_bridge_enable,
  369. .atomic_disable = hdmi5_bridge_disable,
  370. .edid_read = hdmi5_bridge_edid_read,
  371. };
  372. static void hdmi5_bridge_init(struct omap_hdmi *hdmi)
  373. {
  374. hdmi->bridge.of_node = hdmi->pdev->dev.of_node;
  375. hdmi->bridge.ops = DRM_BRIDGE_OP_EDID;
  376. hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
  377. drm_bridge_add(&hdmi->bridge);
  378. }
  379. static void hdmi5_bridge_cleanup(struct omap_hdmi *hdmi)
  380. {
  381. drm_bridge_remove(&hdmi->bridge);
  382. }
  383. /* -----------------------------------------------------------------------------
  384. * Audio Callbacks
  385. */
  386. static int hdmi_audio_startup(struct device *dev,
  387. void (*abort_cb)(struct device *dev))
  388. {
  389. struct omap_hdmi *hd = dev_get_drvdata(dev);
  390. mutex_lock(&hd->lock);
  391. WARN_ON(hd->audio_abort_cb != NULL);
  392. hd->audio_abort_cb = abort_cb;
  393. mutex_unlock(&hd->lock);
  394. return 0;
  395. }
  396. static int hdmi_audio_shutdown(struct device *dev)
  397. {
  398. struct omap_hdmi *hd = dev_get_drvdata(dev);
  399. mutex_lock(&hd->lock);
  400. hd->audio_abort_cb = NULL;
  401. hd->audio_configured = false;
  402. hd->audio_playing = false;
  403. mutex_unlock(&hd->lock);
  404. return 0;
  405. }
  406. static int hdmi_audio_start(struct device *dev)
  407. {
  408. struct omap_hdmi *hd = dev_get_drvdata(dev);
  409. unsigned long flags;
  410. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  411. if (hd->display_enabled) {
  412. if (!hdmi_mode_has_audio(&hd->cfg))
  413. DSSERR("%s: Video mode does not support audio\n",
  414. __func__);
  415. hdmi_start_audio_stream(hd);
  416. }
  417. hd->audio_playing = true;
  418. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  419. return 0;
  420. }
  421. static void hdmi_audio_stop(struct device *dev)
  422. {
  423. struct omap_hdmi *hd = dev_get_drvdata(dev);
  424. unsigned long flags;
  425. if (!hdmi_mode_has_audio(&hd->cfg))
  426. DSSERR("%s: Video mode does not support audio\n", __func__);
  427. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  428. if (hd->display_enabled)
  429. hdmi_stop_audio_stream(hd);
  430. hd->audio_playing = false;
  431. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  432. }
  433. static int hdmi_audio_config(struct device *dev,
  434. struct omap_dss_audio *dss_audio)
  435. {
  436. struct omap_hdmi *hd = dev_get_drvdata(dev);
  437. int ret = 0;
  438. mutex_lock(&hd->lock);
  439. if (hd->display_enabled) {
  440. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  441. hd->cfg.vm.pixelclock);
  442. if (ret)
  443. goto out;
  444. }
  445. hd->audio_configured = true;
  446. hd->audio_config = *dss_audio;
  447. out:
  448. mutex_unlock(&hd->lock);
  449. return ret;
  450. }
  451. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  452. .audio_startup = hdmi_audio_startup,
  453. .audio_shutdown = hdmi_audio_shutdown,
  454. .audio_start = hdmi_audio_start,
  455. .audio_stop = hdmi_audio_stop,
  456. .audio_config = hdmi_audio_config,
  457. };
  458. static int hdmi_audio_register(struct omap_hdmi *hdmi)
  459. {
  460. struct omap_hdmi_audio_pdata pdata = {
  461. .dev = &hdmi->pdev->dev,
  462. .version = 5,
  463. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
  464. .ops = &hdmi_audio_ops,
  465. };
  466. hdmi->audio_pdev = platform_device_register_data(
  467. &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  468. &pdata, sizeof(pdata));
  469. if (IS_ERR(hdmi->audio_pdev))
  470. return PTR_ERR(hdmi->audio_pdev);
  471. hdmi_runtime_get(hdmi);
  472. hdmi->wp_idlemode =
  473. REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  474. hdmi_runtime_put(hdmi);
  475. return 0;
  476. }
  477. /* -----------------------------------------------------------------------------
  478. * Component Bind & Unbind
  479. */
  480. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  481. {
  482. struct dss_device *dss = dss_get_device(master);
  483. struct omap_hdmi *hdmi = dev_get_drvdata(dev);
  484. int r;
  485. hdmi->dss = dss;
  486. r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
  487. if (r)
  488. return r;
  489. r = hdmi_audio_register(hdmi);
  490. if (r) {
  491. DSSERR("Registering HDMI audio failed %d\n", r);
  492. goto err_pll_uninit;
  493. }
  494. hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
  495. hdmi);
  496. return 0;
  497. err_pll_uninit:
  498. hdmi_pll_uninit(&hdmi->pll);
  499. return r;
  500. }
  501. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  502. {
  503. struct omap_hdmi *hdmi = dev_get_drvdata(dev);
  504. dss_debugfs_remove_file(hdmi->debugfs);
  505. if (hdmi->audio_pdev)
  506. platform_device_unregister(hdmi->audio_pdev);
  507. hdmi_pll_uninit(&hdmi->pll);
  508. }
  509. static const struct component_ops hdmi5_component_ops = {
  510. .bind = hdmi5_bind,
  511. .unbind = hdmi5_unbind,
  512. };
  513. /* -----------------------------------------------------------------------------
  514. * Probe & Remove, Suspend & Resume
  515. */
  516. static int hdmi5_init_output(struct omap_hdmi *hdmi)
  517. {
  518. struct omap_dss_device *out = &hdmi->output;
  519. int r;
  520. hdmi5_bridge_init(hdmi);
  521. out->dev = &hdmi->pdev->dev;
  522. out->id = OMAP_DSS_OUTPUT_HDMI;
  523. out->type = OMAP_DISPLAY_TYPE_HDMI;
  524. out->name = "hdmi.0";
  525. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  526. out->of_port = 0;
  527. r = omapdss_device_init_output(out, &hdmi->bridge);
  528. if (r < 0) {
  529. hdmi5_bridge_cleanup(hdmi);
  530. return r;
  531. }
  532. omapdss_device_register(out);
  533. return 0;
  534. }
  535. static void hdmi5_uninit_output(struct omap_hdmi *hdmi)
  536. {
  537. struct omap_dss_device *out = &hdmi->output;
  538. omapdss_device_unregister(out);
  539. omapdss_device_cleanup_output(out);
  540. hdmi5_bridge_cleanup(hdmi);
  541. }
  542. static int hdmi5_probe_of(struct omap_hdmi *hdmi)
  543. {
  544. struct platform_device *pdev = hdmi->pdev;
  545. struct device_node *node = pdev->dev.of_node;
  546. struct device_node *ep;
  547. int r;
  548. ep = of_graph_get_endpoint_by_regs(node, 0, 0);
  549. if (!ep)
  550. return 0;
  551. r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
  552. of_node_put(ep);
  553. return r;
  554. }
  555. static int hdmi5_probe(struct platform_device *pdev)
  556. {
  557. struct omap_hdmi *hdmi;
  558. int irq;
  559. int r;
  560. hdmi = devm_drm_bridge_alloc(&pdev->dev, struct omap_hdmi, bridge, &hdmi5_bridge_funcs);
  561. if (IS_ERR(hdmi))
  562. return PTR_ERR(hdmi);
  563. hdmi->pdev = pdev;
  564. dev_set_drvdata(&pdev->dev, hdmi);
  565. mutex_init(&hdmi->lock);
  566. spin_lock_init(&hdmi->audio_playing_lock);
  567. r = hdmi5_probe_of(hdmi);
  568. if (r)
  569. return r;
  570. r = hdmi_wp_init(pdev, &hdmi->wp, 5);
  571. if (r)
  572. return r;
  573. r = hdmi_phy_init(pdev, &hdmi->phy, 5);
  574. if (r)
  575. return r;
  576. r = hdmi5_core_init(pdev, &hdmi->core);
  577. if (r)
  578. return r;
  579. irq = platform_get_irq(pdev, 0);
  580. if (irq < 0) {
  581. DSSERR("platform_get_irq failed\n");
  582. return -ENODEV;
  583. }
  584. r = devm_request_threaded_irq(&pdev->dev, irq,
  585. NULL, hdmi_irq_handler,
  586. IRQF_ONESHOT, "OMAP HDMI", hdmi);
  587. if (r) {
  588. DSSERR("HDMI IRQ request failed\n");
  589. return r;
  590. }
  591. hdmi->vdda_reg = devm_regulator_get(&pdev->dev, "vdda");
  592. if (IS_ERR(hdmi->vdda_reg)) {
  593. r = PTR_ERR(hdmi->vdda_reg);
  594. if (r != -EPROBE_DEFER)
  595. DSSERR("can't get VDDA regulator\n");
  596. return r;
  597. }
  598. pm_runtime_enable(&pdev->dev);
  599. r = hdmi5_init_output(hdmi);
  600. if (r)
  601. goto err_pm_disable;
  602. r = component_add(&pdev->dev, &hdmi5_component_ops);
  603. if (r)
  604. goto err_uninit_output;
  605. return 0;
  606. err_uninit_output:
  607. hdmi5_uninit_output(hdmi);
  608. err_pm_disable:
  609. pm_runtime_disable(&pdev->dev);
  610. return r;
  611. }
  612. static void hdmi5_remove(struct platform_device *pdev)
  613. {
  614. struct omap_hdmi *hdmi = platform_get_drvdata(pdev);
  615. component_del(&pdev->dev, &hdmi5_component_ops);
  616. hdmi5_uninit_output(hdmi);
  617. pm_runtime_disable(&pdev->dev);
  618. }
  619. static const struct of_device_id hdmi_of_match[] = {
  620. { .compatible = "ti,omap5-hdmi", },
  621. { .compatible = "ti,dra7-hdmi", },
  622. {},
  623. };
  624. struct platform_driver omapdss_hdmi5hw_driver = {
  625. .probe = hdmi5_probe,
  626. .remove = hdmi5_remove,
  627. .driver = {
  628. .name = "omapdss_hdmi5",
  629. .of_match_table = hdmi_of_match,
  630. .suppress_bind_attrs = true,
  631. },
  632. };