hdmi_i2c.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <robdclark@gmail.com>
  5. */
  6. #include "hdmi.h"
  7. struct hdmi_i2c_adapter {
  8. struct i2c_adapter base;
  9. struct hdmi *hdmi;
  10. bool sw_done;
  11. wait_queue_head_t ddc_event;
  12. };
  13. #define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base)
  14. static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c)
  15. {
  16. struct hdmi *hdmi = hdmi_i2c->hdmi;
  17. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  18. HDMI_DDC_CTRL_SW_STATUS_RESET);
  19. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  20. HDMI_DDC_CTRL_SOFT_RESET);
  21. hdmi_write(hdmi, REG_HDMI_DDC_SPEED,
  22. HDMI_DDC_SPEED_THRESHOLD(2) |
  23. HDMI_DDC_SPEED_PRESCALE(10));
  24. hdmi_write(hdmi, REG_HDMI_DDC_SETUP,
  25. HDMI_DDC_SETUP_TIMEOUT(0xff));
  26. /* enable reference timer for 27us */
  27. hdmi_write(hdmi, REG_HDMI_DDC_REF,
  28. HDMI_DDC_REF_REFTIMER_ENABLE |
  29. HDMI_DDC_REF_REFTIMER(27));
  30. }
  31. static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c)
  32. {
  33. struct hdmi *hdmi = hdmi_i2c->hdmi;
  34. struct drm_device *dev = hdmi->dev;
  35. uint32_t retry = 0xffff;
  36. uint32_t ddc_int_ctrl;
  37. do {
  38. --retry;
  39. hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
  40. HDMI_DDC_INT_CTRL_SW_DONE_ACK |
  41. HDMI_DDC_INT_CTRL_SW_DONE_MASK);
  42. ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
  43. } while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry);
  44. if (!retry) {
  45. DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n");
  46. return -ETIMEDOUT;
  47. }
  48. hdmi_i2c->sw_done = false;
  49. return 0;
  50. }
  51. #define MAX_TRANSACTIONS 4
  52. static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
  53. {
  54. struct hdmi *hdmi = hdmi_i2c->hdmi;
  55. if (!hdmi_i2c->sw_done) {
  56. uint32_t ddc_int_ctrl;
  57. ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
  58. if ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_MASK) &&
  59. (ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT)) {
  60. hdmi_i2c->sw_done = true;
  61. hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
  62. HDMI_DDC_INT_CTRL_SW_DONE_ACK);
  63. }
  64. }
  65. return hdmi_i2c->sw_done;
  66. }
  67. static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
  68. struct i2c_msg *msgs, int num)
  69. {
  70. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  71. struct hdmi *hdmi = hdmi_i2c->hdmi;
  72. struct drm_device *dev = hdmi->dev;
  73. static const uint32_t nack[] = {
  74. HDMI_DDC_SW_STATUS_NACK0, HDMI_DDC_SW_STATUS_NACK1,
  75. HDMI_DDC_SW_STATUS_NACK2, HDMI_DDC_SW_STATUS_NACK3,
  76. };
  77. int indices[MAX_TRANSACTIONS];
  78. int ret, i, j, index = 0;
  79. uint32_t ddc_status, ddc_data, i2c_trans;
  80. num = min(num, MAX_TRANSACTIONS);
  81. WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE));
  82. if (num == 0)
  83. return num;
  84. ret = pm_runtime_resume_and_get(&hdmi->pdev->dev);
  85. if (ret)
  86. return ret;
  87. init_ddc(hdmi_i2c);
  88. ret = ddc_clear_irq(hdmi_i2c);
  89. if (ret)
  90. goto fail;
  91. for (i = 0; i < num; i++) {
  92. struct i2c_msg *p = &msgs[i];
  93. uint32_t raw_addr = p->addr << 1;
  94. if (p->flags & I2C_M_RD)
  95. raw_addr |= 1;
  96. ddc_data = HDMI_DDC_DATA_DATA(raw_addr) |
  97. HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
  98. if (i == 0) {
  99. ddc_data |= HDMI_DDC_DATA_INDEX(0) |
  100. HDMI_DDC_DATA_INDEX_WRITE;
  101. }
  102. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  103. index++;
  104. indices[i] = index;
  105. if (p->flags & I2C_M_RD) {
  106. index += p->len;
  107. } else {
  108. for (j = 0; j < p->len; j++) {
  109. ddc_data = HDMI_DDC_DATA_DATA(p->buf[j]) |
  110. HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
  111. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  112. index++;
  113. }
  114. }
  115. i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) |
  116. HDMI_I2C_TRANSACTION_REG_RW(
  117. (p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) |
  118. HDMI_I2C_TRANSACTION_REG_START;
  119. if (i == (num - 1))
  120. i2c_trans |= HDMI_I2C_TRANSACTION_REG_STOP;
  121. hdmi_write(hdmi, REG_HDMI_I2C_TRANSACTION(i), i2c_trans);
  122. }
  123. /* trigger the transfer: */
  124. hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
  125. HDMI_DDC_CTRL_TRANSACTION_CNT(num - 1) |
  126. HDMI_DDC_CTRL_GO);
  127. ret = wait_event_timeout(hdmi_i2c->ddc_event, sw_done(hdmi_i2c), HZ/4);
  128. if (ret <= 0) {
  129. if (ret == 0)
  130. ret = -ETIMEDOUT;
  131. dev_warn(dev->dev, "DDC timeout: %d\n", ret);
  132. DBG("sw_status=%08x, hw_status=%08x, int_ctrl=%08x",
  133. hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
  134. hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
  135. hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
  136. goto fail;
  137. }
  138. ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
  139. /* read back results of any read transactions: */
  140. for (i = 0; i < num; i++) {
  141. struct i2c_msg *p = &msgs[i];
  142. if (!(p->flags & I2C_M_RD))
  143. continue;
  144. /* check for NACK: */
  145. if (ddc_status & nack[i]) {
  146. DBG("ddc_status=%08x", ddc_status);
  147. break;
  148. }
  149. ddc_data = HDMI_DDC_DATA_DATA_RW(DDC_READ) |
  150. HDMI_DDC_DATA_INDEX(indices[i]) |
  151. HDMI_DDC_DATA_INDEX_WRITE;
  152. hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
  153. /* discard first byte: */
  154. hdmi_read(hdmi, REG_HDMI_DDC_DATA);
  155. for (j = 0; j < p->len; j++) {
  156. ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA);
  157. p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA);
  158. }
  159. }
  160. pm_runtime_put(&hdmi->pdev->dev);
  161. return i;
  162. fail:
  163. pm_runtime_put(&hdmi->pdev->dev);
  164. return ret;
  165. }
  166. static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
  167. {
  168. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  169. }
  170. static const struct i2c_algorithm msm_hdmi_i2c_algorithm = {
  171. .master_xfer = msm_hdmi_i2c_xfer,
  172. .functionality = msm_hdmi_i2c_func,
  173. };
  174. void msm_hdmi_i2c_irq(struct i2c_adapter *i2c)
  175. {
  176. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  177. if (sw_done(hdmi_i2c))
  178. wake_up_all(&hdmi_i2c->ddc_event);
  179. }
  180. void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c)
  181. {
  182. struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
  183. i2c_del_adapter(i2c);
  184. kfree(hdmi_i2c);
  185. }
  186. struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)
  187. {
  188. struct hdmi_i2c_adapter *hdmi_i2c;
  189. struct i2c_adapter *i2c = NULL;
  190. int ret;
  191. hdmi_i2c = kzalloc_obj(*hdmi_i2c);
  192. if (!hdmi_i2c) {
  193. ret = -ENOMEM;
  194. goto fail;
  195. }
  196. i2c = &hdmi_i2c->base;
  197. hdmi_i2c->hdmi = hdmi;
  198. init_waitqueue_head(&hdmi_i2c->ddc_event);
  199. i2c->owner = THIS_MODULE;
  200. snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
  201. i2c->dev.parent = &hdmi->pdev->dev;
  202. i2c->algo = &msm_hdmi_i2c_algorithm;
  203. ret = i2c_add_adapter(i2c);
  204. if (ret)
  205. goto fail;
  206. return i2c;
  207. fail:
  208. if (i2c)
  209. msm_hdmi_i2c_destroy(i2c);
  210. return ERR_PTR(ret);
  211. }