dpu_trace.h 28 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
  3. */
  4. #if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
  5. #define _DPU_TRACE_H_
  6. #include <linux/stringify.h>
  7. #include <linux/types.h>
  8. #include <linux/tracepoint.h>
  9. #include <drm/drm_rect.h>
  10. #include "dpu_crtc.h"
  11. #include "dpu_encoder_phys.h"
  12. #include "dpu_hw_mdss.h"
  13. #include "dpu_hw_vbif.h"
  14. #include "dpu_plane.h"
  15. #undef TRACE_SYSTEM
  16. #define TRACE_SYSTEM dpu
  17. #undef TRACE_INCLUDE_FILE
  18. #define TRACE_INCLUDE_FILE dpu_trace
  19. TRACE_EVENT(dpu_perf_set_qos_luts,
  20. TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
  21. u32 lut, u32 lut_usage),
  22. TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
  23. TP_STRUCT__entry(
  24. __field(u32, pnum)
  25. __field(u32, fmt)
  26. __field(bool, rt)
  27. __field(u32, fl)
  28. __field(u64, lut)
  29. __field(u32, lut_usage)
  30. ),
  31. TP_fast_assign(
  32. __entry->pnum = pnum;
  33. __entry->fmt = fmt;
  34. __entry->rt = rt;
  35. __entry->fl = fl;
  36. __entry->lut = lut;
  37. __entry->lut_usage = lut_usage;
  38. ),
  39. TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
  40. __entry->pnum, __entry->fmt,
  41. __entry->rt, __entry->fl,
  42. __entry->lut, __entry->lut_usage)
  43. );
  44. TRACE_EVENT(dpu_perf_set_danger_luts,
  45. TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
  46. u32 safe_lut),
  47. TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
  48. TP_STRUCT__entry(
  49. __field(u32, pnum)
  50. __field(u32, fmt)
  51. __field(u32, mode)
  52. __field(u32, danger_lut)
  53. __field(u32, safe_lut)
  54. ),
  55. TP_fast_assign(
  56. __entry->pnum = pnum;
  57. __entry->fmt = fmt;
  58. __entry->mode = mode;
  59. __entry->danger_lut = danger_lut;
  60. __entry->safe_lut = safe_lut;
  61. ),
  62. TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
  63. __entry->pnum, __entry->fmt,
  64. __entry->mode, __entry->danger_lut,
  65. __entry->safe_lut)
  66. );
  67. TRACE_EVENT(dpu_perf_set_ot,
  68. TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
  69. TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
  70. TP_STRUCT__entry(
  71. __field(u32, pnum)
  72. __field(u32, xin_id)
  73. __field(u32, rd_lim)
  74. __field(u32, vbif_idx)
  75. ),
  76. TP_fast_assign(
  77. __entry->pnum = pnum;
  78. __entry->xin_id = xin_id;
  79. __entry->rd_lim = rd_lim;
  80. __entry->vbif_idx = vbif_idx;
  81. ),
  82. TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
  83. __entry->pnum, __entry->xin_id, __entry->rd_lim,
  84. __entry->vbif_idx)
  85. )
  86. TRACE_EVENT(dpu_cmd_release_bw,
  87. TP_PROTO(u32 crtc_id),
  88. TP_ARGS(crtc_id),
  89. TP_STRUCT__entry(
  90. __field(u32, crtc_id)
  91. ),
  92. TP_fast_assign(
  93. __entry->crtc_id = crtc_id;
  94. ),
  95. TP_printk("crtc:%d", __entry->crtc_id)
  96. );
  97. TRACE_EVENT(tracing_mark_write,
  98. TP_PROTO(int pid, const char *name, bool trace_begin),
  99. TP_ARGS(pid, name, trace_begin),
  100. TP_STRUCT__entry(
  101. __field(int, pid)
  102. __string(trace_name, name)
  103. __field(bool, trace_begin)
  104. ),
  105. TP_fast_assign(
  106. __entry->pid = pid;
  107. __assign_str(trace_name);
  108. __entry->trace_begin = trace_begin;
  109. ),
  110. TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
  111. __entry->pid, __get_str(trace_name))
  112. )
  113. TRACE_EVENT(dpu_trace_counter,
  114. TP_PROTO(int pid, char *name, int value),
  115. TP_ARGS(pid, name, value),
  116. TP_STRUCT__entry(
  117. __field(int, pid)
  118. __string(counter_name, name)
  119. __field(int, value)
  120. ),
  121. TP_fast_assign(
  122. __entry->pid = current->tgid;
  123. __assign_str(counter_name);
  124. __entry->value = value;
  125. ),
  126. TP_printk("%d|%s|%d", __entry->pid,
  127. __get_str(counter_name), __entry->value)
  128. )
  129. TRACE_EVENT(dpu_perf_crtc_update,
  130. TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate,
  131. bool stop_req, bool update_bus, bool update_clk),
  132. TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk),
  133. TP_STRUCT__entry(
  134. __field(u32, crtc)
  135. __field(u64, bw_ctl)
  136. __field(u32, core_clk_rate)
  137. __field(bool, stop_req)
  138. __field(u32, update_bus)
  139. __field(u32, update_clk)
  140. ),
  141. TP_fast_assign(
  142. __entry->crtc = crtc;
  143. __entry->bw_ctl = bw_ctl;
  144. __entry->core_clk_rate = core_clk_rate;
  145. __entry->stop_req = stop_req;
  146. __entry->update_bus = update_bus;
  147. __entry->update_clk = update_clk;
  148. ),
  149. TP_printk(
  150. "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
  151. __entry->crtc,
  152. __entry->bw_ctl,
  153. __entry->core_clk_rate,
  154. __entry->stop_req,
  155. __entry->update_bus,
  156. __entry->update_clk)
  157. );
  158. DECLARE_EVENT_CLASS(dpu_irq_template,
  159. TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
  160. TP_ARGS(irq_reg, irq_bit),
  161. TP_STRUCT__entry(
  162. __field( unsigned int, irq_reg )
  163. __field( unsigned int, irq_bit )
  164. ),
  165. TP_fast_assign(
  166. __entry->irq_reg = irq_reg;
  167. __entry->irq_bit = irq_bit;
  168. ),
  169. TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
  170. );
  171. DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success,
  172. TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
  173. TP_ARGS(irq_reg, irq_bit)
  174. );
  175. DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success,
  176. TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
  177. TP_ARGS(irq_reg, irq_bit)
  178. );
  179. TRACE_EVENT(dpu_enc_irq_wait_success,
  180. TP_PROTO(uint32_t drm_id, void *func,
  181. unsigned int irq_reg, unsigned int irq_bit, enum dpu_pingpong pp_idx, int atomic_cnt),
  182. TP_ARGS(drm_id, func, irq_reg, irq_bit, pp_idx, atomic_cnt),
  183. TP_STRUCT__entry(
  184. __field( uint32_t, drm_id )
  185. __field( void *, func )
  186. __field( unsigned int, irq_reg )
  187. __field( unsigned int, irq_bit )
  188. __field( enum dpu_pingpong, pp_idx )
  189. __field( int, atomic_cnt )
  190. ),
  191. TP_fast_assign(
  192. __entry->drm_id = drm_id;
  193. __entry->func = func;
  194. __entry->irq_reg = irq_reg;
  195. __entry->irq_bit = irq_bit;
  196. __entry->pp_idx = pp_idx;
  197. __entry->atomic_cnt = atomic_cnt;
  198. ),
  199. TP_printk("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d",
  200. __entry->drm_id, __entry->func,
  201. __entry->irq_reg, __entry->irq_bit, __entry->pp_idx, __entry->atomic_cnt)
  202. );
  203. DECLARE_EVENT_CLASS(dpu_drm_obj_template,
  204. TP_PROTO(uint32_t drm_id),
  205. TP_ARGS(drm_id),
  206. TP_STRUCT__entry(
  207. __field( uint32_t, drm_id )
  208. ),
  209. TP_fast_assign(
  210. __entry->drm_id = drm_id;
  211. ),
  212. TP_printk("id=%u", __entry->drm_id)
  213. );
  214. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
  215. TP_PROTO(uint32_t drm_id),
  216. TP_ARGS(drm_id)
  217. );
  218. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
  219. TP_PROTO(uint32_t drm_id),
  220. TP_ARGS(drm_id)
  221. );
  222. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
  223. TP_PROTO(uint32_t drm_id),
  224. TP_ARGS(drm_id)
  225. );
  226. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
  227. TP_PROTO(uint32_t drm_id),
  228. TP_ARGS(drm_id)
  229. );
  230. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
  231. TP_PROTO(uint32_t drm_id),
  232. TP_ARGS(drm_id)
  233. );
  234. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
  235. TP_PROTO(uint32_t drm_id),
  236. TP_ARGS(drm_id)
  237. );
  238. DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
  239. TP_PROTO(uint32_t drm_id),
  240. TP_ARGS(drm_id)
  241. );
  242. DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
  243. TP_PROTO(uint32_t drm_id),
  244. TP_ARGS(drm_id)
  245. );
  246. DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
  247. TP_PROTO(uint32_t drm_id),
  248. TP_ARGS(drm_id)
  249. );
  250. DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
  251. TP_PROTO(uint32_t drm_id),
  252. TP_ARGS(drm_id)
  253. );
  254. DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
  255. TP_PROTO(uint32_t drm_id),
  256. TP_ARGS(drm_id)
  257. );
  258. DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
  259. TP_PROTO(uint32_t drm_id),
  260. TP_ARGS(drm_id)
  261. );
  262. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_enable,
  263. TP_PROTO(uint32_t drm_id),
  264. TP_ARGS(drm_id)
  265. );
  266. DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_disable,
  267. TP_PROTO(uint32_t drm_id),
  268. TP_ARGS(drm_id)
  269. );
  270. TRACE_EVENT(dpu_enc_enable,
  271. TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
  272. TP_ARGS(drm_id, hdisplay, vdisplay),
  273. TP_STRUCT__entry(
  274. __field( uint32_t, drm_id )
  275. __field( int, hdisplay )
  276. __field( int, vdisplay )
  277. ),
  278. TP_fast_assign(
  279. __entry->drm_id = drm_id;
  280. __entry->hdisplay = hdisplay;
  281. __entry->vdisplay = vdisplay;
  282. ),
  283. TP_printk("id=%u, mode=%dx%d",
  284. __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
  285. );
  286. DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
  287. TP_PROTO(uint32_t drm_id, int val),
  288. TP_ARGS(drm_id, val),
  289. TP_STRUCT__entry(
  290. __field( uint32_t, drm_id )
  291. __field( int, val )
  292. ),
  293. TP_fast_assign(
  294. __entry->drm_id = drm_id;
  295. __entry->val = val;
  296. ),
  297. TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
  298. );
  299. DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
  300. TP_PROTO(uint32_t drm_id, int count),
  301. TP_ARGS(drm_id, count)
  302. );
  303. DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
  304. TP_PROTO(uint32_t drm_id, int ctl_idx),
  305. TP_ARGS(drm_id, ctl_idx)
  306. );
  307. TRACE_EVENT(dpu_enc_atomic_check_flags,
  308. TP_PROTO(uint32_t drm_id, unsigned int flags),
  309. TP_ARGS(drm_id, flags),
  310. TP_STRUCT__entry(
  311. __field( uint32_t, drm_id )
  312. __field( unsigned int, flags )
  313. ),
  314. TP_fast_assign(
  315. __entry->drm_id = drm_id;
  316. __entry->flags = flags;
  317. ),
  318. TP_printk("id=%u, flags=%u",
  319. __entry->drm_id, __entry->flags)
  320. );
  321. DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
  322. TP_PROTO(uint32_t drm_id, bool enable),
  323. TP_ARGS(drm_id, enable),
  324. TP_STRUCT__entry(
  325. __field( uint32_t, drm_id )
  326. __field( bool, enable )
  327. ),
  328. TP_fast_assign(
  329. __entry->drm_id = drm_id;
  330. __entry->enable = enable;
  331. ),
  332. TP_printk("id=%u, enable=%s",
  333. __entry->drm_id, __entry->enable ? "true" : "false")
  334. );
  335. DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
  336. TP_PROTO(uint32_t drm_id, bool enable),
  337. TP_ARGS(drm_id, enable)
  338. );
  339. DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
  340. TP_PROTO(uint32_t drm_id, bool enable),
  341. TP_ARGS(drm_id, enable)
  342. );
  343. TRACE_EVENT(dpu_enc_rc,
  344. TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
  345. int rc_state, const char *stage),
  346. TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
  347. TP_STRUCT__entry(
  348. __field( uint32_t, drm_id )
  349. __field( u32, sw_event )
  350. __field( bool, idle_pc_supported )
  351. __field( int, rc_state )
  352. __string( stage_str, stage )
  353. ),
  354. TP_fast_assign(
  355. __entry->drm_id = drm_id;
  356. __entry->sw_event = sw_event;
  357. __entry->idle_pc_supported = idle_pc_supported;
  358. __entry->rc_state = rc_state;
  359. __assign_str(stage_str);
  360. ),
  361. TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d",
  362. __get_str(stage_str), __entry->drm_id, __entry->sw_event,
  363. __entry->idle_pc_supported ? "true" : "false",
  364. __entry->rc_state)
  365. );
  366. TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
  367. TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf intf_idx,
  368. enum dpu_wb wb_idx),
  369. TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx),
  370. TP_STRUCT__entry(
  371. __field( uint32_t, drm_id )
  372. __field( u32, event )
  373. __string( intf_mode_str, intf_mode )
  374. __field( enum dpu_intf, intf_idx )
  375. __field( enum dpu_wb, wb_idx )
  376. ),
  377. TP_fast_assign(
  378. __entry->drm_id = drm_id;
  379. __entry->event = event;
  380. __assign_str(intf_mode_str);
  381. __entry->intf_idx = intf_idx;
  382. __entry->wb_idx = wb_idx;
  383. ),
  384. TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", __entry->drm_id,
  385. __entry->event, __get_str(intf_mode_str),
  386. __entry->intf_idx, __entry->wb_idx)
  387. );
  388. TRACE_EVENT(dpu_enc_frame_done_cb,
  389. TP_PROTO(uint32_t drm_id, unsigned int idx,
  390. unsigned long frame_busy_mask),
  391. TP_ARGS(drm_id, idx, frame_busy_mask),
  392. TP_STRUCT__entry(
  393. __field( uint32_t, drm_id )
  394. __field( unsigned int, idx )
  395. __field( unsigned long, frame_busy_mask )
  396. ),
  397. TP_fast_assign(
  398. __entry->drm_id = drm_id;
  399. __entry->idx = idx;
  400. __entry->frame_busy_mask = frame_busy_mask;
  401. ),
  402. TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
  403. __entry->idx, __entry->frame_busy_mask)
  404. );
  405. TRACE_EVENT(dpu_enc_trigger_flush,
  406. TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum dpu_wb wb_idx,
  407. int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
  408. u32 pending_flush_ret),
  409. TP_ARGS(drm_id, intf_mode, intf_idx, wb_idx, pending_kickoff_cnt, ctl_idx,
  410. extra_flush_bits, pending_flush_ret),
  411. TP_STRUCT__entry(
  412. __field( uint32_t, drm_id )
  413. __string( intf_mode_str, intf_mode )
  414. __field( enum dpu_intf, intf_idx )
  415. __field( enum dpu_wb, wb_idx )
  416. __field( int, pending_kickoff_cnt )
  417. __field( int, ctl_idx )
  418. __field( u32, extra_flush_bits )
  419. __field( u32, pending_flush_ret )
  420. ),
  421. TP_fast_assign(
  422. __entry->drm_id = drm_id;
  423. __assign_str(intf_mode_str);
  424. __entry->intf_idx = intf_idx;
  425. __entry->wb_idx = wb_idx;
  426. __entry->pending_kickoff_cnt = pending_kickoff_cnt;
  427. __entry->ctl_idx = ctl_idx;
  428. __entry->extra_flush_bits = extra_flush_bits;
  429. __entry->pending_flush_ret = pending_flush_ret;
  430. ),
  431. TP_printk("id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
  432. "extra_flush_bits=0x%x pending_flush_ret=0x%x",
  433. __entry->drm_id, __get_str(intf_mode_str), __entry->intf_idx, __entry->wb_idx,
  434. __entry->pending_kickoff_cnt, __entry->ctl_idx,
  435. __entry->extra_flush_bits, __entry->pending_flush_ret)
  436. );
  437. DECLARE_EVENT_CLASS(dpu_id_event_template,
  438. TP_PROTO(uint32_t drm_id, u32 event),
  439. TP_ARGS(drm_id, event),
  440. TP_STRUCT__entry(
  441. __field( uint32_t, drm_id )
  442. __field( u32, event )
  443. ),
  444. TP_fast_assign(
  445. __entry->drm_id = drm_id;
  446. __entry->event = event;
  447. ),
  448. TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
  449. );
  450. DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
  451. TP_PROTO(uint32_t drm_id, u32 event),
  452. TP_ARGS(drm_id, event)
  453. );
  454. DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
  455. TP_PROTO(uint32_t drm_id, u32 event),
  456. TP_ARGS(drm_id, event)
  457. );
  458. DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
  459. TP_PROTO(uint32_t drm_id, u32 event),
  460. TP_ARGS(drm_id, event)
  461. );
  462. DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
  463. TP_PROTO(uint32_t drm_id, u32 event),
  464. TP_ARGS(drm_id, event)
  465. );
  466. TRACE_EVENT(dpu_enc_wait_event_timeout,
  467. TP_PROTO(uint32_t drm_id, unsigned int irq_reg, unsigned int irq_bit, int rc, s64 time,
  468. s64 expected_time, int atomic_cnt),
  469. TP_ARGS(drm_id, irq_reg, irq_bit, rc, time, expected_time, atomic_cnt),
  470. TP_STRUCT__entry(
  471. __field( uint32_t, drm_id )
  472. __field( unsigned int, irq_reg )
  473. __field( unsigned int, irq_bit )
  474. __field( int, rc )
  475. __field( s64, time )
  476. __field( s64, expected_time )
  477. __field( int, atomic_cnt )
  478. ),
  479. TP_fast_assign(
  480. __entry->drm_id = drm_id;
  481. __entry->irq_reg = irq_reg;
  482. __entry->irq_bit = irq_bit;
  483. __entry->rc = rc;
  484. __entry->time = time;
  485. __entry->expected_time = expected_time;
  486. __entry->atomic_cnt = atomic_cnt;
  487. ),
  488. TP_printk("id=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d",
  489. __entry->drm_id, __entry->irq_reg, __entry->irq_bit, __entry->rc, __entry->time,
  490. __entry->expected_time, __entry->atomic_cnt)
  491. );
  492. TRACE_EVENT(dpu_enc_phys_cmd_irq_enable,
  493. TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp,
  494. int refcnt),
  495. TP_ARGS(drm_id, pp, refcnt),
  496. TP_STRUCT__entry(
  497. __field( uint32_t, drm_id )
  498. __field( enum dpu_pingpong, pp )
  499. __field( int, refcnt )
  500. ),
  501. TP_fast_assign(
  502. __entry->drm_id = drm_id;
  503. __entry->pp = pp;
  504. __entry->refcnt = refcnt;
  505. ),
  506. TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id,
  507. __entry->pp,
  508. __entry->refcnt)
  509. );
  510. TRACE_EVENT(dpu_enc_phys_cmd_irq_disable,
  511. TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp,
  512. int refcnt),
  513. TP_ARGS(drm_id, pp, refcnt),
  514. TP_STRUCT__entry(
  515. __field( uint32_t, drm_id )
  516. __field( enum dpu_pingpong, pp )
  517. __field( int, refcnt )
  518. ),
  519. TP_fast_assign(
  520. __entry->drm_id = drm_id;
  521. __entry->pp = pp;
  522. __entry->refcnt = refcnt;
  523. ),
  524. TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id,
  525. __entry->pp,
  526. __entry->refcnt)
  527. );
  528. TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
  529. TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
  530. u32 event),
  531. TP_ARGS(drm_id, pp, new_count, event),
  532. TP_STRUCT__entry(
  533. __field( uint32_t, drm_id )
  534. __field( enum dpu_pingpong, pp )
  535. __field( int, new_count )
  536. __field( u32, event )
  537. ),
  538. TP_fast_assign(
  539. __entry->drm_id = drm_id;
  540. __entry->pp = pp;
  541. __entry->new_count = new_count;
  542. __entry->event = event;
  543. ),
  544. TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
  545. __entry->pp, __entry->new_count, __entry->event)
  546. );
  547. TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
  548. TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
  549. int kickoff_count, u32 event),
  550. TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
  551. TP_STRUCT__entry(
  552. __field( uint32_t, drm_id )
  553. __field( enum dpu_pingpong, pp )
  554. __field( int, timeout_count )
  555. __field( int, kickoff_count )
  556. __field( u32, event )
  557. ),
  558. TP_fast_assign(
  559. __entry->drm_id = drm_id;
  560. __entry->pp = pp;
  561. __entry->timeout_count = timeout_count;
  562. __entry->kickoff_count = kickoff_count;
  563. __entry->event = event;
  564. ),
  565. TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
  566. __entry->drm_id, __entry->pp, __entry->timeout_count,
  567. __entry->kickoff_count, __entry->event)
  568. );
  569. TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
  570. TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
  571. TP_ARGS(drm_id, intf_idx),
  572. TP_STRUCT__entry(
  573. __field( uint32_t, drm_id )
  574. __field( enum dpu_intf, intf_idx )
  575. ),
  576. TP_fast_assign(
  577. __entry->drm_id = drm_id;
  578. __entry->intf_idx = intf_idx;
  579. ),
  580. TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
  581. );
  582. TRACE_EVENT(dpu_enc_phys_vid_irq_enable,
  583. TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
  584. int refcnt),
  585. TP_ARGS(drm_id, intf_idx, refcnt),
  586. TP_STRUCT__entry(
  587. __field( uint32_t, drm_id )
  588. __field( enum dpu_intf, intf_idx )
  589. __field( int, refcnt )
  590. ),
  591. TP_fast_assign(
  592. __entry->drm_id = drm_id;
  593. __entry->intf_idx = intf_idx;
  594. __entry->refcnt = refcnt;
  595. ),
  596. TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id,
  597. __entry->intf_idx,
  598. __entry->drm_id)
  599. );
  600. TRACE_EVENT(dpu_enc_phys_vid_irq_disable,
  601. TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
  602. int refcnt),
  603. TP_ARGS(drm_id, intf_idx, refcnt),
  604. TP_STRUCT__entry(
  605. __field( uint32_t, drm_id )
  606. __field( enum dpu_intf, intf_idx )
  607. __field( int, refcnt )
  608. ),
  609. TP_fast_assign(
  610. __entry->drm_id = drm_id;
  611. __entry->intf_idx = intf_idx;
  612. __entry->refcnt = refcnt;
  613. ),
  614. TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id,
  615. __entry->intf_idx,
  616. __entry->drm_id)
  617. );
  618. TRACE_EVENT(dpu_crtc_setup_mixer,
  619. TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
  620. struct drm_plane_state *state, struct dpu_plane_state *pstate,
  621. uint32_t stage_idx, uint32_t pixel_format,
  622. struct dpu_sw_pipe *pipe, uint64_t modifier),
  623. TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx,
  624. pixel_format, pipe, modifier),
  625. TP_STRUCT__entry(
  626. __field( uint32_t, crtc_id )
  627. __field( uint32_t, plane_id )
  628. __field( uint32_t, fb_id )
  629. __field_struct( struct drm_rect, src_rect )
  630. __field_struct( struct drm_rect, dst_rect )
  631. __field( uint32_t, stage_idx )
  632. __field( enum dpu_stage, stage )
  633. __field( enum dpu_sspp, sspp )
  634. __field( uint32_t, multirect_idx )
  635. __field( uint32_t, multirect_mode )
  636. __field( uint32_t, pixel_format )
  637. __field( uint64_t, modifier )
  638. ),
  639. TP_fast_assign(
  640. __entry->crtc_id = crtc_id;
  641. __entry->plane_id = plane_id;
  642. __entry->fb_id = state ? state->fb->base.id : 0;
  643. __entry->src_rect = drm_plane_state_src(state);
  644. __entry->dst_rect = drm_plane_state_dest(state);
  645. __entry->stage_idx = stage_idx;
  646. __entry->stage = pstate->stage;
  647. __entry->sspp = pipe->sspp->idx;
  648. __entry->multirect_idx = pipe->multirect_index;
  649. __entry->multirect_mode = pipe->multirect_mode;
  650. __entry->pixel_format = pixel_format;
  651. __entry->modifier = modifier;
  652. ),
  653. TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
  654. " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
  655. "multirect_index:%d multirect_mode:%u pix_format:%u "
  656. "modifier:%llu",
  657. __entry->crtc_id, __entry->plane_id, __entry->fb_id,
  658. DRM_RECT_FP_ARG(&__entry->src_rect),
  659. DRM_RECT_ARG(&__entry->dst_rect),
  660. __entry->stage_idx, __entry->stage, __entry->sspp,
  661. __entry->multirect_idx, __entry->multirect_mode,
  662. __entry->pixel_format, __entry->modifier)
  663. );
  664. TRACE_EVENT(dpu_crtc_setup_lm_bounds,
  665. TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
  666. TP_ARGS(drm_id, mixer, bounds),
  667. TP_STRUCT__entry(
  668. __field( uint32_t, drm_id )
  669. __field( int, mixer )
  670. __field_struct( struct drm_rect, bounds )
  671. ),
  672. TP_fast_assign(
  673. __entry->drm_id = drm_id;
  674. __entry->mixer = mixer;
  675. __entry->bounds = *bounds;
  676. ),
  677. TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
  678. __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
  679. );
  680. TRACE_EVENT(dpu_crtc_vblank_enable,
  681. TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
  682. struct dpu_crtc *crtc),
  683. TP_ARGS(drm_id, enc_id, enable, crtc),
  684. TP_STRUCT__entry(
  685. __field( uint32_t, drm_id )
  686. __field( uint32_t, enc_id )
  687. __field( bool, enable )
  688. __field( bool, enabled )
  689. ),
  690. TP_fast_assign(
  691. __entry->drm_id = drm_id;
  692. __entry->enc_id = enc_id;
  693. __entry->enable = enable;
  694. __entry->enabled = crtc->enabled;
  695. ),
  696. TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
  697. __entry->drm_id, __entry->enc_id,
  698. __entry->enable ? "true" : "false",
  699. __entry->enabled ? "true" : "false")
  700. );
  701. DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
  702. TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
  703. TP_ARGS(drm_id, enable, crtc),
  704. TP_STRUCT__entry(
  705. __field( uint32_t, drm_id )
  706. __field( bool, enable )
  707. __field( bool, enabled )
  708. ),
  709. TP_fast_assign(
  710. __entry->drm_id = drm_id;
  711. __entry->enable = enable;
  712. __entry->enabled = crtc->enabled;
  713. ),
  714. TP_printk("id:%u enable:%s state{enabled:%s}",
  715. __entry->drm_id, __entry->enable ? "true" : "false",
  716. __entry->enabled ? "true" : "false")
  717. );
  718. DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
  719. TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
  720. TP_ARGS(drm_id, enable, crtc)
  721. );
  722. DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
  723. TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
  724. TP_ARGS(drm_id, enable, crtc)
  725. );
  726. DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
  727. TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
  728. TP_ARGS(drm_id, enable, crtc)
  729. );
  730. TRACE_EVENT(dpu_crtc_disable_frame_pending,
  731. TP_PROTO(uint32_t drm_id, int frame_pending),
  732. TP_ARGS(drm_id, frame_pending),
  733. TP_STRUCT__entry(
  734. __field( uint32_t, drm_id )
  735. __field( int, frame_pending )
  736. ),
  737. TP_fast_assign(
  738. __entry->drm_id = drm_id;
  739. __entry->frame_pending = frame_pending;
  740. ),
  741. TP_printk("id:%u frame_pending:%d", __entry->drm_id,
  742. __entry->frame_pending)
  743. );
  744. TRACE_EVENT(dpu_plane_set_scanout,
  745. TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout),
  746. TP_ARGS(pipe, layout),
  747. TP_STRUCT__entry(
  748. __field( enum dpu_sspp, index )
  749. __field_struct( struct dpu_hw_fmt_layout, layout )
  750. __field( enum dpu_sspp_multirect_index, multirect_index)
  751. ),
  752. TP_fast_assign(
  753. __entry->index = pipe->sspp->idx;
  754. __entry->layout = *layout;
  755. __entry->multirect_index = pipe->multirect_index;
  756. ),
  757. TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
  758. "multirect_index:%d", __entry->index, __entry->layout.width,
  759. __entry->layout.height, __entry->layout.plane_addr[0],
  760. __entry->layout.plane_size[0],
  761. __entry->layout.plane_addr[1],
  762. __entry->layout.plane_size[1],
  763. __entry->layout.plane_addr[2],
  764. __entry->layout.plane_size[2],
  765. __entry->layout.plane_addr[3],
  766. __entry->layout.plane_size[3], __entry->multirect_index)
  767. );
  768. TRACE_EVENT(dpu_plane_disable,
  769. TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
  770. TP_ARGS(drm_id, is_virtual, multirect_mode),
  771. TP_STRUCT__entry(
  772. __field( uint32_t, drm_id )
  773. __field( bool, is_virtual )
  774. __field( uint32_t, multirect_mode )
  775. ),
  776. TP_fast_assign(
  777. __entry->drm_id = drm_id;
  778. __entry->is_virtual = is_virtual;
  779. __entry->multirect_mode = multirect_mode;
  780. ),
  781. TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
  782. __entry->is_virtual ? "true" : "false",
  783. __entry->multirect_mode)
  784. );
  785. DECLARE_EVENT_CLASS(dpu_rm_iter_template,
  786. TP_PROTO(uint32_t id, uint32_t enc_id),
  787. TP_ARGS(id, enc_id),
  788. TP_STRUCT__entry(
  789. __field( uint32_t, id )
  790. __field( uint32_t, enc_id )
  791. ),
  792. TP_fast_assign(
  793. __entry->id = id;
  794. __entry->enc_id = enc_id;
  795. ),
  796. TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
  797. );
  798. DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
  799. TP_PROTO(uint32_t id, uint32_t enc_id),
  800. TP_ARGS(id, enc_id)
  801. );
  802. DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
  803. TP_PROTO(uint32_t id, uint32_t enc_id),
  804. TP_ARGS(id, enc_id)
  805. );
  806. TRACE_EVENT(dpu_rm_reserve_lms,
  807. TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
  808. TP_ARGS(id, enc_id, pp_id),
  809. TP_STRUCT__entry(
  810. __field( uint32_t, id )
  811. __field( uint32_t, enc_id )
  812. __field( uint32_t, pp_id )
  813. ),
  814. TP_fast_assign(
  815. __entry->id = id;
  816. __entry->enc_id = enc_id;
  817. __entry->pp_id = pp_id;
  818. ),
  819. TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
  820. __entry->enc_id, __entry->pp_id)
  821. );
  822. TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
  823. TP_PROTO(enum dpu_vbif index, u32 xin_id),
  824. TP_ARGS(index, xin_id),
  825. TP_STRUCT__entry(
  826. __field( enum dpu_vbif, index )
  827. __field( u32, xin_id )
  828. ),
  829. TP_fast_assign(
  830. __entry->index = index;
  831. __entry->xin_id = xin_id;
  832. ),
  833. TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
  834. );
  835. TRACE_EVENT(dpu_pp_connect_ext_te,
  836. TP_PROTO(enum dpu_pingpong pp, u32 cfg),
  837. TP_ARGS(pp, cfg),
  838. TP_STRUCT__entry(
  839. __field( enum dpu_pingpong, pp )
  840. __field( u32, cfg )
  841. ),
  842. TP_fast_assign(
  843. __entry->pp = pp;
  844. __entry->cfg = cfg;
  845. ),
  846. TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
  847. );
  848. TRACE_EVENT(dpu_intf_connect_ext_te,
  849. TP_PROTO(enum dpu_intf intf, u32 cfg),
  850. TP_ARGS(intf, cfg),
  851. TP_STRUCT__entry(
  852. __field( enum dpu_intf, intf )
  853. __field( u32, cfg )
  854. ),
  855. TP_fast_assign(
  856. __entry->intf = intf;
  857. __entry->cfg = cfg;
  858. ),
  859. TP_printk("intf:%d cfg:%u", __entry->intf, __entry->cfg)
  860. );
  861. TRACE_EVENT(dpu_core_irq_register_callback,
  862. TP_PROTO(unsigned int irq_reg, unsigned int irq_bit, void *callback),
  863. TP_ARGS(irq_reg, irq_bit, callback),
  864. TP_STRUCT__entry(
  865. __field( unsigned int, irq_reg )
  866. __field( unsigned int, irq_bit )
  867. __field( void *, callback)
  868. ),
  869. TP_fast_assign(
  870. __entry->irq_reg = irq_reg;
  871. __entry->irq_bit = irq_bit;
  872. __entry->callback = callback;
  873. ),
  874. TP_printk("IRQ=[%d, %d] callback:%ps", __entry->irq_reg, __entry->irq_bit,
  875. __entry->callback)
  876. );
  877. TRACE_EVENT(dpu_core_irq_unregister_callback,
  878. TP_PROTO(unsigned int irq_reg, unsigned int irq_bit),
  879. TP_ARGS(irq_reg, irq_bit),
  880. TP_STRUCT__entry(
  881. __field( unsigned int, irq_reg )
  882. __field( unsigned int, irq_bit )
  883. ),
  884. TP_fast_assign(
  885. __entry->irq_reg = irq_reg;
  886. __entry->irq_bit = irq_bit;
  887. ),
  888. TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit)
  889. );
  890. TRACE_EVENT(dpu_core_perf_update_clk,
  891. TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
  892. TP_ARGS(dev, stop_req, clk_rate),
  893. TP_STRUCT__entry(
  894. __string( dev_name, dev->unique )
  895. __field( bool, stop_req )
  896. __field( u64, clk_rate )
  897. ),
  898. TP_fast_assign(
  899. __assign_str(dev_name);
  900. __entry->stop_req = stop_req;
  901. __entry->clk_rate = clk_rate;
  902. ),
  903. TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
  904. __entry->stop_req ? "true" : "false", __entry->clk_rate)
  905. );
  906. TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
  907. TP_PROTO(u32 new_bits, u32 pending_mask),
  908. TP_ARGS(new_bits, pending_mask),
  909. TP_STRUCT__entry(
  910. __field( u32, new_bits )
  911. __field( u32, pending_mask )
  912. ),
  913. TP_fast_assign(
  914. __entry->new_bits = new_bits;
  915. __entry->pending_mask = pending_mask;
  916. ),
  917. TP_printk("new=%x existing=%x", __entry->new_bits,
  918. __entry->pending_mask)
  919. );
  920. DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
  921. TP_PROTO(u32 pending_mask, u32 ctl_flush),
  922. TP_ARGS(pending_mask, ctl_flush),
  923. TP_STRUCT__entry(
  924. __field( u32, pending_mask )
  925. __field( u32, ctl_flush )
  926. ),
  927. TP_fast_assign(
  928. __entry->pending_mask = pending_mask;
  929. __entry->ctl_flush = ctl_flush;
  930. ),
  931. TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
  932. __entry->ctl_flush)
  933. );
  934. DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
  935. TP_PROTO(u32 pending_mask, u32 ctl_flush),
  936. TP_ARGS(pending_mask, ctl_flush)
  937. );
  938. DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
  939. dpu_hw_ctl_trigger_pending_flush,
  940. TP_PROTO(u32 pending_mask, u32 ctl_flush),
  941. TP_ARGS(pending_mask, ctl_flush)
  942. );
  943. DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
  944. TP_PROTO(u32 pending_mask, u32 ctl_flush),
  945. TP_ARGS(pending_mask, ctl_flush)
  946. );
  947. DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
  948. TP_PROTO(u32 pending_mask, u32 ctl_flush),
  949. TP_ARGS(pending_mask, ctl_flush)
  950. );
  951. #define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
  952. #define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
  953. #define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
  954. #define DPU_ATRACE_INT(name, value) \
  955. trace_dpu_trace_counter(current->tgid, name, value)
  956. #endif /* _DPU_TRACE_H_ */
  957. /* This part must be outside protection */
  958. #undef TRACE_INCLUDE_PATH
  959. #define TRACE_INCLUDE_PATH .
  960. #include <trace/define_trace.h>