dw_hdmi-imx.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
  3. *
  4. * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
  5. */
  6. #include <linux/component.h>
  7. #include <linux/mfd/syscon.h>
  8. #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/regmap.h>
  12. #include <video/imx-ipu-v3.h>
  13. #include <drm/bridge/dw_hdmi.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_bridge.h>
  16. #include <drm/drm_edid.h>
  17. #include <drm/drm_encoder.h>
  18. #include <drm/drm_managed.h>
  19. #include <drm/drm_of.h>
  20. #include <drm/drm_simple_kms_helper.h>
  21. #include "imx-drm.h"
  22. struct imx_hdmi;
  23. struct imx_hdmi_encoder {
  24. struct drm_encoder encoder;
  25. struct imx_hdmi *hdmi;
  26. };
  27. struct imx_hdmi {
  28. struct device *dev;
  29. struct drm_bridge *bridge;
  30. struct dw_hdmi *hdmi;
  31. struct regmap *regmap;
  32. };
  33. static inline struct imx_hdmi *enc_to_imx_hdmi(struct drm_encoder *e)
  34. {
  35. return container_of(e, struct imx_hdmi_encoder, encoder)->hdmi;
  36. }
  37. static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = {
  38. {
  39. 45250000, {
  40. { 0x01e0, 0x0000 },
  41. { 0x21e1, 0x0000 },
  42. { 0x41e2, 0x0000 }
  43. },
  44. }, {
  45. 92500000, {
  46. { 0x0140, 0x0005 },
  47. { 0x2141, 0x0005 },
  48. { 0x4142, 0x0005 },
  49. },
  50. }, {
  51. 148500000, {
  52. { 0x00a0, 0x000a },
  53. { 0x20a1, 0x000a },
  54. { 0x40a2, 0x000a },
  55. },
  56. }, {
  57. 216000000, {
  58. { 0x00a0, 0x000a },
  59. { 0x2001, 0x000f },
  60. { 0x4002, 0x000f },
  61. },
  62. }, {
  63. ~0UL, {
  64. { 0x0000, 0x0000 },
  65. { 0x0000, 0x0000 },
  66. { 0x0000, 0x0000 },
  67. },
  68. }
  69. };
  70. static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = {
  71. /* pixelclk bpp8 bpp10 bpp12 */
  72. {
  73. 54000000, { 0x091c, 0x091c, 0x06dc },
  74. }, {
  75. 58400000, { 0x091c, 0x06dc, 0x06dc },
  76. }, {
  77. 72000000, { 0x06dc, 0x06dc, 0x091c },
  78. }, {
  79. 74250000, { 0x06dc, 0x0b5c, 0x091c },
  80. }, {
  81. 118800000, { 0x091c, 0x091c, 0x06dc },
  82. }, {
  83. 216000000, { 0x06dc, 0x0b5c, 0x091c },
  84. }, {
  85. ~0UL, { 0x0000, 0x0000, 0x0000 },
  86. },
  87. };
  88. /*
  89. * Resistance term 133Ohm Cfg
  90. * PREEMP config 0.00
  91. * TX/CK level 10
  92. */
  93. static const struct dw_hdmi_phy_config imx_phy_config[] = {
  94. /*pixelclk symbol term vlev */
  95. { 216000000, 0x800d, 0x0005, 0x01ad},
  96. { ~0UL, 0x0000, 0x0000, 0x0000}
  97. };
  98. static void dw_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
  99. {
  100. struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder);
  101. int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder);
  102. regmap_update_bits(hdmi->regmap, IOMUXC_GPR3,
  103. IMX6Q_GPR3_HDMI_MUX_CTL_MASK,
  104. mux << IMX6Q_GPR3_HDMI_MUX_CTL_SHIFT);
  105. }
  106. static int dw_hdmi_imx_atomic_check(struct drm_encoder *encoder,
  107. struct drm_crtc_state *crtc_state,
  108. struct drm_connector_state *conn_state)
  109. {
  110. struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
  111. imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
  112. imx_crtc_state->di_hsync_pin = 2;
  113. imx_crtc_state->di_vsync_pin = 3;
  114. return 0;
  115. }
  116. static const struct drm_encoder_helper_funcs dw_hdmi_imx_encoder_helper_funcs = {
  117. .enable = dw_hdmi_imx_encoder_enable,
  118. .atomic_check = dw_hdmi_imx_atomic_check,
  119. };
  120. static enum drm_mode_status
  121. imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
  122. const struct drm_display_info *info,
  123. const struct drm_display_mode *mode)
  124. {
  125. if (mode->clock < 13500)
  126. return MODE_CLOCK_LOW;
  127. /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */
  128. if (mode->clock > 216000)
  129. return MODE_CLOCK_HIGH;
  130. return MODE_OK;
  131. }
  132. static enum drm_mode_status
  133. imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data,
  134. const struct drm_display_info *info,
  135. const struct drm_display_mode *mode)
  136. {
  137. if (mode->clock < 13500)
  138. return MODE_CLOCK_LOW;
  139. /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */
  140. if (mode->clock > 216000)
  141. return MODE_CLOCK_HIGH;
  142. return MODE_OK;
  143. }
  144. static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
  145. .mpll_cfg = imx_mpll_cfg,
  146. .cur_ctr = imx_cur_ctr,
  147. .phy_config = imx_phy_config,
  148. .mode_valid = imx6q_hdmi_mode_valid,
  149. };
  150. static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
  151. .mpll_cfg = imx_mpll_cfg,
  152. .cur_ctr = imx_cur_ctr,
  153. .phy_config = imx_phy_config,
  154. .mode_valid = imx6dl_hdmi_mode_valid,
  155. };
  156. static const struct of_device_id dw_hdmi_imx_dt_ids[] = {
  157. { .compatible = "fsl,imx6q-hdmi",
  158. .data = &imx6q_hdmi_drv_data
  159. }, {
  160. .compatible = "fsl,imx6dl-hdmi",
  161. .data = &imx6dl_hdmi_drv_data
  162. },
  163. {},
  164. };
  165. MODULE_DEVICE_TABLE(of, dw_hdmi_imx_dt_ids);
  166. static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
  167. void *data)
  168. {
  169. struct drm_device *drm = data;
  170. struct imx_hdmi_encoder *hdmi_encoder;
  171. struct drm_encoder *encoder;
  172. int ret;
  173. hdmi_encoder = drmm_simple_encoder_alloc(drm, struct imx_hdmi_encoder,
  174. encoder, DRM_MODE_ENCODER_TMDS);
  175. if (IS_ERR(hdmi_encoder))
  176. return PTR_ERR(hdmi_encoder);
  177. hdmi_encoder->hdmi = dev_get_drvdata(dev);
  178. encoder = &hdmi_encoder->encoder;
  179. ret = imx_drm_encoder_parse_of(drm, encoder, dev->of_node);
  180. if (ret)
  181. return ret;
  182. drm_encoder_helper_add(encoder, &dw_hdmi_imx_encoder_helper_funcs);
  183. return drm_bridge_attach(encoder, hdmi_encoder->hdmi->bridge, NULL, 0);
  184. }
  185. static const struct component_ops dw_hdmi_imx_ops = {
  186. .bind = dw_hdmi_imx_bind,
  187. };
  188. static int dw_hdmi_imx_probe(struct platform_device *pdev)
  189. {
  190. struct device_node *np = pdev->dev.of_node;
  191. const struct of_device_id *match = of_match_node(dw_hdmi_imx_dt_ids, np);
  192. struct imx_hdmi *hdmi;
  193. int ret;
  194. hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
  195. if (!hdmi)
  196. return -ENOMEM;
  197. platform_set_drvdata(pdev, hdmi);
  198. hdmi->dev = &pdev->dev;
  199. hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
  200. if (IS_ERR(hdmi->regmap)) {
  201. dev_err(hdmi->dev, "Unable to get gpr\n");
  202. return PTR_ERR(hdmi->regmap);
  203. }
  204. hdmi->hdmi = dw_hdmi_probe(pdev, match->data);
  205. if (IS_ERR(hdmi->hdmi))
  206. return PTR_ERR(hdmi->hdmi);
  207. hdmi->bridge = of_drm_find_and_get_bridge(np);
  208. if (!hdmi->bridge) {
  209. dev_err(hdmi->dev, "Unable to find bridge\n");
  210. dw_hdmi_remove(hdmi->hdmi);
  211. return -ENODEV;
  212. }
  213. ret = component_add(&pdev->dev, &dw_hdmi_imx_ops);
  214. if (ret) {
  215. drm_bridge_put(hdmi->bridge);
  216. dw_hdmi_remove(hdmi->hdmi);
  217. }
  218. return ret;
  219. }
  220. static void dw_hdmi_imx_remove(struct platform_device *pdev)
  221. {
  222. struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
  223. component_del(&pdev->dev, &dw_hdmi_imx_ops);
  224. drm_bridge_put(hdmi->bridge);
  225. dw_hdmi_remove(hdmi->hdmi);
  226. }
  227. static struct platform_driver dw_hdmi_imx_platform_driver = {
  228. .probe = dw_hdmi_imx_probe,
  229. .remove = dw_hdmi_imx_remove,
  230. .driver = {
  231. .name = "dwhdmi-imx",
  232. .of_match_table = dw_hdmi_imx_dt_ids,
  233. },
  234. };
  235. module_platform_driver(dw_hdmi_imx_platform_driver);
  236. MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
  237. MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
  238. MODULE_DESCRIPTION("IMX6 Specific DW-HDMI Driver Extension");
  239. MODULE_LICENSE("GPL");