oaktrail_lvds.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright © 2006-2009 Intel Corporation
  4. *
  5. * Authors:
  6. * Eric Anholt <eric@anholt.net>
  7. * Dave Airlie <airlied@linux.ie>
  8. * Jesse Barnes <jesse.barnes@intel.com>
  9. */
  10. #include <linux/i2c.h>
  11. #include <linux/pm_runtime.h>
  12. #include <drm/drm_edid.h>
  13. #include <drm/drm_modeset_helper_vtables.h>
  14. #include <drm/drm_print.h>
  15. #include <drm/drm_simple_kms_helper.h>
  16. #include "intel_bios.h"
  17. #include "power.h"
  18. #include "psb_drv.h"
  19. #include "psb_intel_drv.h"
  20. #include "psb_intel_reg.h"
  21. /* The max/min PWM frequency in BPCR[31:17] - */
  22. /* The smallest number is 1 (not 0) that can fit in the
  23. * 15-bit field of the and then*/
  24. /* shifts to the left by one bit to get the actual 16-bit
  25. * value that the 15-bits correspond to.*/
  26. #define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
  27. #define BRIGHTNESS_MAX_LEVEL 100
  28. /*
  29. * Sets the power state for the panel.
  30. */
  31. static void oaktrail_lvds_set_power(struct drm_device *dev,
  32. struct gma_encoder *gma_encoder,
  33. bool on)
  34. {
  35. u32 pp_status;
  36. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  37. if (!gma_power_begin(dev, true))
  38. return;
  39. if (on) {
  40. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
  41. POWER_TARGET_ON);
  42. do {
  43. pp_status = REG_READ(PP_STATUS);
  44. } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
  45. dev_priv->is_lvds_on = true;
  46. if (dev_priv->ops->lvds_bl_power)
  47. dev_priv->ops->lvds_bl_power(dev, true);
  48. } else {
  49. if (dev_priv->ops->lvds_bl_power)
  50. dev_priv->ops->lvds_bl_power(dev, false);
  51. REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
  52. ~POWER_TARGET_ON);
  53. do {
  54. pp_status = REG_READ(PP_STATUS);
  55. } while (pp_status & PP_ON);
  56. dev_priv->is_lvds_on = false;
  57. }
  58. gma_power_end(dev);
  59. }
  60. static void oaktrail_lvds_dpms(struct drm_encoder *encoder, int mode)
  61. {
  62. struct drm_device *dev = encoder->dev;
  63. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  64. if (mode == DRM_MODE_DPMS_ON)
  65. oaktrail_lvds_set_power(dev, gma_encoder, true);
  66. else
  67. oaktrail_lvds_set_power(dev, gma_encoder, false);
  68. /* XXX: We never power down the LVDS pairs. */
  69. }
  70. static void oaktrail_lvds_mode_set(struct drm_encoder *encoder,
  71. struct drm_display_mode *mode,
  72. struct drm_display_mode *adjusted_mode)
  73. {
  74. struct drm_device *dev = encoder->dev;
  75. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  76. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  77. struct drm_connector_list_iter conn_iter;
  78. struct drm_connector *connector = NULL;
  79. struct drm_crtc *crtc = encoder->crtc;
  80. u32 lvds_port;
  81. uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
  82. if (!gma_power_begin(dev, true))
  83. return;
  84. /*
  85. * The LVDS pin pair will already have been turned on in the
  86. * psb_intel_crtc_mode_set since it has a large impact on the DPLL
  87. * settings.
  88. */
  89. lvds_port = (REG_READ(LVDS) &
  90. (~LVDS_PIPEB_SELECT)) |
  91. LVDS_PORT_EN |
  92. LVDS_BORDER_EN;
  93. /* If the firmware says dither on Moorestown, or the BIOS does
  94. on Oaktrail then enable dithering */
  95. if (mode_dev->panel_wants_dither || dev_priv->lvds_dither)
  96. lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
  97. REG_WRITE(LVDS, lvds_port);
  98. /* Find the connector we're trying to set up */
  99. drm_connector_list_iter_begin(dev, &conn_iter);
  100. drm_for_each_connector_iter(connector, &conn_iter) {
  101. if (connector->encoder && connector->encoder->crtc == crtc)
  102. break;
  103. }
  104. if (!connector) {
  105. drm_connector_list_iter_end(&conn_iter);
  106. DRM_ERROR("Couldn't find connector when setting mode");
  107. gma_power_end(dev);
  108. return;
  109. }
  110. drm_object_property_get_value( &connector->base,
  111. dev->mode_config.scaling_mode_property, &v);
  112. drm_connector_list_iter_end(&conn_iter);
  113. if (v == DRM_MODE_SCALE_NO_SCALE)
  114. REG_WRITE(PFIT_CONTROL, 0);
  115. else if (v == DRM_MODE_SCALE_ASPECT) {
  116. if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
  117. (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
  118. if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
  119. (mode->hdisplay * adjusted_mode->crtc_vdisplay))
  120. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  121. else if ((adjusted_mode->crtc_hdisplay *
  122. mode->vdisplay) > (mode->hdisplay *
  123. adjusted_mode->crtc_vdisplay))
  124. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  125. PFIT_SCALING_MODE_PILLARBOX);
  126. else
  127. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
  128. PFIT_SCALING_MODE_LETTERBOX);
  129. } else
  130. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  131. } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
  132. REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
  133. gma_power_end(dev);
  134. }
  135. static void oaktrail_lvds_prepare(struct drm_encoder *encoder)
  136. {
  137. struct drm_device *dev = encoder->dev;
  138. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  139. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  140. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  141. if (!gma_power_begin(dev, true))
  142. return;
  143. mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
  144. mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL &
  145. BACKLIGHT_DUTY_CYCLE_MASK);
  146. oaktrail_lvds_set_power(dev, gma_encoder, false);
  147. gma_power_end(dev);
  148. }
  149. static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev)
  150. {
  151. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  152. u32 ret;
  153. if (gma_power_begin(dev, false)) {
  154. ret = ((REG_READ(BLC_PWM_CTL) &
  155. BACKLIGHT_MODULATION_FREQ_MASK) >>
  156. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  157. gma_power_end(dev);
  158. } else
  159. ret = ((dev_priv->regs.saveBLC_PWM_CTL &
  160. BACKLIGHT_MODULATION_FREQ_MASK) >>
  161. BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
  162. return ret;
  163. }
  164. static void oaktrail_lvds_commit(struct drm_encoder *encoder)
  165. {
  166. struct drm_device *dev = encoder->dev;
  167. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  168. struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
  169. struct psb_intel_mode_device *mode_dev = &dev_priv->mode_dev;
  170. if (mode_dev->backlight_duty_cycle == 0)
  171. mode_dev->backlight_duty_cycle =
  172. oaktrail_lvds_get_max_backlight(dev);
  173. oaktrail_lvds_set_power(dev, gma_encoder, true);
  174. }
  175. static const struct drm_encoder_helper_funcs oaktrail_lvds_helper_funcs = {
  176. .dpms = oaktrail_lvds_dpms,
  177. .mode_fixup = psb_intel_lvds_mode_fixup,
  178. .prepare = oaktrail_lvds_prepare,
  179. .mode_set = oaktrail_lvds_mode_set,
  180. .commit = oaktrail_lvds_commit,
  181. };
  182. /* Returns the panel fixed mode from configuration. */
  183. static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev,
  184. struct psb_intel_mode_device *mode_dev)
  185. {
  186. struct drm_display_mode *mode = NULL;
  187. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  188. struct oaktrail_timing_info *ti = &dev_priv->gct_data.DTD;
  189. mode_dev->panel_fixed_mode = NULL;
  190. /* Use the firmware provided data on Moorestown */
  191. if (dev_priv->has_gct) {
  192. mode = kzalloc_obj(*mode);
  193. if (!mode)
  194. return;
  195. mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
  196. mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
  197. mode->hsync_start = mode->hdisplay + \
  198. ((ti->hsync_offset_hi << 8) | \
  199. ti->hsync_offset_lo);
  200. mode->hsync_end = mode->hsync_start + \
  201. ((ti->hsync_pulse_width_hi << 8) | \
  202. ti->hsync_pulse_width_lo);
  203. mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
  204. ti->hblank_lo);
  205. mode->vsync_start = \
  206. mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
  207. ti->vsync_offset_lo);
  208. mode->vsync_end = \
  209. mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
  210. ti->vsync_pulse_width_lo);
  211. mode->vtotal = mode->vdisplay + \
  212. ((ti->vblank_hi << 8) | ti->vblank_lo);
  213. mode->clock = ti->pixel_clock * 10;
  214. #if 0
  215. pr_info("hdisplay is %d\n", mode->hdisplay);
  216. pr_info("vdisplay is %d\n", mode->vdisplay);
  217. pr_info("HSS is %d\n", mode->hsync_start);
  218. pr_info("HSE is %d\n", mode->hsync_end);
  219. pr_info("htotal is %d\n", mode->htotal);
  220. pr_info("VSS is %d\n", mode->vsync_start);
  221. pr_info("VSE is %d\n", mode->vsync_end);
  222. pr_info("vtotal is %d\n", mode->vtotal);
  223. pr_info("clock is %d\n", mode->clock);
  224. #endif
  225. mode_dev->panel_fixed_mode = mode;
  226. }
  227. /* Use the BIOS VBT mode if available */
  228. if (mode_dev->panel_fixed_mode == NULL && mode_dev->vbt_mode)
  229. mode_dev->panel_fixed_mode = drm_mode_duplicate(dev,
  230. mode_dev->vbt_mode);
  231. /* Then try the LVDS VBT mode */
  232. if (mode_dev->panel_fixed_mode == NULL)
  233. if (dev_priv->lfp_lvds_vbt_mode)
  234. mode_dev->panel_fixed_mode =
  235. drm_mode_duplicate(dev,
  236. dev_priv->lfp_lvds_vbt_mode);
  237. /* If we still got no mode then bail */
  238. if (mode_dev->panel_fixed_mode == NULL)
  239. return;
  240. drm_mode_set_name(mode_dev->panel_fixed_mode);
  241. drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0);
  242. }
  243. /**
  244. * oaktrail_lvds_init - setup LVDS connectors on this device
  245. * @dev: drm device
  246. * @mode_dev: PSB mode device
  247. *
  248. * Create the connector, register the LVDS DDC bus, and try to figure out what
  249. * modes we can display on the LVDS panel (if present).
  250. */
  251. void oaktrail_lvds_init(struct drm_device *dev,
  252. struct psb_intel_mode_device *mode_dev)
  253. {
  254. struct gma_encoder *gma_encoder;
  255. struct gma_connector *gma_connector;
  256. struct gma_i2c_chan *ddc_bus;
  257. struct drm_connector *connector;
  258. struct drm_encoder *encoder;
  259. struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
  260. struct edid *edid;
  261. struct i2c_adapter *i2c_adap;
  262. struct drm_display_mode *scan; /* *modes, *bios_mode; */
  263. int ret;
  264. gma_encoder = kzalloc_obj(struct gma_encoder);
  265. if (!gma_encoder)
  266. return;
  267. gma_connector = kzalloc_obj(struct gma_connector);
  268. if (!gma_connector)
  269. goto err_free_encoder;
  270. connector = &gma_connector->base;
  271. encoder = &gma_encoder->base;
  272. dev_priv->is_lvds_on = true;
  273. ret = drm_connector_init(dev, connector,
  274. &psb_intel_lvds_connector_funcs,
  275. DRM_MODE_CONNECTOR_LVDS);
  276. if (ret)
  277. goto err_free_connector;
  278. ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_LVDS);
  279. if (ret)
  280. goto err_connector_cleanup;
  281. gma_connector_attach_encoder(gma_connector, gma_encoder);
  282. gma_encoder->type = INTEL_OUTPUT_LVDS;
  283. drm_encoder_helper_add(encoder, &oaktrail_lvds_helper_funcs);
  284. drm_connector_helper_add(connector,
  285. &psb_intel_lvds_connector_helper_funcs);
  286. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  287. connector->interlace_allowed = false;
  288. connector->doublescan_allowed = false;
  289. drm_object_attach_property(&connector->base,
  290. dev->mode_config.scaling_mode_property,
  291. DRM_MODE_SCALE_FULLSCREEN);
  292. drm_object_attach_property(&connector->base,
  293. dev_priv->backlight_property,
  294. BRIGHTNESS_MAX_LEVEL);
  295. mode_dev->panel_wants_dither = false;
  296. if (dev_priv->has_gct)
  297. mode_dev->panel_wants_dither = (dev_priv->gct_data.
  298. Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
  299. if (dev_priv->lvds_dither)
  300. mode_dev->panel_wants_dither = 1;
  301. /*
  302. * LVDS discovery:
  303. * 1) check for EDID on DDC
  304. * 2) check for VBT data
  305. * 3) check to see if LVDS is already on
  306. * if none of the above, no panel
  307. * 4) make sure lid is open
  308. * if closed, act like it's not there for now
  309. */
  310. edid = NULL;
  311. mutex_lock(&dev->mode_config.mutex);
  312. i2c_adap = i2c_get_adapter(dev_priv->ops->i2c_bus);
  313. if (i2c_adap)
  314. edid = drm_get_edid(connector, i2c_adap);
  315. if (edid == NULL && dev_priv->lpc_gpio_base) {
  316. ddc_bus = oaktrail_lvds_i2c_init(dev);
  317. if (!IS_ERR(ddc_bus)) {
  318. i2c_adap = &ddc_bus->base;
  319. edid = drm_get_edid(connector, i2c_adap);
  320. }
  321. }
  322. /*
  323. * Due to the logic in probing for i2c buses above we do not know the
  324. * i2c_adap until now. Hence we cannot use drm_connector_init_with_ddc()
  325. * but must instead set connector->ddc manually here.
  326. */
  327. connector->ddc = i2c_adap;
  328. /*
  329. * Attempt to get the fixed panel mode from DDC. Assume that the
  330. * preferred mode is the right one.
  331. */
  332. if (edid) {
  333. drm_connector_update_edid_property(connector, edid);
  334. drm_add_edid_modes(connector, edid);
  335. kfree(edid);
  336. list_for_each_entry(scan, &connector->probed_modes, head) {
  337. if (scan->type & DRM_MODE_TYPE_PREFERRED) {
  338. mode_dev->panel_fixed_mode =
  339. drm_mode_duplicate(dev, scan);
  340. goto out; /* FIXME: check for quirks */
  341. }
  342. }
  343. } else
  344. dev_err(dev->dev, "No ddc adapter available!\n");
  345. /*
  346. * If we didn't get EDID, try geting panel timing
  347. * from configuration data
  348. */
  349. oaktrail_lvds_get_configuration_mode(dev, mode_dev);
  350. if (mode_dev->panel_fixed_mode) {
  351. mode_dev->panel_fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
  352. goto out; /* FIXME: check for quirks */
  353. }
  354. /* If we still don't have a mode after all that, give up. */
  355. if (!mode_dev->panel_fixed_mode) {
  356. dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n");
  357. goto err_unlock;
  358. }
  359. out:
  360. mutex_unlock(&dev->mode_config.mutex);
  361. return;
  362. err_unlock:
  363. mutex_unlock(&dev->mode_config.mutex);
  364. gma_i2c_destroy(to_gma_i2c_chan(connector->ddc));
  365. drm_encoder_cleanup(encoder);
  366. err_connector_cleanup:
  367. drm_connector_cleanup(connector);
  368. err_free_connector:
  369. kfree(gma_connector);
  370. err_free_encoder:
  371. kfree(gma_encoder);
  372. }