exynos_drm_rotator.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2012 Samsung Electronics Co.Ltd
  4. * Authors:
  5. * YoungJun Cho <yj44.cho@samsung.com>
  6. * Eunchul Kim <chulspro.kim@samsung.com>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/component.h>
  10. #include <linux/err.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/of.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/sizes.h>
  18. #include <drm/drm_fourcc.h>
  19. #include <drm/exynos_drm.h>
  20. #include "exynos_drm_drv.h"
  21. #include "exynos_drm_ipp.h"
  22. #include "regs-rotator.h"
  23. /*
  24. * Rotator supports image crop/rotator and input/output DMA operations.
  25. * input DMA reads image data from the memory.
  26. * output DMA writes image data to memory.
  27. */
  28. #define ROTATOR_AUTOSUSPEND_DELAY 2000
  29. #define rot_read(offset) readl(rot->regs + (offset))
  30. #define rot_write(cfg, offset) writel(cfg, rot->regs + (offset))
  31. enum rot_irq_status {
  32. ROT_IRQ_STATUS_COMPLETE = 8,
  33. ROT_IRQ_STATUS_ILLEGAL = 9,
  34. };
  35. struct rot_variant {
  36. const struct exynos_drm_ipp_formats *formats;
  37. unsigned int num_formats;
  38. };
  39. /*
  40. * A structure of rotator context.
  41. * @ippdrv: prepare initialization using ippdrv.
  42. * @regs: memory mapped io registers.
  43. * @clock: rotator gate clock.
  44. * @limit_tbl: limitation of rotator.
  45. * @irq: irq number.
  46. */
  47. struct rot_context {
  48. struct exynos_drm_ipp ipp;
  49. struct drm_device *drm_dev;
  50. void *dma_priv;
  51. struct device *dev;
  52. void __iomem *regs;
  53. struct clk *clock;
  54. const struct exynos_drm_ipp_formats *formats;
  55. unsigned int num_formats;
  56. struct exynos_drm_ipp_task *task;
  57. };
  58. static void rotator_reg_set_irq(struct rot_context *rot, bool enable)
  59. {
  60. u32 val = rot_read(ROT_CONFIG);
  61. if (enable == true)
  62. val |= ROT_CONFIG_IRQ;
  63. else
  64. val &= ~ROT_CONFIG_IRQ;
  65. rot_write(val, ROT_CONFIG);
  66. }
  67. static enum rot_irq_status rotator_reg_get_irq_status(struct rot_context *rot)
  68. {
  69. u32 val = rot_read(ROT_STATUS);
  70. val = ROT_STATUS_IRQ(val);
  71. if (val == ROT_STATUS_IRQ_VAL_COMPLETE)
  72. return ROT_IRQ_STATUS_COMPLETE;
  73. return ROT_IRQ_STATUS_ILLEGAL;
  74. }
  75. static irqreturn_t rotator_irq_handler(int irq, void *arg)
  76. {
  77. struct rot_context *rot = arg;
  78. enum rot_irq_status irq_status;
  79. u32 val;
  80. /* Get execution result */
  81. irq_status = rotator_reg_get_irq_status(rot);
  82. /* clear status */
  83. val = rot_read(ROT_STATUS);
  84. val |= ROT_STATUS_IRQ_PENDING((u32)irq_status);
  85. rot_write(val, ROT_STATUS);
  86. if (rot->task) {
  87. struct exynos_drm_ipp_task *task = rot->task;
  88. rot->task = NULL;
  89. pm_runtime_mark_last_busy(rot->dev);
  90. pm_runtime_put_autosuspend(rot->dev);
  91. exynos_drm_ipp_task_done(task,
  92. irq_status == ROT_IRQ_STATUS_COMPLETE ? 0 : -EINVAL);
  93. }
  94. return IRQ_HANDLED;
  95. }
  96. static void rotator_src_set_fmt(struct rot_context *rot, u32 fmt)
  97. {
  98. u32 val;
  99. val = rot_read(ROT_CONTROL);
  100. val &= ~ROT_CONTROL_FMT_MASK;
  101. switch (fmt) {
  102. case DRM_FORMAT_NV12:
  103. val |= ROT_CONTROL_FMT_YCBCR420_2P;
  104. break;
  105. case DRM_FORMAT_XRGB8888:
  106. val |= ROT_CONTROL_FMT_RGB888;
  107. break;
  108. }
  109. rot_write(val, ROT_CONTROL);
  110. }
  111. static void rotator_src_set_buf(struct rot_context *rot,
  112. struct exynos_drm_ipp_buffer *buf)
  113. {
  114. u32 val;
  115. /* Set buffer size configuration */
  116. val = ROT_SET_BUF_SIZE_H(buf->buf.height) |
  117. ROT_SET_BUF_SIZE_W(buf->buf.pitch[0] / buf->format->cpp[0]);
  118. rot_write(val, ROT_SRC_BUF_SIZE);
  119. /* Set crop image position configuration */
  120. val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x);
  121. rot_write(val, ROT_SRC_CROP_POS);
  122. val = ROT_SRC_CROP_SIZE_H(buf->rect.h) |
  123. ROT_SRC_CROP_SIZE_W(buf->rect.w);
  124. rot_write(val, ROT_SRC_CROP_SIZE);
  125. /* Set buffer DMA address */
  126. rot_write(buf->dma_addr[0], ROT_SRC_BUF_ADDR(0));
  127. rot_write(buf->dma_addr[1], ROT_SRC_BUF_ADDR(1));
  128. }
  129. static void rotator_dst_set_transf(struct rot_context *rot,
  130. unsigned int rotation)
  131. {
  132. u32 val;
  133. /* Set transform configuration */
  134. val = rot_read(ROT_CONTROL);
  135. val &= ~ROT_CONTROL_FLIP_MASK;
  136. if (rotation & DRM_MODE_REFLECT_X)
  137. val |= ROT_CONTROL_FLIP_VERTICAL;
  138. if (rotation & DRM_MODE_REFLECT_Y)
  139. val |= ROT_CONTROL_FLIP_HORIZONTAL;
  140. val &= ~ROT_CONTROL_ROT_MASK;
  141. if (rotation & DRM_MODE_ROTATE_90)
  142. val |= ROT_CONTROL_ROT_90;
  143. else if (rotation & DRM_MODE_ROTATE_180)
  144. val |= ROT_CONTROL_ROT_180;
  145. else if (rotation & DRM_MODE_ROTATE_270)
  146. val |= ROT_CONTROL_ROT_270;
  147. rot_write(val, ROT_CONTROL);
  148. }
  149. static void rotator_dst_set_buf(struct rot_context *rot,
  150. struct exynos_drm_ipp_buffer *buf)
  151. {
  152. u32 val;
  153. /* Set buffer size configuration */
  154. val = ROT_SET_BUF_SIZE_H(buf->buf.height) |
  155. ROT_SET_BUF_SIZE_W(buf->buf.pitch[0] / buf->format->cpp[0]);
  156. rot_write(val, ROT_DST_BUF_SIZE);
  157. /* Set crop image position configuration */
  158. val = ROT_CROP_POS_Y(buf->rect.y) | ROT_CROP_POS_X(buf->rect.x);
  159. rot_write(val, ROT_DST_CROP_POS);
  160. /* Set buffer DMA address */
  161. rot_write(buf->dma_addr[0], ROT_DST_BUF_ADDR(0));
  162. rot_write(buf->dma_addr[1], ROT_DST_BUF_ADDR(1));
  163. }
  164. static void rotator_start(struct rot_context *rot)
  165. {
  166. u32 val;
  167. /* Set interrupt enable */
  168. rotator_reg_set_irq(rot, true);
  169. val = rot_read(ROT_CONTROL);
  170. val |= ROT_CONTROL_START;
  171. rot_write(val, ROT_CONTROL);
  172. }
  173. static int rotator_commit(struct exynos_drm_ipp *ipp,
  174. struct exynos_drm_ipp_task *task)
  175. {
  176. struct rot_context *rot =
  177. container_of(ipp, struct rot_context, ipp);
  178. int ret;
  179. ret = pm_runtime_resume_and_get(rot->dev);
  180. if (ret < 0) {
  181. dev_err(rot->dev, "failed to enable ROTATOR device.\n");
  182. return ret;
  183. }
  184. rot->task = task;
  185. rotator_src_set_fmt(rot, task->src.buf.fourcc);
  186. rotator_src_set_buf(rot, &task->src);
  187. rotator_dst_set_transf(rot, task->transform.rotation);
  188. rotator_dst_set_buf(rot, &task->dst);
  189. rotator_start(rot);
  190. return 0;
  191. }
  192. static const struct exynos_drm_ipp_funcs ipp_funcs = {
  193. .commit = rotator_commit,
  194. };
  195. static int rotator_bind(struct device *dev, struct device *master, void *data)
  196. {
  197. struct rot_context *rot = dev_get_drvdata(dev);
  198. struct drm_device *drm_dev = data;
  199. struct exynos_drm_ipp *ipp = &rot->ipp;
  200. rot->drm_dev = drm_dev;
  201. ipp->drm_dev = drm_dev;
  202. exynos_drm_register_dma(drm_dev, dev, &rot->dma_priv);
  203. exynos_drm_ipp_register(dev, ipp, &ipp_funcs,
  204. DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE,
  205. rot->formats, rot->num_formats, "rotator");
  206. dev_info(dev, "The exynos rotator has been probed successfully\n");
  207. return 0;
  208. }
  209. static void rotator_unbind(struct device *dev, struct device *master,
  210. void *data)
  211. {
  212. struct rot_context *rot = dev_get_drvdata(dev);
  213. struct exynos_drm_ipp *ipp = &rot->ipp;
  214. exynos_drm_ipp_unregister(dev, ipp);
  215. exynos_drm_unregister_dma(rot->drm_dev, rot->dev, &rot->dma_priv);
  216. }
  217. static const struct component_ops rotator_component_ops = {
  218. .bind = rotator_bind,
  219. .unbind = rotator_unbind,
  220. };
  221. static int rotator_probe(struct platform_device *pdev)
  222. {
  223. struct device *dev = &pdev->dev;
  224. struct rot_context *rot;
  225. const struct rot_variant *variant;
  226. int irq;
  227. int ret;
  228. rot = devm_kzalloc(dev, sizeof(*rot), GFP_KERNEL);
  229. if (!rot)
  230. return -ENOMEM;
  231. variant = of_device_get_match_data(dev);
  232. rot->formats = variant->formats;
  233. rot->num_formats = variant->num_formats;
  234. rot->dev = dev;
  235. rot->regs = devm_platform_ioremap_resource(pdev, 0);
  236. if (IS_ERR(rot->regs))
  237. return PTR_ERR(rot->regs);
  238. irq = platform_get_irq(pdev, 0);
  239. if (irq < 0)
  240. return irq;
  241. ret = devm_request_irq(dev, irq, rotator_irq_handler, 0, dev_name(dev),
  242. rot);
  243. if (ret < 0) {
  244. dev_err(dev, "failed to request irq\n");
  245. return ret;
  246. }
  247. rot->clock = devm_clk_get(dev, "rotator");
  248. if (IS_ERR(rot->clock)) {
  249. dev_err(dev, "failed to get clock\n");
  250. return PTR_ERR(rot->clock);
  251. }
  252. pm_runtime_use_autosuspend(dev);
  253. pm_runtime_set_autosuspend_delay(dev, ROTATOR_AUTOSUSPEND_DELAY);
  254. pm_runtime_enable(dev);
  255. platform_set_drvdata(pdev, rot);
  256. ret = component_add(dev, &rotator_component_ops);
  257. if (ret)
  258. goto err_component;
  259. return 0;
  260. err_component:
  261. pm_runtime_dont_use_autosuspend(dev);
  262. pm_runtime_disable(dev);
  263. return ret;
  264. }
  265. static void rotator_remove(struct platform_device *pdev)
  266. {
  267. struct device *dev = &pdev->dev;
  268. component_del(dev, &rotator_component_ops);
  269. pm_runtime_dont_use_autosuspend(dev);
  270. pm_runtime_disable(dev);
  271. }
  272. static int rotator_runtime_suspend(struct device *dev)
  273. {
  274. struct rot_context *rot = dev_get_drvdata(dev);
  275. clk_disable_unprepare(rot->clock);
  276. return 0;
  277. }
  278. static int rotator_runtime_resume(struct device *dev)
  279. {
  280. struct rot_context *rot = dev_get_drvdata(dev);
  281. return clk_prepare_enable(rot->clock);
  282. }
  283. static const struct drm_exynos_ipp_limit rotator_s5pv210_rbg888_limits[] = {
  284. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_16K }, .v = { 8, SZ_16K }) },
  285. { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
  286. };
  287. static const struct drm_exynos_ipp_limit rotator_4210_rbg888_limits[] = {
  288. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_16K }, .v = { 8, SZ_16K }) },
  289. { IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
  290. };
  291. static const struct drm_exynos_ipp_limit rotator_4412_rbg888_limits[] = {
  292. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
  293. { IPP_SIZE_LIMIT(AREA, .h.align = 4, .v.align = 4) },
  294. };
  295. static const struct drm_exynos_ipp_limit rotator_5250_rbg888_limits[] = {
  296. { IPP_SIZE_LIMIT(BUFFER, .h = { 8, SZ_8K }, .v = { 8, SZ_8K }) },
  297. { IPP_SIZE_LIMIT(AREA, .h.align = 2, .v.align = 2) },
  298. };
  299. static const struct drm_exynos_ipp_limit rotator_s5pv210_yuv_limits[] = {
  300. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
  301. { IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
  302. };
  303. static const struct drm_exynos_ipp_limit rotator_4210_yuv_limits[] = {
  304. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_64K }, .v = { 32, SZ_64K }) },
  305. { IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
  306. };
  307. static const struct drm_exynos_ipp_limit rotator_4412_yuv_limits[] = {
  308. { IPP_SIZE_LIMIT(BUFFER, .h = { 32, SZ_32K }, .v = { 32, SZ_32K }) },
  309. { IPP_SIZE_LIMIT(AREA, .h.align = 8, .v.align = 8) },
  310. };
  311. static const struct exynos_drm_ipp_formats rotator_s5pv210_formats[] = {
  312. { IPP_SRCDST_FORMAT(XRGB8888, rotator_s5pv210_rbg888_limits) },
  313. { IPP_SRCDST_FORMAT(NV12, rotator_s5pv210_yuv_limits) },
  314. };
  315. static const struct exynos_drm_ipp_formats rotator_4210_formats[] = {
  316. { IPP_SRCDST_FORMAT(XRGB8888, rotator_4210_rbg888_limits) },
  317. { IPP_SRCDST_FORMAT(NV12, rotator_4210_yuv_limits) },
  318. };
  319. static const struct exynos_drm_ipp_formats rotator_4412_formats[] = {
  320. { IPP_SRCDST_FORMAT(XRGB8888, rotator_4412_rbg888_limits) },
  321. { IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
  322. };
  323. static const struct exynos_drm_ipp_formats rotator_5250_formats[] = {
  324. { IPP_SRCDST_FORMAT(XRGB8888, rotator_5250_rbg888_limits) },
  325. { IPP_SRCDST_FORMAT(NV12, rotator_4412_yuv_limits) },
  326. };
  327. static const struct rot_variant rotator_s5pv210_data = {
  328. .formats = rotator_s5pv210_formats,
  329. .num_formats = ARRAY_SIZE(rotator_s5pv210_formats),
  330. };
  331. static const struct rot_variant rotator_4210_data = {
  332. .formats = rotator_4210_formats,
  333. .num_formats = ARRAY_SIZE(rotator_4210_formats),
  334. };
  335. static const struct rot_variant rotator_4412_data = {
  336. .formats = rotator_4412_formats,
  337. .num_formats = ARRAY_SIZE(rotator_4412_formats),
  338. };
  339. static const struct rot_variant rotator_5250_data = {
  340. .formats = rotator_5250_formats,
  341. .num_formats = ARRAY_SIZE(rotator_5250_formats),
  342. };
  343. static const struct of_device_id exynos_rotator_match[] = {
  344. {
  345. .compatible = "samsung,s5pv210-rotator",
  346. .data = &rotator_s5pv210_data,
  347. }, {
  348. .compatible = "samsung,exynos4210-rotator",
  349. .data = &rotator_4210_data,
  350. }, {
  351. .compatible = "samsung,exynos4212-rotator",
  352. .data = &rotator_4412_data,
  353. }, {
  354. .compatible = "samsung,exynos5250-rotator",
  355. .data = &rotator_5250_data,
  356. }, {
  357. },
  358. };
  359. MODULE_DEVICE_TABLE(of, exynos_rotator_match);
  360. static DEFINE_RUNTIME_DEV_PM_OPS(rotator_pm_ops, rotator_runtime_suspend,
  361. rotator_runtime_resume, NULL);
  362. struct platform_driver rotator_driver = {
  363. .probe = rotator_probe,
  364. .remove = rotator_remove,
  365. .driver = {
  366. .name = "exynos-rotator",
  367. .pm = pm_ptr(&rotator_pm_ops),
  368. .of_match_table = exynos_rotator_match,
  369. },
  370. };