hdlcd_drv.h 1003 B

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * ARM HDLCD Controller register definition
  4. */
  5. #ifndef __HDLCD_DRV_H__
  6. #define __HDLCD_DRV_H__
  7. struct hdlcd_drm_private {
  8. struct drm_device base;
  9. void __iomem *mmio;
  10. struct clk *clk;
  11. struct drm_crtc crtc;
  12. struct drm_plane *plane;
  13. unsigned int irq;
  14. #ifdef CONFIG_DEBUG_FS
  15. atomic_t buffer_underrun_count;
  16. atomic_t bus_error_count;
  17. atomic_t vsync_count;
  18. atomic_t dma_end_count;
  19. #endif
  20. };
  21. #define drm_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, base)
  22. #define crtc_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, crtc)
  23. static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd,
  24. unsigned int reg, u32 value)
  25. {
  26. writel(value, hdlcd->mmio + reg);
  27. }
  28. static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg)
  29. {
  30. return readl(hdlcd->mmio + reg);
  31. }
  32. int hdlcd_setup_crtc(struct drm_device *dev);
  33. void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
  34. #endif /* __HDLCD_DRV_H__ */