adp_drv.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. #include <linux/component.h>
  3. #include <linux/iopoll.h>
  4. #include <linux/of.h>
  5. #include <linux/platform_device.h>
  6. #include <drm/drm_atomic.h>
  7. #include <drm/drm_atomic_helper.h>
  8. #include <drm/drm_bridge.h>
  9. #include <drm/drm_bridge_connector.h>
  10. #include <drm/drm_drv.h>
  11. #include <drm/drm_fb_dma_helper.h>
  12. #include <drm/drm_framebuffer.h>
  13. #include <drm/drm_gem_atomic_helper.h>
  14. #include <drm/drm_gem_dma_helper.h>
  15. #include <drm/drm_gem_framebuffer_helper.h>
  16. #include <drm/drm_of.h>
  17. #include <drm/drm_print.h>
  18. #include <drm/drm_probe_helper.h>
  19. #include <drm/drm_vblank.h>
  20. #define ADP_INT_STATUS 0x34
  21. #define ADP_INT_STATUS_INT_MASK 0x7
  22. #define ADP_INT_STATUS_VBLANK 0x1
  23. #define ADP_CTRL 0x100
  24. #define ADP_CTRL_VBLANK_ON 0x12
  25. #define ADP_CTRL_FIFO_ON 0x601
  26. #define ADP_SCREEN_SIZE 0x0c
  27. #define ADP_SCREEN_HSIZE GENMASK(15, 0)
  28. #define ADP_SCREEN_VSIZE GENMASK(31, 16)
  29. #define ADBE_FIFO 0x10c0
  30. #define ADBE_FIFO_SYNC 0xc0000000
  31. #define ADBE_BLEND_BYPASS 0x2020
  32. #define ADBE_BLEND_EN1 0x2028
  33. #define ADBE_BLEND_EN2 0x2074
  34. #define ADBE_BLEND_EN3 0x202c
  35. #define ADBE_BLEND_EN4 0x2034
  36. #define ADBE_MASK_BUF 0x2200
  37. #define ADBE_SRC_START 0x4040
  38. #define ADBE_SRC_SIZE 0x4048
  39. #define ADBE_DST_START 0x4050
  40. #define ADBE_DST_SIZE 0x4054
  41. #define ADBE_STRIDE 0x4038
  42. #define ADBE_FB_BASE 0x4030
  43. #define ADBE_LAYER_EN1 0x4020
  44. #define ADBE_LAYER_EN2 0x4068
  45. #define ADBE_LAYER_EN3 0x40b4
  46. #define ADBE_LAYER_EN4 0x40f4
  47. #define ADBE_SCALE_CTL 0x40ac
  48. #define ADBE_SCALE_CTL_BYPASS 0x100000
  49. #define ADBE_LAYER_CTL 0x1038
  50. #define ADBE_LAYER_CTL_ENABLE 0x10000
  51. #define ADBE_PIX_FMT 0x402c
  52. #define ADBE_PIX_FMT_XRGB32 0x53e4001
  53. static int adp_open(struct inode *inode, struct file *filp)
  54. {
  55. /*
  56. * The modesetting driver does not check the non-desktop connector
  57. * property and keeps the device open and locked. If the touchbar daemon
  58. * opens the device first, modesetting breaks the whole X session.
  59. * Simply refuse to open the device for X11 server processes as
  60. * workaround.
  61. */
  62. if (current->comm[0] == 'X')
  63. return -EBUSY;
  64. return drm_open(inode, filp);
  65. }
  66. static const struct file_operations adp_fops = {
  67. .owner = THIS_MODULE,
  68. .open = adp_open,
  69. .release = drm_release,
  70. .unlocked_ioctl = drm_ioctl,
  71. .compat_ioctl = drm_compat_ioctl,
  72. .poll = drm_poll,
  73. .read = drm_read,
  74. .llseek = noop_llseek,
  75. .mmap = drm_gem_mmap,
  76. .fop_flags = FOP_UNSIGNED_OFFSET,
  77. DRM_GEM_DMA_UNMAPPED_AREA_FOPS
  78. };
  79. static int adp_drm_gem_dumb_create(struct drm_file *file_priv,
  80. struct drm_device *drm,
  81. struct drm_mode_create_dumb *args)
  82. {
  83. args->height = ALIGN(args->height, 64);
  84. args->size = args->pitch * args->height;
  85. return drm_gem_dma_dumb_create_internal(file_priv, drm, args);
  86. }
  87. static const struct drm_driver adp_driver = {
  88. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  89. .fops = &adp_fops,
  90. DRM_GEM_DMA_DRIVER_OPS_VMAP_WITH_DUMB_CREATE(adp_drm_gem_dumb_create),
  91. .name = "adp",
  92. .desc = "Apple Display Pipe DRM Driver",
  93. .major = 0,
  94. .minor = 1,
  95. };
  96. struct adp_drv_private {
  97. struct drm_device drm;
  98. struct drm_crtc crtc;
  99. struct drm_encoder *encoder;
  100. struct drm_connector *connector;
  101. struct drm_bridge *next_bridge;
  102. void __iomem *be;
  103. void __iomem *fe;
  104. u32 *mask_buf;
  105. u64 mask_buf_size;
  106. dma_addr_t mask_iova;
  107. int be_irq;
  108. int fe_irq;
  109. struct drm_pending_vblank_event *event;
  110. };
  111. #define to_adp(x) container_of(x, struct adp_drv_private, drm)
  112. #define crtc_to_adp(x) container_of(x, struct adp_drv_private, crtc)
  113. static int adp_plane_atomic_check(struct drm_plane *plane,
  114. struct drm_atomic_state *state)
  115. {
  116. struct drm_plane_state *new_plane_state;
  117. struct drm_crtc_state *crtc_state;
  118. new_plane_state = drm_atomic_get_new_plane_state(state, plane);
  119. if (!new_plane_state->crtc)
  120. return 0;
  121. crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc);
  122. if (IS_ERR(crtc_state))
  123. return PTR_ERR(crtc_state);
  124. return drm_atomic_helper_check_plane_state(new_plane_state,
  125. crtc_state,
  126. DRM_PLANE_NO_SCALING,
  127. DRM_PLANE_NO_SCALING,
  128. true, true);
  129. }
  130. static void adp_plane_atomic_update(struct drm_plane *plane,
  131. struct drm_atomic_state *state)
  132. {
  133. struct adp_drv_private *adp;
  134. struct drm_rect src_rect;
  135. struct drm_gem_dma_object *obj;
  136. struct drm_framebuffer *fb;
  137. struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
  138. u32 src_pos, src_size, dst_pos, dst_size;
  139. if (!plane || !new_state)
  140. return;
  141. fb = new_state->fb;
  142. if (!fb)
  143. return;
  144. adp = to_adp(plane->dev);
  145. drm_rect_fp_to_int(&src_rect, &new_state->src);
  146. src_pos = src_rect.x1 << 16 | src_rect.y1;
  147. dst_pos = new_state->dst.x1 << 16 | new_state->dst.y1;
  148. src_size = drm_rect_width(&src_rect) << 16 | drm_rect_height(&src_rect);
  149. dst_size = drm_rect_width(&new_state->dst) << 16 |
  150. drm_rect_height(&new_state->dst);
  151. writel(src_pos, adp->be + ADBE_SRC_START);
  152. writel(src_size, adp->be + ADBE_SRC_SIZE);
  153. writel(dst_pos, adp->be + ADBE_DST_START);
  154. writel(dst_size, adp->be + ADBE_DST_SIZE);
  155. writel(fb->pitches[0], adp->be + ADBE_STRIDE);
  156. obj = drm_fb_dma_get_gem_obj(fb, 0);
  157. if (obj)
  158. writel(obj->dma_addr + fb->offsets[0], adp->be + ADBE_FB_BASE);
  159. writel(BIT(0), adp->be + ADBE_LAYER_EN1);
  160. writel(BIT(0), adp->be + ADBE_LAYER_EN2);
  161. writel(BIT(0), adp->be + ADBE_LAYER_EN3);
  162. writel(BIT(0), adp->be + ADBE_LAYER_EN4);
  163. writel(ADBE_SCALE_CTL_BYPASS, adp->be + ADBE_SCALE_CTL);
  164. writel(ADBE_LAYER_CTL_ENABLE | BIT(0), adp->be + ADBE_LAYER_CTL);
  165. writel(ADBE_PIX_FMT_XRGB32, adp->be + ADBE_PIX_FMT);
  166. }
  167. static void adp_plane_atomic_disable(struct drm_plane *plane,
  168. struct drm_atomic_state *state)
  169. {
  170. struct adp_drv_private *adp = to_adp(plane->dev);
  171. writel(0x0, adp->be + ADBE_LAYER_EN1);
  172. writel(0x0, adp->be + ADBE_LAYER_EN2);
  173. writel(0x0, adp->be + ADBE_LAYER_EN3);
  174. writel(0x0, adp->be + ADBE_LAYER_EN4);
  175. writel(ADBE_LAYER_CTL_ENABLE, adp->be + ADBE_LAYER_CTL);
  176. }
  177. static const struct drm_plane_helper_funcs adp_plane_helper_funcs = {
  178. .atomic_check = adp_plane_atomic_check,
  179. .atomic_update = adp_plane_atomic_update,
  180. .atomic_disable = adp_plane_atomic_disable,
  181. DRM_GEM_SHADOW_PLANE_HELPER_FUNCS
  182. };
  183. static const struct drm_plane_funcs adp_plane_funcs = {
  184. .update_plane = drm_atomic_helper_update_plane,
  185. .disable_plane = drm_atomic_helper_disable_plane,
  186. DRM_GEM_SHADOW_PLANE_FUNCS
  187. };
  188. static const u32 plane_formats[] = {
  189. DRM_FORMAT_XRGB8888,
  190. };
  191. #define ALL_CRTCS 1
  192. static struct drm_plane *adp_plane_new(struct adp_drv_private *adp)
  193. {
  194. struct drm_device *drm = &adp->drm;
  195. struct drm_plane *plane;
  196. plane = __drmm_universal_plane_alloc(drm, sizeof(struct drm_plane), 0,
  197. ALL_CRTCS, &adp_plane_funcs,
  198. plane_formats, ARRAY_SIZE(plane_formats),
  199. NULL, DRM_PLANE_TYPE_PRIMARY, "plane");
  200. if (IS_ERR(plane)) {
  201. drm_err(drm, "failed to allocate plane");
  202. return plane;
  203. }
  204. drm_plane_helper_add(plane, &adp_plane_helper_funcs);
  205. return plane;
  206. }
  207. static void adp_enable_vblank(struct adp_drv_private *adp)
  208. {
  209. u32 cur_ctrl;
  210. writel(ADP_INT_STATUS_INT_MASK, adp->fe + ADP_INT_STATUS);
  211. cur_ctrl = readl(adp->fe + ADP_CTRL);
  212. writel(cur_ctrl | ADP_CTRL_VBLANK_ON, adp->fe + ADP_CTRL);
  213. }
  214. static int adp_crtc_enable_vblank(struct drm_crtc *crtc)
  215. {
  216. struct drm_device *dev = crtc->dev;
  217. struct adp_drv_private *adp = to_adp(dev);
  218. adp_enable_vblank(adp);
  219. return 0;
  220. }
  221. static void adp_disable_vblank(struct adp_drv_private *adp)
  222. {
  223. u32 cur_ctrl;
  224. cur_ctrl = readl(adp->fe + ADP_CTRL);
  225. writel(cur_ctrl & ~ADP_CTRL_VBLANK_ON, adp->fe + ADP_CTRL);
  226. writel(ADP_INT_STATUS_INT_MASK, adp->fe + ADP_INT_STATUS);
  227. }
  228. static void adp_crtc_disable_vblank(struct drm_crtc *crtc)
  229. {
  230. struct drm_device *dev = crtc->dev;
  231. struct adp_drv_private *adp = to_adp(dev);
  232. adp_disable_vblank(adp);
  233. }
  234. static void adp_crtc_atomic_enable(struct drm_crtc *crtc,
  235. struct drm_atomic_state *state)
  236. {
  237. struct adp_drv_private *adp = crtc_to_adp(crtc);
  238. writel(BIT(0), adp->be + ADBE_BLEND_EN2);
  239. writel(BIT(4), adp->be + ADBE_BLEND_EN1);
  240. writel(BIT(0), adp->be + ADBE_BLEND_EN3);
  241. writel(BIT(0), adp->be + ADBE_BLEND_BYPASS);
  242. writel(BIT(0), adp->be + ADBE_BLEND_EN4);
  243. drm_crtc_vblank_on(crtc);
  244. }
  245. static void adp_crtc_atomic_disable(struct drm_crtc *crtc,
  246. struct drm_atomic_state *state)
  247. {
  248. struct adp_drv_private *adp = crtc_to_adp(crtc);
  249. struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc);
  250. drm_atomic_helper_disable_planes_on_crtc(old_state, false);
  251. writel(0x0, adp->be + ADBE_BLEND_EN2);
  252. writel(0x0, adp->be + ADBE_BLEND_EN1);
  253. writel(0x0, adp->be + ADBE_BLEND_EN3);
  254. writel(0x0, adp->be + ADBE_BLEND_BYPASS);
  255. writel(0x0, adp->be + ADBE_BLEND_EN4);
  256. drm_crtc_vblank_off(crtc);
  257. }
  258. static void adp_crtc_atomic_flush(struct drm_crtc *crtc,
  259. struct drm_atomic_state *state)
  260. {
  261. u32 frame_num = 1;
  262. unsigned long flags;
  263. struct adp_drv_private *adp = crtc_to_adp(crtc);
  264. struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, crtc);
  265. u64 new_size = ALIGN(new_state->mode.hdisplay *
  266. new_state->mode.vdisplay * 4, PAGE_SIZE);
  267. if (new_size != adp->mask_buf_size) {
  268. if (adp->mask_buf)
  269. dma_free_coherent(crtc->dev->dev, adp->mask_buf_size,
  270. adp->mask_buf, adp->mask_iova);
  271. adp->mask_buf = NULL;
  272. if (new_size != 0) {
  273. adp->mask_buf = dma_alloc_coherent(crtc->dev->dev, new_size,
  274. &adp->mask_iova, GFP_KERNEL);
  275. memset(adp->mask_buf, 0xFF, new_size);
  276. writel(adp->mask_iova, adp->be + ADBE_MASK_BUF);
  277. }
  278. adp->mask_buf_size = new_size;
  279. }
  280. writel(ADBE_FIFO_SYNC | frame_num, adp->be + ADBE_FIFO);
  281. //FIXME: use adbe flush interrupt
  282. if (crtc->state->event) {
  283. struct drm_pending_vblank_event *event = crtc->state->event;
  284. crtc->state->event = NULL;
  285. spin_lock_irqsave(&crtc->dev->event_lock, flags);
  286. if (drm_crtc_vblank_get(crtc) != 0)
  287. drm_crtc_send_vblank_event(crtc, event);
  288. else
  289. adp->event = event;
  290. spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
  291. }
  292. }
  293. static const struct drm_crtc_funcs adp_crtc_funcs = {
  294. .destroy = drm_crtc_cleanup,
  295. .set_config = drm_atomic_helper_set_config,
  296. .page_flip = drm_atomic_helper_page_flip,
  297. .reset = drm_atomic_helper_crtc_reset,
  298. .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
  299. .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
  300. .enable_vblank = adp_crtc_enable_vblank,
  301. .disable_vblank = adp_crtc_disable_vblank,
  302. };
  303. static const struct drm_crtc_helper_funcs adp_crtc_helper_funcs = {
  304. .atomic_enable = adp_crtc_atomic_enable,
  305. .atomic_disable = adp_crtc_atomic_disable,
  306. .atomic_flush = adp_crtc_atomic_flush,
  307. };
  308. static int adp_setup_crtc(struct adp_drv_private *adp)
  309. {
  310. struct drm_device *drm = &adp->drm;
  311. struct drm_plane *primary;
  312. int ret;
  313. primary = adp_plane_new(adp);
  314. if (IS_ERR(primary))
  315. return PTR_ERR(primary);
  316. ret = drm_crtc_init_with_planes(drm, &adp->crtc, primary,
  317. NULL, &adp_crtc_funcs, NULL);
  318. if (ret)
  319. return ret;
  320. drm_crtc_helper_add(&adp->crtc, &adp_crtc_helper_funcs);
  321. return 0;
  322. }
  323. static const struct drm_mode_config_funcs adp_mode_config_funcs = {
  324. .fb_create = drm_gem_fb_create_with_dirty,
  325. .atomic_check = drm_atomic_helper_check,
  326. .atomic_commit = drm_atomic_helper_commit,
  327. };
  328. static int adp_setup_mode_config(struct adp_drv_private *adp)
  329. {
  330. struct drm_device *drm = &adp->drm;
  331. int ret;
  332. u32 size;
  333. ret = drmm_mode_config_init(drm);
  334. if (ret)
  335. return ret;
  336. /*
  337. * Query screen size restrict the frame buffer size to the screen size
  338. * aligned to the next multiple of 64. This is not necessary but can be
  339. * used as simple check for non-desktop devices.
  340. * Xorg's modesetting driver does not care about the connector
  341. * "non-desktop" property. The max frame buffer width or height can be
  342. * easily checked and a device can be reject if the max width/height is
  343. * smaller than 120 for example.
  344. * Any touchbar daemon is not limited by this small framebuffer size.
  345. */
  346. size = readl(adp->fe + ADP_SCREEN_SIZE);
  347. drm->mode_config.min_width = 32;
  348. drm->mode_config.min_height = 32;
  349. drm->mode_config.max_width = ALIGN(FIELD_GET(ADP_SCREEN_HSIZE, size), 64);
  350. drm->mode_config.max_height = ALIGN(FIELD_GET(ADP_SCREEN_VSIZE, size), 64);
  351. drm->mode_config.preferred_depth = 24;
  352. drm->mode_config.prefer_shadow = 0;
  353. drm->mode_config.funcs = &adp_mode_config_funcs;
  354. ret = adp_setup_crtc(adp);
  355. if (ret) {
  356. drm_err(drm, "failed to create crtc");
  357. return ret;
  358. }
  359. adp->encoder = drmm_plain_encoder_alloc(drm, NULL, DRM_MODE_ENCODER_DSI, NULL);
  360. if (IS_ERR(adp->encoder)) {
  361. drm_err(drm, "failed to init encoder");
  362. return PTR_ERR(adp->encoder);
  363. }
  364. adp->encoder->possible_crtcs = ALL_CRTCS;
  365. ret = drm_bridge_attach(adp->encoder, adp->next_bridge, NULL,
  366. DRM_BRIDGE_ATTACH_NO_CONNECTOR);
  367. if (ret) {
  368. drm_err(drm, "failed to init bridge chain");
  369. return ret;
  370. }
  371. adp->connector = drm_bridge_connector_init(drm, adp->encoder);
  372. if (IS_ERR(adp->connector))
  373. return PTR_ERR(adp->connector);
  374. drm_connector_attach_encoder(adp->connector, adp->encoder);
  375. ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
  376. if (ret < 0) {
  377. drm_err(drm, "failed to initialize vblank");
  378. return ret;
  379. }
  380. drm_mode_config_reset(drm);
  381. return 0;
  382. }
  383. static int adp_parse_of(struct platform_device *pdev, struct adp_drv_private *adp)
  384. {
  385. struct device *dev = &pdev->dev;
  386. adp->be = devm_platform_ioremap_resource_byname(pdev, "be");
  387. if (IS_ERR(adp->be)) {
  388. dev_err(dev, "failed to map display backend mmio");
  389. return PTR_ERR(adp->be);
  390. }
  391. adp->fe = devm_platform_ioremap_resource_byname(pdev, "fe");
  392. if (IS_ERR(adp->fe)) {
  393. dev_err(dev, "failed to map display pipe mmio");
  394. return PTR_ERR(adp->fe);
  395. }
  396. adp->be_irq = platform_get_irq_byname(pdev, "be");
  397. if (adp->be_irq < 0)
  398. return adp->be_irq;
  399. adp->fe_irq = platform_get_irq_byname(pdev, "fe");
  400. if (adp->fe_irq < 0)
  401. return adp->fe_irq;
  402. return 0;
  403. }
  404. static irqreturn_t adp_fe_irq(int irq, void *arg)
  405. {
  406. struct adp_drv_private *adp = (struct adp_drv_private *)arg;
  407. u32 int_status;
  408. u32 int_ctl;
  409. int_status = readl(adp->fe + ADP_INT_STATUS);
  410. if (int_status & ADP_INT_STATUS_VBLANK) {
  411. drm_crtc_handle_vblank(&adp->crtc);
  412. spin_lock(&adp->crtc.dev->event_lock);
  413. if (adp->event) {
  414. int_ctl = readl(adp->fe + ADP_CTRL);
  415. if ((int_ctl & 0xF00) == 0x600) {
  416. drm_crtc_send_vblank_event(&adp->crtc, adp->event);
  417. adp->event = NULL;
  418. drm_crtc_vblank_put(&adp->crtc);
  419. }
  420. }
  421. spin_unlock(&adp->crtc.dev->event_lock);
  422. }
  423. writel(int_status, adp->fe + ADP_INT_STATUS);
  424. return IRQ_HANDLED;
  425. }
  426. static int adp_drm_bind(struct device *dev)
  427. {
  428. struct drm_device *drm = dev_get_drvdata(dev);
  429. struct adp_drv_private *adp = to_adp(drm);
  430. int err;
  431. writel(ADP_CTRL_FIFO_ON, adp->fe + ADP_CTRL);
  432. adp->next_bridge = drmm_of_get_bridge(&adp->drm, dev->of_node, 0, 0);
  433. if (IS_ERR(adp->next_bridge)) {
  434. dev_err(dev, "failed to find next bridge");
  435. return PTR_ERR(adp->next_bridge);
  436. }
  437. err = adp_setup_mode_config(adp);
  438. if (err < 0)
  439. return err;
  440. err = request_irq(adp->fe_irq, adp_fe_irq, 0, "adp-fe", adp);
  441. if (err)
  442. return err;
  443. err = drm_dev_register(&adp->drm, 0);
  444. if (err)
  445. return err;
  446. return 0;
  447. }
  448. static void adp_drm_unbind(struct device *dev)
  449. {
  450. struct drm_device *drm = dev_get_drvdata(dev);
  451. struct adp_drv_private *adp = to_adp(drm);
  452. drm_dev_unregister(drm);
  453. drm_atomic_helper_shutdown(drm);
  454. free_irq(adp->fe_irq, adp);
  455. }
  456. static const struct component_master_ops adp_master_ops = {
  457. .bind = adp_drm_bind,
  458. .unbind = adp_drm_unbind,
  459. };
  460. static int compare_dev(struct device *dev, void *data)
  461. {
  462. return dev->of_node == data;
  463. }
  464. static int adp_probe(struct platform_device *pdev)
  465. {
  466. struct device_node *port;
  467. struct component_match *match = NULL;
  468. struct adp_drv_private *adp;
  469. int err;
  470. adp = devm_drm_dev_alloc(&pdev->dev, &adp_driver, struct adp_drv_private, drm);
  471. if (IS_ERR(adp))
  472. return PTR_ERR(adp);
  473. dev_set_drvdata(&pdev->dev, &adp->drm);
  474. err = adp_parse_of(pdev, adp);
  475. if (err < 0)
  476. return err;
  477. port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
  478. if (!port)
  479. return -ENODEV;
  480. drm_of_component_match_add(&pdev->dev, &match, compare_dev, port);
  481. of_node_put(port);
  482. return component_master_add_with_match(&pdev->dev, &adp_master_ops, match);
  483. }
  484. static void adp_remove(struct platform_device *pdev)
  485. {
  486. component_master_del(&pdev->dev, &adp_master_ops);
  487. dev_set_drvdata(&pdev->dev, NULL);
  488. }
  489. static const struct of_device_id adp_of_match[] = {
  490. { .compatible = "apple,h7-display-pipe", },
  491. { },
  492. };
  493. MODULE_DEVICE_TABLE(of, adp_of_match);
  494. static struct platform_driver adp_platform_driver = {
  495. .driver = {
  496. .name = "adp",
  497. .of_match_table = adp_of_match,
  498. },
  499. .probe = adp_probe,
  500. .remove = adp_remove,
  501. };
  502. module_platform_driver(adp_platform_driver);
  503. MODULE_DESCRIPTION("Apple Display Pipe DRM driver");
  504. MODULE_LICENSE("GPL");