hp82335.h 1.5 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /***************************************************************************
  3. * copyright : (C) 2002 by Frank Mori Hess *
  4. ***************************************************************************/
  5. #ifndef _HP82335_H
  6. #define _HP82335_H
  7. #include "tms9914.h"
  8. #include "gpibP.h"
  9. // struct which defines private_data for board
  10. struct hp82335_priv {
  11. struct tms9914_priv tms9914_priv;
  12. unsigned int irq;
  13. unsigned long raw_iobase;
  14. };
  15. // size of io memory region used
  16. static const int hp82335_rom_size = 0x2000;
  17. static const int hp82335_upper_iomem_size = 0x2000;
  18. // hp82335 register offsets
  19. enum hp_read_regs {
  20. HPREG_CSR = 0x17f8,
  21. HPREG_STATUS = 0x1ffc,
  22. };
  23. enum hp_write_regs {
  24. HPREG_INTR_CLEAR = 0x17f7,
  25. HPREG_CCR = HPREG_CSR,
  26. };
  27. enum ccr_bits {
  28. DMA_ENABLE = (1 << 0), /* DMA enable */
  29. DMA_CHAN_SELECT = (1 << 1), /* DMA channel select O=3,1=2 */
  30. INTR_ENABLE = (1 << 2), /* interrupt enable */
  31. SYS_DISABLE = (1 << 3), /* system controller disable */
  32. };
  33. enum csr_bits {
  34. SWITCH6 = (1 << 0), /* switch 6 position */
  35. SWITCH5 = (1 << 1), /* switch 5 position */
  36. SYS_CONTROLLER = (1 << 2), /* system controller bit */
  37. DMA_ENABLE_STATUS = (1 << 4), /* DMA enabled */
  38. DMA_CHAN_STATUS = (1 << 5), /* DMA channel 0=3,1=2 */
  39. INTR_ENABLE_STATUS = (1 << 6), /* Interrupt enable */
  40. INTR_PENDING = (1 << 7), /* Interrupt Pending */
  41. };
  42. #endif // _HP82335_H