main.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /* Copyright(c) Advanced Micro Devices, Inc */
  3. #include <linux/module.h>
  4. #include <linux/auxiliary_bus.h>
  5. #include <linux/pci.h>
  6. #include <linux/vmalloc.h>
  7. #include <linux/bitfield.h>
  8. #include <linux/string.h>
  9. #include <uapi/fwctl/fwctl.h>
  10. #include <uapi/fwctl/pds.h>
  11. #include <linux/fwctl.h>
  12. #include <linux/pds/pds_common.h>
  13. #include <linux/pds/pds_core_if.h>
  14. #include <linux/pds/pds_adminq.h>
  15. #include <linux/pds/pds_auxbus.h>
  16. struct pdsfc_uctx {
  17. struct fwctl_uctx uctx;
  18. u32 uctx_caps;
  19. };
  20. struct pdsfc_rpc_endpoint_info {
  21. u32 endpoint;
  22. dma_addr_t operations_pa;
  23. struct pds_fwctl_query_data *operations;
  24. struct mutex lock; /* lock for endpoint info management */
  25. };
  26. struct pdsfc_dev {
  27. struct fwctl_device fwctl;
  28. struct pds_auxiliary_dev *padev;
  29. u32 caps;
  30. struct pds_fwctl_ident ident;
  31. dma_addr_t endpoints_pa;
  32. struct pds_fwctl_query_data *endpoints;
  33. struct pdsfc_rpc_endpoint_info *endpoint_info;
  34. };
  35. static int pdsfc_open_uctx(struct fwctl_uctx *uctx)
  36. {
  37. struct pdsfc_dev *pdsfc = container_of(uctx->fwctl, struct pdsfc_dev, fwctl);
  38. struct pdsfc_uctx *pdsfc_uctx = container_of(uctx, struct pdsfc_uctx, uctx);
  39. pdsfc_uctx->uctx_caps = pdsfc->caps;
  40. return 0;
  41. }
  42. static void pdsfc_close_uctx(struct fwctl_uctx *uctx)
  43. {
  44. }
  45. static void *pdsfc_info(struct fwctl_uctx *uctx, size_t *length)
  46. {
  47. struct pdsfc_uctx *pdsfc_uctx = container_of(uctx, struct pdsfc_uctx, uctx);
  48. struct fwctl_info_pds *info;
  49. info = kzalloc_obj(*info);
  50. if (!info)
  51. return ERR_PTR(-ENOMEM);
  52. info->uctx_caps = pdsfc_uctx->uctx_caps;
  53. return info;
  54. }
  55. static int pdsfc_identify(struct pdsfc_dev *pdsfc)
  56. {
  57. struct device *dev = &pdsfc->fwctl.dev;
  58. union pds_core_adminq_comp comp = {0};
  59. union pds_core_adminq_cmd cmd;
  60. struct pds_fwctl_ident *ident;
  61. dma_addr_t ident_pa;
  62. int err;
  63. ident = dma_alloc_coherent(dev->parent, sizeof(*ident), &ident_pa, GFP_KERNEL);
  64. if (!ident) {
  65. dev_err(dev, "Failed to map ident buffer\n");
  66. return -ENOMEM;
  67. }
  68. cmd = (union pds_core_adminq_cmd) {
  69. .fwctl_ident = {
  70. .opcode = PDS_FWCTL_CMD_IDENT,
  71. .version = 0,
  72. .len = cpu_to_le32(sizeof(*ident)),
  73. .ident_pa = cpu_to_le64(ident_pa),
  74. }
  75. };
  76. err = pds_client_adminq_cmd(pdsfc->padev, &cmd, sizeof(cmd), &comp, 0);
  77. if (err)
  78. dev_err(dev, "Failed to send adminq cmd opcode: %u err: %d\n",
  79. cmd.fwctl_ident.opcode, err);
  80. else
  81. pdsfc->ident = *ident;
  82. dma_free_coherent(dev->parent, sizeof(*ident), ident, ident_pa);
  83. return err;
  84. }
  85. static void pdsfc_free_endpoints(struct pdsfc_dev *pdsfc)
  86. {
  87. struct device *dev = &pdsfc->fwctl.dev;
  88. u32 num_endpoints;
  89. int i;
  90. if (!pdsfc->endpoints)
  91. return;
  92. num_endpoints = le32_to_cpu(pdsfc->endpoints->num_entries);
  93. for (i = 0; pdsfc->endpoint_info && i < num_endpoints; i++)
  94. mutex_destroy(&pdsfc->endpoint_info[i].lock);
  95. vfree(pdsfc->endpoint_info);
  96. pdsfc->endpoint_info = NULL;
  97. dma_free_coherent(dev->parent, PAGE_SIZE,
  98. pdsfc->endpoints, pdsfc->endpoints_pa);
  99. pdsfc->endpoints = NULL;
  100. pdsfc->endpoints_pa = DMA_MAPPING_ERROR;
  101. }
  102. static void pdsfc_free_operations(struct pdsfc_dev *pdsfc)
  103. {
  104. struct device *dev = &pdsfc->fwctl.dev;
  105. u32 num_endpoints;
  106. int i;
  107. num_endpoints = le32_to_cpu(pdsfc->endpoints->num_entries);
  108. for (i = 0; i < num_endpoints; i++) {
  109. struct pdsfc_rpc_endpoint_info *ei = &pdsfc->endpoint_info[i];
  110. if (ei->operations) {
  111. dma_free_coherent(dev->parent, PAGE_SIZE,
  112. ei->operations, ei->operations_pa);
  113. ei->operations = NULL;
  114. ei->operations_pa = DMA_MAPPING_ERROR;
  115. }
  116. }
  117. }
  118. static struct pds_fwctl_query_data *pdsfc_get_endpoints(struct pdsfc_dev *pdsfc,
  119. dma_addr_t *pa)
  120. {
  121. struct device *dev = &pdsfc->fwctl.dev;
  122. union pds_core_adminq_comp comp = {0};
  123. struct pds_fwctl_query_data *data;
  124. union pds_core_adminq_cmd cmd;
  125. dma_addr_t data_pa;
  126. int err;
  127. data = dma_alloc_coherent(dev->parent, PAGE_SIZE, &data_pa, GFP_KERNEL);
  128. if (!data) {
  129. dev_err(dev, "Failed to map endpoint list\n");
  130. return ERR_PTR(-ENOMEM);
  131. }
  132. cmd = (union pds_core_adminq_cmd) {
  133. .fwctl_query = {
  134. .opcode = PDS_FWCTL_CMD_QUERY,
  135. .entity = PDS_FWCTL_RPC_ROOT,
  136. .version = 0,
  137. .query_data_buf_len = cpu_to_le32(PAGE_SIZE),
  138. .query_data_buf_pa = cpu_to_le64(data_pa),
  139. }
  140. };
  141. err = pds_client_adminq_cmd(pdsfc->padev, &cmd, sizeof(cmd), &comp, 0);
  142. if (err) {
  143. dev_err(dev, "Failed to send adminq cmd opcode: %u entity: %u err: %d\n",
  144. cmd.fwctl_query.opcode, cmd.fwctl_query.entity, err);
  145. dma_free_coherent(dev->parent, PAGE_SIZE, data, data_pa);
  146. return ERR_PTR(err);
  147. }
  148. *pa = data_pa;
  149. return data;
  150. }
  151. static int pdsfc_init_endpoints(struct pdsfc_dev *pdsfc)
  152. {
  153. struct pds_fwctl_query_data_endpoint *ep_entry;
  154. u32 num_endpoints;
  155. int i;
  156. pdsfc->endpoints = pdsfc_get_endpoints(pdsfc, &pdsfc->endpoints_pa);
  157. if (IS_ERR(pdsfc->endpoints))
  158. return PTR_ERR(pdsfc->endpoints);
  159. num_endpoints = le32_to_cpu(pdsfc->endpoints->num_entries);
  160. pdsfc->endpoint_info = vcalloc(num_endpoints,
  161. sizeof(*pdsfc->endpoint_info));
  162. if (!pdsfc->endpoint_info) {
  163. pdsfc_free_endpoints(pdsfc);
  164. return -ENOMEM;
  165. }
  166. ep_entry = (struct pds_fwctl_query_data_endpoint *)pdsfc->endpoints->entries;
  167. for (i = 0; i < num_endpoints; i++) {
  168. mutex_init(&pdsfc->endpoint_info[i].lock);
  169. pdsfc->endpoint_info[i].endpoint = le32_to_cpu(ep_entry[i].id);
  170. }
  171. return 0;
  172. }
  173. static struct pds_fwctl_query_data *pdsfc_get_operations(struct pdsfc_dev *pdsfc,
  174. dma_addr_t *pa, u32 ep)
  175. {
  176. struct pds_fwctl_query_data_operation *entries;
  177. struct device *dev = &pdsfc->fwctl.dev;
  178. union pds_core_adminq_comp comp = {0};
  179. struct pds_fwctl_query_data *data;
  180. union pds_core_adminq_cmd cmd;
  181. dma_addr_t data_pa;
  182. u32 num_entries;
  183. int err;
  184. int i;
  185. /* Query the operations list for the given endpoint */
  186. data = dma_alloc_coherent(dev->parent, PAGE_SIZE, &data_pa, GFP_KERNEL);
  187. if (!data) {
  188. dev_err(dev, "Failed to map operations list\n");
  189. return ERR_PTR(-ENOMEM);
  190. }
  191. cmd = (union pds_core_adminq_cmd) {
  192. .fwctl_query = {
  193. .opcode = PDS_FWCTL_CMD_QUERY,
  194. .entity = PDS_FWCTL_RPC_ENDPOINT,
  195. .version = 0,
  196. .query_data_buf_len = cpu_to_le32(PAGE_SIZE),
  197. .query_data_buf_pa = cpu_to_le64(data_pa),
  198. .ep = cpu_to_le32(ep),
  199. }
  200. };
  201. err = pds_client_adminq_cmd(pdsfc->padev, &cmd, sizeof(cmd), &comp, 0);
  202. if (err) {
  203. dev_err(dev, "Failed to send adminq cmd opcode: %u entity: %u err: %d\n",
  204. cmd.fwctl_query.opcode, cmd.fwctl_query.entity, err);
  205. dma_free_coherent(dev->parent, PAGE_SIZE, data, data_pa);
  206. return ERR_PTR(err);
  207. }
  208. *pa = data_pa;
  209. entries = (struct pds_fwctl_query_data_operation *)data->entries;
  210. num_entries = le32_to_cpu(data->num_entries);
  211. dev_dbg(dev, "num_entries %d\n", num_entries);
  212. for (i = 0; i < num_entries; i++) {
  213. /* Translate FW command attribute to fwctl scope */
  214. switch (entries[i].scope) {
  215. case PDSFC_FW_CMD_ATTR_READ:
  216. case PDSFC_FW_CMD_ATTR_WRITE:
  217. case PDSFC_FW_CMD_ATTR_SYNC:
  218. entries[i].scope = FWCTL_RPC_CONFIGURATION;
  219. break;
  220. case PDSFC_FW_CMD_ATTR_DEBUG_READ:
  221. entries[i].scope = FWCTL_RPC_DEBUG_READ_ONLY;
  222. break;
  223. case PDSFC_FW_CMD_ATTR_DEBUG_WRITE:
  224. entries[i].scope = FWCTL_RPC_DEBUG_WRITE;
  225. break;
  226. default:
  227. entries[i].scope = FWCTL_RPC_DEBUG_WRITE_FULL;
  228. break;
  229. }
  230. dev_dbg(dev, "endpoint %d operation: id %x scope %d\n",
  231. ep, le32_to_cpu(entries[i].id), entries[i].scope);
  232. }
  233. return data;
  234. }
  235. static int pdsfc_validate_rpc(struct pdsfc_dev *pdsfc,
  236. struct fwctl_rpc_pds *rpc,
  237. enum fwctl_rpc_scope scope)
  238. {
  239. struct pds_fwctl_query_data_operation *op_entry;
  240. struct pdsfc_rpc_endpoint_info *ep_info = NULL;
  241. struct device *dev = &pdsfc->fwctl.dev;
  242. u32 num_entries;
  243. int i;
  244. /* validate rpc in_len & out_len based
  245. * on ident.max_req_sz & max_resp_sz
  246. */
  247. if (rpc->in.len > le32_to_cpu(pdsfc->ident.max_req_sz)) {
  248. dev_dbg(dev, "Invalid request size %u, max %u\n",
  249. rpc->in.len, le32_to_cpu(pdsfc->ident.max_req_sz));
  250. return -EINVAL;
  251. }
  252. if (rpc->out.len > le32_to_cpu(pdsfc->ident.max_resp_sz)) {
  253. dev_dbg(dev, "Invalid response size %u, max %u\n",
  254. rpc->out.len, le32_to_cpu(pdsfc->ident.max_resp_sz));
  255. return -EINVAL;
  256. }
  257. num_entries = le32_to_cpu(pdsfc->endpoints->num_entries);
  258. for (i = 0; i < num_entries; i++) {
  259. if (pdsfc->endpoint_info[i].endpoint == rpc->in.ep) {
  260. ep_info = &pdsfc->endpoint_info[i];
  261. break;
  262. }
  263. }
  264. if (!ep_info) {
  265. dev_dbg(dev, "Invalid endpoint %d\n", rpc->in.ep);
  266. return -EINVAL;
  267. }
  268. /* query and cache this endpoint's operations */
  269. mutex_lock(&ep_info->lock);
  270. if (!ep_info->operations) {
  271. struct pds_fwctl_query_data *operations;
  272. operations = pdsfc_get_operations(pdsfc,
  273. &ep_info->operations_pa,
  274. rpc->in.ep);
  275. if (IS_ERR(operations)) {
  276. mutex_unlock(&ep_info->lock);
  277. return -ENOMEM;
  278. }
  279. ep_info->operations = operations;
  280. }
  281. mutex_unlock(&ep_info->lock);
  282. /* reject unsupported and/or out of scope commands */
  283. op_entry = (struct pds_fwctl_query_data_operation *)ep_info->operations->entries;
  284. num_entries = le32_to_cpu(ep_info->operations->num_entries);
  285. for (i = 0; i < num_entries; i++) {
  286. if (PDS_FWCTL_RPC_OPCODE_CMP(rpc->in.op, le32_to_cpu(op_entry[i].id))) {
  287. if (scope < op_entry[i].scope)
  288. return -EPERM;
  289. return 0;
  290. }
  291. }
  292. dev_dbg(dev, "Invalid operation %d for endpoint %d\n", rpc->in.op, rpc->in.ep);
  293. return -EINVAL;
  294. }
  295. static void *pdsfc_fw_rpc(struct fwctl_uctx *uctx, enum fwctl_rpc_scope scope,
  296. void *in, size_t in_len, size_t *out_len)
  297. {
  298. struct pdsfc_dev *pdsfc = container_of(uctx->fwctl, struct pdsfc_dev, fwctl);
  299. struct device *dev = &uctx->fwctl->dev;
  300. union pds_core_adminq_comp comp = {0};
  301. dma_addr_t out_payload_dma_addr = 0;
  302. dma_addr_t in_payload_dma_addr = 0;
  303. struct fwctl_rpc_pds *rpc = in;
  304. union pds_core_adminq_cmd cmd;
  305. void *out_payload = NULL;
  306. void *in_payload = NULL;
  307. void *out = NULL;
  308. int err;
  309. err = pdsfc_validate_rpc(pdsfc, rpc, scope);
  310. if (err)
  311. return ERR_PTR(err);
  312. if (rpc->in.len > 0) {
  313. in_payload = memdup_user(u64_to_user_ptr(rpc->in.payload), rpc->in.len);
  314. if (IS_ERR(in_payload)) {
  315. dev_dbg(dev, "Failed to copy in_payload from user\n");
  316. return in_payload;
  317. }
  318. in_payload_dma_addr = dma_map_single(dev->parent, in_payload,
  319. rpc->in.len, DMA_TO_DEVICE);
  320. err = dma_mapping_error(dev->parent, in_payload_dma_addr);
  321. if (err) {
  322. dev_dbg(dev, "Failed to map in_payload\n");
  323. goto err_in_payload;
  324. }
  325. }
  326. if (rpc->out.len > 0) {
  327. out_payload = kzalloc(rpc->out.len, GFP_KERNEL);
  328. if (!out_payload) {
  329. dev_dbg(dev, "Failed to allocate out_payload\n");
  330. err = -ENOMEM;
  331. goto err_out_payload;
  332. }
  333. out_payload_dma_addr = dma_map_single(dev->parent, out_payload,
  334. rpc->out.len, DMA_FROM_DEVICE);
  335. err = dma_mapping_error(dev->parent, out_payload_dma_addr);
  336. if (err) {
  337. dev_dbg(dev, "Failed to map out_payload\n");
  338. goto err_out_payload;
  339. }
  340. }
  341. cmd = (union pds_core_adminq_cmd) {
  342. .fwctl_rpc = {
  343. .opcode = PDS_FWCTL_CMD_RPC,
  344. .flags = cpu_to_le16(PDS_FWCTL_RPC_IND_REQ | PDS_FWCTL_RPC_IND_RESP),
  345. .ep = cpu_to_le32(rpc->in.ep),
  346. .op = cpu_to_le32(rpc->in.op),
  347. .req_pa = cpu_to_le64(in_payload_dma_addr),
  348. .req_sz = cpu_to_le32(rpc->in.len),
  349. .resp_pa = cpu_to_le64(out_payload_dma_addr),
  350. .resp_sz = cpu_to_le32(rpc->out.len),
  351. }
  352. };
  353. err = pds_client_adminq_cmd(pdsfc->padev, &cmd, sizeof(cmd), &comp, 0);
  354. if (err) {
  355. dev_dbg(dev, "%s: ep %d op %x req_pa %llx req_sz %d req_sg %d resp_pa %llx resp_sz %d resp_sg %d err %d\n",
  356. __func__, rpc->in.ep, rpc->in.op,
  357. cmd.fwctl_rpc.req_pa, cmd.fwctl_rpc.req_sz, cmd.fwctl_rpc.req_sg_elems,
  358. cmd.fwctl_rpc.resp_pa, cmd.fwctl_rpc.resp_sz, cmd.fwctl_rpc.resp_sg_elems,
  359. err);
  360. goto done;
  361. }
  362. dynamic_hex_dump("out ", DUMP_PREFIX_OFFSET, 16, 1, out_payload, rpc->out.len, true);
  363. if (copy_to_user(u64_to_user_ptr(rpc->out.payload), out_payload, rpc->out.len)) {
  364. dev_dbg(dev, "Failed to copy out_payload to user\n");
  365. out = ERR_PTR(-EFAULT);
  366. goto done;
  367. }
  368. rpc->out.retval = le32_to_cpu(comp.fwctl_rpc.err);
  369. *out_len = in_len;
  370. out = in;
  371. done:
  372. if (out_payload_dma_addr)
  373. dma_unmap_single(dev->parent, out_payload_dma_addr,
  374. rpc->out.len, DMA_FROM_DEVICE);
  375. err_out_payload:
  376. kfree(out_payload);
  377. if (in_payload_dma_addr)
  378. dma_unmap_single(dev->parent, in_payload_dma_addr,
  379. rpc->in.len, DMA_TO_DEVICE);
  380. err_in_payload:
  381. kfree(in_payload);
  382. if (err)
  383. return ERR_PTR(err);
  384. return out;
  385. }
  386. static const struct fwctl_ops pdsfc_ops = {
  387. .device_type = FWCTL_DEVICE_TYPE_PDS,
  388. .uctx_size = sizeof(struct pdsfc_uctx),
  389. .open_uctx = pdsfc_open_uctx,
  390. .close_uctx = pdsfc_close_uctx,
  391. .info = pdsfc_info,
  392. .fw_rpc = pdsfc_fw_rpc,
  393. };
  394. static int pdsfc_probe(struct auxiliary_device *adev,
  395. const struct auxiliary_device_id *id)
  396. {
  397. struct pds_auxiliary_dev *padev =
  398. container_of(adev, struct pds_auxiliary_dev, aux_dev);
  399. struct device *dev = &adev->dev;
  400. struct pdsfc_dev *pdsfc;
  401. int err;
  402. pdsfc = fwctl_alloc_device(&padev->vf_pdev->dev, &pdsfc_ops,
  403. struct pdsfc_dev, fwctl);
  404. if (!pdsfc)
  405. return -ENOMEM;
  406. pdsfc->padev = padev;
  407. err = pdsfc_identify(pdsfc);
  408. if (err) {
  409. fwctl_put(&pdsfc->fwctl);
  410. return dev_err_probe(dev, err, "Failed to identify device\n");
  411. }
  412. err = pdsfc_init_endpoints(pdsfc);
  413. if (err) {
  414. fwctl_put(&pdsfc->fwctl);
  415. return dev_err_probe(dev, err, "Failed to init endpoints\n");
  416. }
  417. pdsfc->caps = PDS_FWCTL_QUERY_CAP | PDS_FWCTL_SEND_CAP;
  418. err = fwctl_register(&pdsfc->fwctl);
  419. if (err) {
  420. pdsfc_free_endpoints(pdsfc);
  421. fwctl_put(&pdsfc->fwctl);
  422. return dev_err_probe(dev, err, "Failed to register device\n");
  423. }
  424. auxiliary_set_drvdata(adev, pdsfc);
  425. return 0;
  426. }
  427. static void pdsfc_remove(struct auxiliary_device *adev)
  428. {
  429. struct pdsfc_dev *pdsfc = auxiliary_get_drvdata(adev);
  430. fwctl_unregister(&pdsfc->fwctl);
  431. pdsfc_free_operations(pdsfc);
  432. pdsfc_free_endpoints(pdsfc);
  433. fwctl_put(&pdsfc->fwctl);
  434. }
  435. static const struct auxiliary_device_id pdsfc_id_table[] = {
  436. {.name = PDS_CORE_DRV_NAME "." PDS_DEV_TYPE_FWCTL_STR },
  437. {}
  438. };
  439. MODULE_DEVICE_TABLE(auxiliary, pdsfc_id_table);
  440. static struct auxiliary_driver pdsfc_driver = {
  441. .name = "pds_fwctl",
  442. .probe = pdsfc_probe,
  443. .remove = pdsfc_remove,
  444. .id_table = pdsfc_id_table,
  445. };
  446. module_auxiliary_driver(pdsfc_driver);
  447. MODULE_IMPORT_NS("FWCTL");
  448. MODULE_DESCRIPTION("pds fwctl driver");
  449. MODULE_AUTHOR("Shannon Nelson <shannon.nelson@amd.com>");
  450. MODULE_AUTHOR("Brett Creeley <brett.creeley@amd.com>");
  451. MODULE_LICENSE("GPL");