Kconfig 6.1 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menuconfig PM_DEVFREQ
  3. bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
  4. select PM_OPP
  5. help
  6. A device may have a list of frequencies and voltages available.
  7. devfreq, a generic DVFS framework can be registered for a device
  8. in order to let the governor provided to devfreq choose an
  9. operating frequency based on the device driver's policy.
  10. Each device may have its own governor and policy. Devfreq can
  11. reevaluate the device state periodically and/or based on the
  12. notification to "nb", a notifier block, of devfreq.
  13. Like some CPUs with CPUfreq, a device may have multiple clocks.
  14. However, because the clock frequencies of a single device are
  15. determined by the single device's state, an instance of devfreq
  16. is attached to a single device and returns a "representative"
  17. clock frequency of the device, which is also attached
  18. to a device by 1-to-1. The device registering devfreq takes the
  19. responsibility to "interpret" the representative frequency and
  20. to set its every clock accordingly with the "target" callback
  21. given to devfreq.
  22. When OPP is used with the devfreq device, it is recommended to
  23. register devfreq's nb to the OPP's notifier head. If OPP is
  24. used with the devfreq device, you may use OPP helper
  25. functions defined in devfreq.h.
  26. if PM_DEVFREQ
  27. comment "DEVFREQ Governors"
  28. config DEVFREQ_GOV_SIMPLE_ONDEMAND
  29. tristate "Simple Ondemand"
  30. help
  31. Chooses frequency based on the recent load on the device. Works
  32. similar as ONDEMAND governor of CPUFREQ does. A device with
  33. Simple-Ondemand should be able to provide busy/total counter
  34. values that imply the usage rate. A device may provide tuned
  35. values to the governor with data field at devfreq_add_device().
  36. config DEVFREQ_GOV_PERFORMANCE
  37. tristate "Performance"
  38. help
  39. Sets the frequency at the maximum available frequency.
  40. This governor always returns UINT_MAX as frequency so that
  41. the DEVFREQ framework returns the highest frequency available
  42. at any time.
  43. config DEVFREQ_GOV_POWERSAVE
  44. tristate "Powersave"
  45. help
  46. Sets the frequency at the minimum available frequency.
  47. This governor always returns 0 as frequency so that
  48. the DEVFREQ framework returns the lowest frequency available
  49. at any time.
  50. config DEVFREQ_GOV_USERSPACE
  51. tristate "Userspace"
  52. help
  53. Sets the frequency at the user specified one.
  54. This governor returns the user configured frequency if there
  55. has been an input to /sys/devices/.../userspace/set_freq.
  56. Otherwise, the governor does not change the frequency
  57. given at the initialization.
  58. config DEVFREQ_GOV_PASSIVE
  59. tristate "Passive"
  60. help
  61. Sets the frequency based on the frequency of its parent devfreq
  62. device. This governor does not change the frequency by itself
  63. through sysfs entries. The passive governor recommends that
  64. devfreq device uses the OPP table to get the frequency/voltage.
  65. comment "DEVFREQ Drivers"
  66. config ARM_EXYNOS_BUS_DEVFREQ
  67. tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
  68. depends on ARCH_EXYNOS || COMPILE_TEST
  69. select DEVFREQ_GOV_SIMPLE_ONDEMAND
  70. select DEVFREQ_GOV_PASSIVE
  71. select DEVFREQ_EVENT_EXYNOS_PPMU
  72. select PM_DEVFREQ_EVENT
  73. help
  74. This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
  75. Memory bus has one more group of memory bus (e.g, MIF and INT block).
  76. Each memory bus group could contain many memoby bus block. It reads
  77. PPMU counters of memory controllers by using DEVFREQ-event device
  78. and adjusts the operating frequencies and voltages with OPP support.
  79. This does not yet operate with optimal voltages.
  80. config ARM_HISI_UNCORE_DEVFREQ
  81. tristate "HiSilicon uncore DEVFREQ Driver"
  82. depends on ACPI && ACPI_PPTT && PCC
  83. select DEVFREQ_GOV_PERFORMANCE
  84. select DEVFREQ_GOV_USERSPACE
  85. help
  86. This adds a DEVFREQ driver that manages uncore frequency scaling for
  87. HiSilicon Kunpeng SoCs. This enables runtime management of uncore
  88. frequency scaling from kernel and userspace. The uncore domain
  89. contains system interconnects and L3 cache.
  90. config ARM_IMX_BUS_DEVFREQ
  91. tristate "i.MX Generic Bus DEVFREQ Driver"
  92. depends on ARCH_MXC || COMPILE_TEST
  93. select DEVFREQ_GOV_USERSPACE
  94. help
  95. This adds the generic DEVFREQ driver for i.MX interconnects. It
  96. allows adjusting NIC/NOC frequency.
  97. config ARM_IMX8M_DDRC_DEVFREQ
  98. tristate "i.MX8M DDRC DEVFREQ Driver"
  99. depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
  100. (COMPILE_TEST && HAVE_ARM_SMCCC)
  101. select DEVFREQ_GOV_USERSPACE
  102. help
  103. This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
  104. adjusting DRAM frequency.
  105. config ARM_TEGRA_DEVFREQ
  106. tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
  107. depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
  108. ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
  109. ARCH_TEGRA_210_SOC || \
  110. COMPILE_TEST
  111. depends on COMMON_CLK
  112. help
  113. This adds the DEVFREQ driver for the Tegra family of SoCs.
  114. It reads ACTMON counters of memory controllers and adjusts the
  115. operating frequencies and voltages with OPP support.
  116. config ARM_MEDIATEK_CCI_DEVFREQ
  117. tristate "MEDIATEK CCI DEVFREQ Driver"
  118. depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
  119. select DEVFREQ_GOV_PASSIVE
  120. help
  121. This adds a devfreq driver for MediaTek Cache Coherent Interconnect
  122. which is shared the same regulators with the cpu cluster. It can track
  123. buck voltages and update a proper CCI frequency. Use the notification
  124. to get the regulator status.
  125. config ARM_RK3399_DMC_DEVFREQ
  126. tristate "ARM RK3399 DMC DEVFREQ Driver"
  127. depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
  128. (COMPILE_TEST && HAVE_ARM_SMCCC)
  129. select DEVFREQ_EVENT_ROCKCHIP_DFI
  130. select DEVFREQ_GOV_SIMPLE_ONDEMAND
  131. select PM_DEVFREQ_EVENT
  132. help
  133. This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
  134. It sets the frequency for the memory controller and reads the usage counts
  135. from hardware.
  136. config ARM_SUN8I_A33_MBUS_DEVFREQ
  137. tristate "sun8i/sun50i MBUS DEVFREQ Driver"
  138. depends on ARCH_SUNXI || COMPILE_TEST
  139. depends on COMMON_CLK
  140. select DEVFREQ_GOV_SIMPLE_ONDEMAND
  141. help
  142. This adds the DEVFREQ driver for the MBUS controller in some
  143. Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
  144. source "drivers/devfreq/event/Kconfig"
  145. endif # PM_DEVFREQ