tegra-se-aes.c 52 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  3. /*
  4. * Crypto driver to handle block cipher algorithms using NVIDIA Security Engine.
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/dma-mapping.h>
  8. #include <linux/module.h>
  9. #include <linux/of_device.h>
  10. #include <linux/platform_device.h>
  11. #include <crypto/aead.h>
  12. #include <crypto/aes.h>
  13. #include <crypto/engine.h>
  14. #include <crypto/gcm.h>
  15. #include <crypto/scatterwalk.h>
  16. #include <crypto/xts.h>
  17. #include <crypto/internal/aead.h>
  18. #include <crypto/internal/hash.h>
  19. #include <crypto/internal/skcipher.h>
  20. #include "tegra-se.h"
  21. struct tegra_aes_ctx {
  22. struct tegra_se *se;
  23. u32 alg;
  24. u32 ivsize;
  25. u32 key1_id;
  26. u32 key2_id;
  27. u32 keylen;
  28. u8 key1[AES_MAX_KEY_SIZE];
  29. u8 key2[AES_MAX_KEY_SIZE];
  30. };
  31. struct tegra_aes_reqctx {
  32. struct tegra_se_datbuf datbuf;
  33. bool encrypt;
  34. u32 config;
  35. u32 crypto_config;
  36. u32 len;
  37. u32 *iv;
  38. };
  39. struct tegra_aead_ctx {
  40. struct tegra_se *se;
  41. unsigned int authsize;
  42. u32 alg;
  43. u32 key_id;
  44. u32 keylen;
  45. u8 key[AES_MAX_KEY_SIZE];
  46. };
  47. struct tegra_aead_reqctx {
  48. struct tegra_se_datbuf inbuf;
  49. struct tegra_se_datbuf outbuf;
  50. struct scatterlist *src_sg;
  51. struct scatterlist *dst_sg;
  52. unsigned int assoclen;
  53. unsigned int cryptlen;
  54. unsigned int authsize;
  55. bool encrypt;
  56. u32 crypto_config;
  57. u32 config;
  58. u32 key_id;
  59. u32 iv[4];
  60. u8 authdata[16];
  61. };
  62. struct tegra_cmac_ctx {
  63. struct tegra_se *se;
  64. unsigned int alg;
  65. u32 key_id;
  66. u32 keylen;
  67. u8 key[AES_MAX_KEY_SIZE];
  68. struct crypto_shash *fallback_tfm;
  69. };
  70. struct tegra_cmac_reqctx {
  71. struct scatterlist *src_sg;
  72. struct tegra_se_datbuf datbuf;
  73. struct tegra_se_datbuf residue;
  74. unsigned int total_len;
  75. unsigned int blk_size;
  76. unsigned int task;
  77. u32 crypto_config;
  78. u32 config;
  79. u32 key_id;
  80. u32 *iv;
  81. u32 result[CMAC_RESULT_REG_COUNT];
  82. };
  83. /* increment counter (128-bit int) */
  84. static void ctr_iv_inc(__u8 *counter, __u8 bits, __u32 nums)
  85. {
  86. do {
  87. --bits;
  88. nums += counter[bits];
  89. counter[bits] = nums & 0xff;
  90. nums >>= 8;
  91. } while (bits && nums);
  92. }
  93. static void tegra_cbc_iv_copyback(struct skcipher_request *req, struct tegra_aes_ctx *ctx)
  94. {
  95. struct tegra_aes_reqctx *rctx = skcipher_request_ctx(req);
  96. unsigned int offset;
  97. offset = req->cryptlen - ctx->ivsize;
  98. if (rctx->encrypt)
  99. memcpy(req->iv, rctx->datbuf.buf + offset, ctx->ivsize);
  100. else
  101. scatterwalk_map_and_copy(req->iv, req->src, offset, ctx->ivsize, 0);
  102. }
  103. static void tegra_aes_update_iv(struct skcipher_request *req, struct tegra_aes_ctx *ctx)
  104. {
  105. int num;
  106. if (ctx->alg == SE_ALG_CBC) {
  107. tegra_cbc_iv_copyback(req, ctx);
  108. } else if (ctx->alg == SE_ALG_CTR) {
  109. num = req->cryptlen / ctx->ivsize;
  110. if (req->cryptlen % ctx->ivsize)
  111. num++;
  112. ctr_iv_inc(req->iv, ctx->ivsize, num);
  113. }
  114. }
  115. static int tegra234_aes_crypto_cfg(u32 alg, bool encrypt)
  116. {
  117. switch (alg) {
  118. case SE_ALG_CMAC:
  119. case SE_ALG_GMAC:
  120. case SE_ALG_GCM:
  121. case SE_ALG_GCM_FINAL:
  122. return 0;
  123. case SE_ALG_CBC:
  124. if (encrypt)
  125. return SE_CRYPTO_CFG_CBC_ENCRYPT;
  126. else
  127. return SE_CRYPTO_CFG_CBC_DECRYPT;
  128. case SE_ALG_ECB:
  129. if (encrypt)
  130. return SE_CRYPTO_CFG_ECB_ENCRYPT;
  131. else
  132. return SE_CRYPTO_CFG_ECB_DECRYPT;
  133. case SE_ALG_XTS:
  134. if (encrypt)
  135. return SE_CRYPTO_CFG_XTS_ENCRYPT;
  136. else
  137. return SE_CRYPTO_CFG_XTS_DECRYPT;
  138. case SE_ALG_CTR:
  139. return SE_CRYPTO_CFG_CTR;
  140. case SE_ALG_CBC_MAC:
  141. return SE_CRYPTO_CFG_CBC_MAC;
  142. default:
  143. break;
  144. }
  145. return -EINVAL;
  146. }
  147. static int tegra234_aes_cfg(u32 alg, bool encrypt)
  148. {
  149. switch (alg) {
  150. case SE_ALG_CBC:
  151. case SE_ALG_ECB:
  152. case SE_ALG_XTS:
  153. case SE_ALG_CTR:
  154. if (encrypt)
  155. return SE_CFG_AES_ENCRYPT;
  156. else
  157. return SE_CFG_AES_DECRYPT;
  158. case SE_ALG_GMAC:
  159. if (encrypt)
  160. return SE_CFG_GMAC_ENCRYPT;
  161. else
  162. return SE_CFG_GMAC_DECRYPT;
  163. case SE_ALG_GCM:
  164. if (encrypt)
  165. return SE_CFG_GCM_ENCRYPT;
  166. else
  167. return SE_CFG_GCM_DECRYPT;
  168. case SE_ALG_GCM_FINAL:
  169. if (encrypt)
  170. return SE_CFG_GCM_FINAL_ENCRYPT;
  171. else
  172. return SE_CFG_GCM_FINAL_DECRYPT;
  173. case SE_ALG_CMAC:
  174. return SE_CFG_CMAC;
  175. case SE_ALG_CBC_MAC:
  176. return SE_AES_ENC_ALG_AES_ENC |
  177. SE_AES_DST_HASH_REG;
  178. }
  179. return -EINVAL;
  180. }
  181. static unsigned int tegra_aes_prep_cmd(struct tegra_aes_ctx *ctx,
  182. struct tegra_aes_reqctx *rctx)
  183. {
  184. unsigned int data_count, res_bits, i = 0, j;
  185. struct tegra_se *se = ctx->se;
  186. u32 *cpuvaddr = se->cmdbuf->addr;
  187. dma_addr_t addr = rctx->datbuf.addr;
  188. data_count = rctx->len / AES_BLOCK_SIZE;
  189. res_bits = (rctx->len % AES_BLOCK_SIZE) * 8;
  190. /*
  191. * Hardware processes data_count + 1 blocks.
  192. * Reduce 1 block if there is no residue
  193. */
  194. if (!res_bits)
  195. data_count--;
  196. if (rctx->iv) {
  197. cpuvaddr[i++] = host1x_opcode_setpayload(SE_CRYPTO_CTR_REG_COUNT);
  198. cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->linear_ctr);
  199. for (j = 0; j < SE_CRYPTO_CTR_REG_COUNT; j++)
  200. cpuvaddr[i++] = rctx->iv[j];
  201. }
  202. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  203. cpuvaddr[i++] = SE_LAST_BLOCK_VAL(data_count) |
  204. SE_LAST_BLOCK_RES_BITS(res_bits);
  205. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  206. cpuvaddr[i++] = rctx->config;
  207. cpuvaddr[i++] = rctx->crypto_config;
  208. /* Source address setting */
  209. cpuvaddr[i++] = lower_32_bits(addr);
  210. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(addr)) | SE_ADDR_HI_SZ(rctx->len);
  211. /* Destination address setting */
  212. cpuvaddr[i++] = lower_32_bits(addr);
  213. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(addr)) |
  214. SE_ADDR_HI_SZ(rctx->len);
  215. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  216. cpuvaddr[i++] = SE_AES_OP_WRSTALL | SE_AES_OP_LASTBUF |
  217. SE_AES_OP_START;
  218. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  219. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  220. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  221. dev_dbg(se->dev, "cfg %#x crypto cfg %#x\n", rctx->config, rctx->crypto_config);
  222. return i;
  223. }
  224. static int tegra_aes_do_one_req(struct crypto_engine *engine, void *areq)
  225. {
  226. struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
  227. struct tegra_aes_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
  228. struct tegra_aes_reqctx *rctx = skcipher_request_ctx(req);
  229. struct tegra_se *se = ctx->se;
  230. unsigned int cmdlen, key1_id, key2_id;
  231. int ret;
  232. rctx->iv = (ctx->alg == SE_ALG_ECB) ? NULL : (u32 *)req->iv;
  233. rctx->len = req->cryptlen;
  234. key1_id = ctx->key1_id;
  235. key2_id = ctx->key2_id;
  236. /* Pad input to AES Block size */
  237. if (ctx->alg != SE_ALG_XTS) {
  238. if (rctx->len % AES_BLOCK_SIZE)
  239. rctx->len += AES_BLOCK_SIZE - (rctx->len % AES_BLOCK_SIZE);
  240. }
  241. rctx->datbuf.size = rctx->len;
  242. rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->datbuf.size,
  243. &rctx->datbuf.addr, GFP_KERNEL);
  244. if (!rctx->datbuf.buf) {
  245. ret = -ENOMEM;
  246. goto out_finalize;
  247. }
  248. scatterwalk_map_and_copy(rctx->datbuf.buf, req->src, 0, req->cryptlen, 0);
  249. rctx->config = tegra234_aes_cfg(ctx->alg, rctx->encrypt);
  250. rctx->crypto_config = tegra234_aes_crypto_cfg(ctx->alg, rctx->encrypt);
  251. if (!key1_id) {
  252. ret = tegra_key_submit_reserved_aes(ctx->se, ctx->key1,
  253. ctx->keylen, ctx->alg, &key1_id);
  254. if (ret)
  255. goto out;
  256. }
  257. rctx->crypto_config |= SE_AES_KEY_INDEX(key1_id);
  258. if (ctx->alg == SE_ALG_XTS) {
  259. if (!key2_id) {
  260. ret = tegra_key_submit_reserved_xts(ctx->se, ctx->key2,
  261. ctx->keylen, ctx->alg, &key2_id);
  262. if (ret)
  263. goto out;
  264. }
  265. rctx->crypto_config |= SE_AES_KEY2_INDEX(key2_id);
  266. }
  267. /* Prepare the command and submit for execution */
  268. cmdlen = tegra_aes_prep_cmd(ctx, rctx);
  269. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  270. /* Copy the result */
  271. tegra_aes_update_iv(req, ctx);
  272. scatterwalk_map_and_copy(rctx->datbuf.buf, req->dst, 0, req->cryptlen, 1);
  273. out:
  274. /* Free the buffer */
  275. dma_free_coherent(ctx->se->dev, rctx->datbuf.size,
  276. rctx->datbuf.buf, rctx->datbuf.addr);
  277. if (tegra_key_is_reserved(key1_id))
  278. tegra_key_invalidate_reserved(ctx->se, key1_id, ctx->alg);
  279. if (tegra_key_is_reserved(key2_id))
  280. tegra_key_invalidate_reserved(ctx->se, key2_id, ctx->alg);
  281. out_finalize:
  282. crypto_finalize_skcipher_request(se->engine, req, ret);
  283. return 0;
  284. }
  285. static int tegra_aes_cra_init(struct crypto_skcipher *tfm)
  286. {
  287. struct tegra_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
  288. struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
  289. struct tegra_se_alg *se_alg;
  290. const char *algname;
  291. int ret;
  292. se_alg = container_of(alg, struct tegra_se_alg, alg.skcipher.base);
  293. crypto_skcipher_set_reqsize(tfm, sizeof(struct tegra_aes_reqctx));
  294. ctx->ivsize = crypto_skcipher_ivsize(tfm);
  295. ctx->se = se_alg->se_dev;
  296. ctx->key1_id = 0;
  297. ctx->key2_id = 0;
  298. ctx->keylen = 0;
  299. algname = crypto_tfm_alg_name(&tfm->base);
  300. ret = se_algname_to_algid(algname);
  301. if (ret < 0) {
  302. dev_err(ctx->se->dev, "invalid algorithm\n");
  303. return ret;
  304. }
  305. ctx->alg = ret;
  306. return 0;
  307. }
  308. static void tegra_aes_cra_exit(struct crypto_skcipher *tfm)
  309. {
  310. struct tegra_aes_ctx *ctx = crypto_tfm_ctx(&tfm->base);
  311. if (ctx->key1_id)
  312. tegra_key_invalidate(ctx->se, ctx->key1_id, ctx->alg);
  313. if (ctx->key2_id)
  314. tegra_key_invalidate(ctx->se, ctx->key2_id, ctx->alg);
  315. }
  316. static int tegra_aes_setkey(struct crypto_skcipher *tfm,
  317. const u8 *key, u32 keylen)
  318. {
  319. struct tegra_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
  320. int ret;
  321. if (aes_check_keylen(keylen)) {
  322. dev_dbg(ctx->se->dev, "invalid key length (%d)\n", keylen);
  323. return -EINVAL;
  324. }
  325. ret = tegra_key_submit(ctx->se, key, keylen, ctx->alg, &ctx->key1_id);
  326. if (ret) {
  327. ctx->keylen = keylen;
  328. memcpy(ctx->key1, key, keylen);
  329. }
  330. return 0;
  331. }
  332. static int tegra_xts_setkey(struct crypto_skcipher *tfm,
  333. const u8 *key, u32 keylen)
  334. {
  335. struct tegra_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
  336. u32 len = keylen / 2;
  337. int ret;
  338. ret = xts_verify_key(tfm, key, keylen);
  339. if (ret || aes_check_keylen(len)) {
  340. dev_dbg(ctx->se->dev, "invalid key length (%d)\n", keylen);
  341. return -EINVAL;
  342. }
  343. ret = tegra_key_submit(ctx->se, key, len,
  344. ctx->alg, &ctx->key1_id);
  345. if (ret) {
  346. ctx->keylen = len;
  347. memcpy(ctx->key1, key, len);
  348. }
  349. ret = tegra_key_submit(ctx->se, key + len, len,
  350. ctx->alg, &ctx->key2_id);
  351. if (ret) {
  352. ctx->keylen = len;
  353. memcpy(ctx->key2, key + len, len);
  354. }
  355. return 0;
  356. }
  357. static int tegra_aes_kac_manifest(u32 user, u32 alg, u32 keylen)
  358. {
  359. int manifest;
  360. manifest = SE_KAC_USER_NS;
  361. switch (alg) {
  362. case SE_ALG_CBC:
  363. case SE_ALG_ECB:
  364. case SE_ALG_CTR:
  365. manifest |= SE_KAC_ENC;
  366. break;
  367. case SE_ALG_XTS:
  368. manifest |= SE_KAC_XTS;
  369. break;
  370. case SE_ALG_GCM:
  371. manifest |= SE_KAC_GCM;
  372. break;
  373. case SE_ALG_CMAC:
  374. manifest |= SE_KAC_CMAC;
  375. break;
  376. case SE_ALG_CBC_MAC:
  377. manifest |= SE_KAC_ENC;
  378. break;
  379. default:
  380. return -EINVAL;
  381. }
  382. switch (keylen) {
  383. case AES_KEYSIZE_128:
  384. manifest |= SE_KAC_SIZE_128;
  385. break;
  386. case AES_KEYSIZE_192:
  387. manifest |= SE_KAC_SIZE_192;
  388. break;
  389. case AES_KEYSIZE_256:
  390. manifest |= SE_KAC_SIZE_256;
  391. break;
  392. default:
  393. return -EINVAL;
  394. }
  395. return manifest;
  396. }
  397. static int tegra_aes_crypt(struct skcipher_request *req, bool encrypt)
  398. {
  399. struct crypto_skcipher *tfm;
  400. struct tegra_aes_ctx *ctx;
  401. struct tegra_aes_reqctx *rctx;
  402. tfm = crypto_skcipher_reqtfm(req);
  403. ctx = crypto_skcipher_ctx(tfm);
  404. rctx = skcipher_request_ctx(req);
  405. if (ctx->alg != SE_ALG_XTS) {
  406. if (!IS_ALIGNED(req->cryptlen, crypto_skcipher_blocksize(tfm))) {
  407. dev_dbg(ctx->se->dev, "invalid length (%d)", req->cryptlen);
  408. return -EINVAL;
  409. }
  410. } else if (req->cryptlen < XTS_BLOCK_SIZE) {
  411. dev_dbg(ctx->se->dev, "invalid length (%d)", req->cryptlen);
  412. return -EINVAL;
  413. }
  414. if (!req->cryptlen)
  415. return 0;
  416. rctx->encrypt = encrypt;
  417. return crypto_transfer_skcipher_request_to_engine(ctx->se->engine, req);
  418. }
  419. static int tegra_aes_encrypt(struct skcipher_request *req)
  420. {
  421. return tegra_aes_crypt(req, true);
  422. }
  423. static int tegra_aes_decrypt(struct skcipher_request *req)
  424. {
  425. return tegra_aes_crypt(req, false);
  426. }
  427. static struct tegra_se_alg tegra_aes_algs[] = {
  428. {
  429. .alg.skcipher.op.do_one_request = tegra_aes_do_one_req,
  430. .alg.skcipher.base = {
  431. .init = tegra_aes_cra_init,
  432. .exit = tegra_aes_cra_exit,
  433. .setkey = tegra_aes_setkey,
  434. .encrypt = tegra_aes_encrypt,
  435. .decrypt = tegra_aes_decrypt,
  436. .min_keysize = AES_MIN_KEY_SIZE,
  437. .max_keysize = AES_MAX_KEY_SIZE,
  438. .ivsize = AES_BLOCK_SIZE,
  439. .base = {
  440. .cra_name = "cbc(aes)",
  441. .cra_driver_name = "cbc-aes-tegra",
  442. .cra_priority = 500,
  443. .cra_flags = CRYPTO_ALG_ASYNC,
  444. .cra_blocksize = AES_BLOCK_SIZE,
  445. .cra_ctxsize = sizeof(struct tegra_aes_ctx),
  446. .cra_alignmask = 0xf,
  447. .cra_module = THIS_MODULE,
  448. },
  449. }
  450. }, {
  451. .alg.skcipher.op.do_one_request = tegra_aes_do_one_req,
  452. .alg.skcipher.base = {
  453. .init = tegra_aes_cra_init,
  454. .exit = tegra_aes_cra_exit,
  455. .setkey = tegra_aes_setkey,
  456. .encrypt = tegra_aes_encrypt,
  457. .decrypt = tegra_aes_decrypt,
  458. .min_keysize = AES_MIN_KEY_SIZE,
  459. .max_keysize = AES_MAX_KEY_SIZE,
  460. .base = {
  461. .cra_name = "ecb(aes)",
  462. .cra_driver_name = "ecb-aes-tegra",
  463. .cra_priority = 500,
  464. .cra_flags = CRYPTO_ALG_ASYNC,
  465. .cra_blocksize = AES_BLOCK_SIZE,
  466. .cra_ctxsize = sizeof(struct tegra_aes_ctx),
  467. .cra_alignmask = 0xf,
  468. .cra_module = THIS_MODULE,
  469. },
  470. }
  471. }, {
  472. .alg.skcipher.op.do_one_request = tegra_aes_do_one_req,
  473. .alg.skcipher.base = {
  474. .init = tegra_aes_cra_init,
  475. .exit = tegra_aes_cra_exit,
  476. .setkey = tegra_aes_setkey,
  477. .encrypt = tegra_aes_encrypt,
  478. .decrypt = tegra_aes_decrypt,
  479. .min_keysize = AES_MIN_KEY_SIZE,
  480. .max_keysize = AES_MAX_KEY_SIZE,
  481. .ivsize = AES_BLOCK_SIZE,
  482. .base = {
  483. .cra_name = "ctr(aes)",
  484. .cra_driver_name = "ctr-aes-tegra",
  485. .cra_priority = 500,
  486. .cra_flags = CRYPTO_ALG_ASYNC,
  487. .cra_blocksize = 1,
  488. .cra_ctxsize = sizeof(struct tegra_aes_ctx),
  489. .cra_alignmask = 0xf,
  490. .cra_module = THIS_MODULE,
  491. },
  492. }
  493. }, {
  494. .alg.skcipher.op.do_one_request = tegra_aes_do_one_req,
  495. .alg.skcipher.base = {
  496. .init = tegra_aes_cra_init,
  497. .exit = tegra_aes_cra_exit,
  498. .setkey = tegra_xts_setkey,
  499. .encrypt = tegra_aes_encrypt,
  500. .decrypt = tegra_aes_decrypt,
  501. .min_keysize = 2 * AES_MIN_KEY_SIZE,
  502. .max_keysize = 2 * AES_MAX_KEY_SIZE,
  503. .ivsize = AES_BLOCK_SIZE,
  504. .base = {
  505. .cra_name = "xts(aes)",
  506. .cra_driver_name = "xts-aes-tegra",
  507. .cra_priority = 500,
  508. .cra_flags = CRYPTO_ALG_ASYNC,
  509. .cra_blocksize = AES_BLOCK_SIZE,
  510. .cra_ctxsize = sizeof(struct tegra_aes_ctx),
  511. .cra_alignmask = (__alignof__(u64) - 1),
  512. .cra_module = THIS_MODULE,
  513. },
  514. }
  515. },
  516. };
  517. static unsigned int tegra_gmac_prep_cmd(struct tegra_aead_ctx *ctx,
  518. struct tegra_aead_reqctx *rctx)
  519. {
  520. unsigned int data_count, res_bits, i = 0;
  521. struct tegra_se *se = ctx->se;
  522. u32 *cpuvaddr = se->cmdbuf->addr;
  523. data_count = (rctx->assoclen / AES_BLOCK_SIZE);
  524. res_bits = (rctx->assoclen % AES_BLOCK_SIZE) * 8;
  525. /*
  526. * Hardware processes data_count + 1 blocks.
  527. * Reduce 1 block if there is no residue
  528. */
  529. if (!res_bits)
  530. data_count--;
  531. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  532. cpuvaddr[i++] = SE_LAST_BLOCK_VAL(data_count) |
  533. SE_LAST_BLOCK_RES_BITS(res_bits);
  534. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 4);
  535. cpuvaddr[i++] = rctx->config;
  536. cpuvaddr[i++] = rctx->crypto_config;
  537. cpuvaddr[i++] = lower_32_bits(rctx->inbuf.addr);
  538. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->inbuf.addr)) |
  539. SE_ADDR_HI_SZ(rctx->assoclen);
  540. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  541. cpuvaddr[i++] = SE_AES_OP_WRSTALL | SE_AES_OP_FINAL |
  542. SE_AES_OP_INIT | SE_AES_OP_LASTBUF |
  543. SE_AES_OP_START;
  544. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  545. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  546. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  547. return i;
  548. }
  549. static unsigned int tegra_gcm_crypt_prep_cmd(struct tegra_aead_ctx *ctx,
  550. struct tegra_aead_reqctx *rctx)
  551. {
  552. unsigned int data_count, res_bits, i = 0, j;
  553. struct tegra_se *se = ctx->se;
  554. u32 *cpuvaddr = se->cmdbuf->addr, op;
  555. data_count = (rctx->cryptlen / AES_BLOCK_SIZE);
  556. res_bits = (rctx->cryptlen % AES_BLOCK_SIZE) * 8;
  557. op = SE_AES_OP_WRSTALL | SE_AES_OP_FINAL |
  558. SE_AES_OP_LASTBUF | SE_AES_OP_START;
  559. /*
  560. * If there is no assoc data,
  561. * this will be the init command
  562. */
  563. if (!rctx->assoclen)
  564. op |= SE_AES_OP_INIT;
  565. /*
  566. * Hardware processes data_count + 1 blocks.
  567. * Reduce 1 block if there is no residue
  568. */
  569. if (!res_bits)
  570. data_count--;
  571. cpuvaddr[i++] = host1x_opcode_setpayload(SE_CRYPTO_CTR_REG_COUNT);
  572. cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->linear_ctr);
  573. for (j = 0; j < SE_CRYPTO_CTR_REG_COUNT; j++)
  574. cpuvaddr[i++] = rctx->iv[j];
  575. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  576. cpuvaddr[i++] = SE_LAST_BLOCK_VAL(data_count) |
  577. SE_LAST_BLOCK_RES_BITS(res_bits);
  578. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  579. cpuvaddr[i++] = rctx->config;
  580. cpuvaddr[i++] = rctx->crypto_config;
  581. /* Source Address */
  582. cpuvaddr[i++] = lower_32_bits(rctx->inbuf.addr);
  583. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->inbuf.addr)) |
  584. SE_ADDR_HI_SZ(rctx->cryptlen);
  585. /* Destination Address */
  586. cpuvaddr[i++] = lower_32_bits(rctx->outbuf.addr);
  587. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->outbuf.addr)) |
  588. SE_ADDR_HI_SZ(rctx->cryptlen);
  589. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  590. cpuvaddr[i++] = op;
  591. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  592. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  593. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  594. dev_dbg(se->dev, "cfg %#x crypto cfg %#x\n", rctx->config, rctx->crypto_config);
  595. return i;
  596. }
  597. static int tegra_gcm_prep_final_cmd(struct tegra_se *se, u32 *cpuvaddr,
  598. struct tegra_aead_reqctx *rctx)
  599. {
  600. unsigned int i = 0, j;
  601. u32 op;
  602. op = SE_AES_OP_WRSTALL | SE_AES_OP_FINAL |
  603. SE_AES_OP_LASTBUF | SE_AES_OP_START;
  604. /*
  605. * Set init for zero sized vector
  606. */
  607. if (!rctx->assoclen && !rctx->cryptlen)
  608. op |= SE_AES_OP_INIT;
  609. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->aad_len, 2);
  610. cpuvaddr[i++] = rctx->assoclen * 8;
  611. cpuvaddr[i++] = 0;
  612. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->cryp_msg_len, 2);
  613. cpuvaddr[i++] = rctx->cryptlen * 8;
  614. cpuvaddr[i++] = 0;
  615. cpuvaddr[i++] = host1x_opcode_setpayload(SE_CRYPTO_CTR_REG_COUNT);
  616. cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->linear_ctr);
  617. for (j = 0; j < SE_CRYPTO_CTR_REG_COUNT; j++)
  618. cpuvaddr[i++] = rctx->iv[j];
  619. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  620. cpuvaddr[i++] = rctx->config;
  621. cpuvaddr[i++] = rctx->crypto_config;
  622. cpuvaddr[i++] = 0;
  623. cpuvaddr[i++] = 0;
  624. /* Destination Address */
  625. cpuvaddr[i++] = lower_32_bits(rctx->outbuf.addr);
  626. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->outbuf.addr)) |
  627. SE_ADDR_HI_SZ(0x10); /* HW always generates 128-bit tag */
  628. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  629. cpuvaddr[i++] = op;
  630. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  631. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  632. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  633. dev_dbg(se->dev, "cfg %#x crypto cfg %#x\n", rctx->config, rctx->crypto_config);
  634. return i;
  635. }
  636. static int tegra_gcm_do_gmac(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  637. {
  638. struct tegra_se *se = ctx->se;
  639. unsigned int cmdlen;
  640. scatterwalk_map_and_copy(rctx->inbuf.buf,
  641. rctx->src_sg, 0, rctx->assoclen, 0);
  642. rctx->config = tegra234_aes_cfg(SE_ALG_GMAC, rctx->encrypt);
  643. rctx->crypto_config = tegra234_aes_crypto_cfg(SE_ALG_GMAC, rctx->encrypt) |
  644. SE_AES_KEY_INDEX(rctx->key_id);
  645. cmdlen = tegra_gmac_prep_cmd(ctx, rctx);
  646. return tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  647. }
  648. static int tegra_gcm_do_crypt(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  649. {
  650. struct tegra_se *se = ctx->se;
  651. int cmdlen, ret;
  652. scatterwalk_map_and_copy(rctx->inbuf.buf, rctx->src_sg,
  653. rctx->assoclen, rctx->cryptlen, 0);
  654. rctx->config = tegra234_aes_cfg(SE_ALG_GCM, rctx->encrypt);
  655. rctx->crypto_config = tegra234_aes_crypto_cfg(SE_ALG_GCM, rctx->encrypt) |
  656. SE_AES_KEY_INDEX(rctx->key_id);
  657. /* Prepare command and submit */
  658. cmdlen = tegra_gcm_crypt_prep_cmd(ctx, rctx);
  659. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  660. if (ret)
  661. return ret;
  662. /* Copy the result */
  663. scatterwalk_map_and_copy(rctx->outbuf.buf, rctx->dst_sg,
  664. rctx->assoclen, rctx->cryptlen, 1);
  665. return 0;
  666. }
  667. static int tegra_gcm_do_final(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  668. {
  669. struct tegra_se *se = ctx->se;
  670. u32 *cpuvaddr = se->cmdbuf->addr;
  671. int cmdlen, ret, offset;
  672. rctx->config = tegra234_aes_cfg(SE_ALG_GCM_FINAL, rctx->encrypt);
  673. rctx->crypto_config = tegra234_aes_crypto_cfg(SE_ALG_GCM_FINAL, rctx->encrypt) |
  674. SE_AES_KEY_INDEX(rctx->key_id);
  675. /* Prepare command and submit */
  676. cmdlen = tegra_gcm_prep_final_cmd(se, cpuvaddr, rctx);
  677. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  678. if (ret)
  679. return ret;
  680. if (rctx->encrypt) {
  681. /* Copy the result */
  682. offset = rctx->assoclen + rctx->cryptlen;
  683. scatterwalk_map_and_copy(rctx->outbuf.buf, rctx->dst_sg,
  684. offset, rctx->authsize, 1);
  685. }
  686. return 0;
  687. }
  688. static int tegra_gcm_do_verify(struct tegra_se *se, struct tegra_aead_reqctx *rctx)
  689. {
  690. unsigned int offset;
  691. u8 mac[16];
  692. offset = rctx->assoclen + rctx->cryptlen;
  693. scatterwalk_map_and_copy(mac, rctx->src_sg, offset, rctx->authsize, 0);
  694. if (crypto_memneq(rctx->outbuf.buf, mac, rctx->authsize))
  695. return -EBADMSG;
  696. return 0;
  697. }
  698. static inline int tegra_ccm_check_iv(const u8 *iv)
  699. {
  700. /* iv[0] gives value of q-1
  701. * 2 <= q <= 8 as per NIST 800-38C notation
  702. * 2 <= L <= 8, so 1 <= L' <= 7. as per rfc 3610 notation
  703. */
  704. if (iv[0] < 1 || iv[0] > 7) {
  705. pr_debug("ccm_check_iv failed %d\n", iv[0]);
  706. return -EINVAL;
  707. }
  708. return 0;
  709. }
  710. static unsigned int tegra_cbcmac_prep_cmd(struct tegra_aead_ctx *ctx,
  711. struct tegra_aead_reqctx *rctx)
  712. {
  713. unsigned int data_count, i = 0;
  714. struct tegra_se *se = ctx->se;
  715. u32 *cpuvaddr = se->cmdbuf->addr;
  716. data_count = (rctx->inbuf.size / AES_BLOCK_SIZE) - 1;
  717. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  718. cpuvaddr[i++] = SE_LAST_BLOCK_VAL(data_count);
  719. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  720. cpuvaddr[i++] = rctx->config;
  721. cpuvaddr[i++] = rctx->crypto_config;
  722. cpuvaddr[i++] = lower_32_bits(rctx->inbuf.addr);
  723. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->inbuf.addr)) |
  724. SE_ADDR_HI_SZ(rctx->inbuf.size);
  725. cpuvaddr[i++] = lower_32_bits(rctx->outbuf.addr);
  726. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->outbuf.addr)) |
  727. SE_ADDR_HI_SZ(0x10); /* HW always generates 128 bit tag */
  728. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  729. cpuvaddr[i++] = SE_AES_OP_WRSTALL |
  730. SE_AES_OP_LASTBUF | SE_AES_OP_START;
  731. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  732. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  733. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  734. return i;
  735. }
  736. static unsigned int tegra_ctr_prep_cmd(struct tegra_aead_ctx *ctx,
  737. struct tegra_aead_reqctx *rctx)
  738. {
  739. unsigned int i = 0, j;
  740. struct tegra_se *se = ctx->se;
  741. u32 *cpuvaddr = se->cmdbuf->addr;
  742. cpuvaddr[i++] = host1x_opcode_setpayload(SE_CRYPTO_CTR_REG_COUNT);
  743. cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->linear_ctr);
  744. for (j = 0; j < SE_CRYPTO_CTR_REG_COUNT; j++)
  745. cpuvaddr[i++] = rctx->iv[j];
  746. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  747. cpuvaddr[i++] = (rctx->inbuf.size / AES_BLOCK_SIZE) - 1;
  748. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  749. cpuvaddr[i++] = rctx->config;
  750. cpuvaddr[i++] = rctx->crypto_config;
  751. /* Source address setting */
  752. cpuvaddr[i++] = lower_32_bits(rctx->inbuf.addr);
  753. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->inbuf.addr)) |
  754. SE_ADDR_HI_SZ(rctx->inbuf.size);
  755. /* Destination address setting */
  756. cpuvaddr[i++] = lower_32_bits(rctx->outbuf.addr);
  757. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->outbuf.addr)) |
  758. SE_ADDR_HI_SZ(rctx->inbuf.size);
  759. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  760. cpuvaddr[i++] = SE_AES_OP_WRSTALL | SE_AES_OP_LASTBUF |
  761. SE_AES_OP_START;
  762. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  763. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  764. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  765. dev_dbg(se->dev, "cfg %#x crypto cfg %#x\n",
  766. rctx->config, rctx->crypto_config);
  767. return i;
  768. }
  769. static int tegra_ccm_do_cbcmac(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  770. {
  771. struct tegra_se *se = ctx->se;
  772. int cmdlen;
  773. rctx->config = tegra234_aes_cfg(SE_ALG_CBC_MAC, rctx->encrypt);
  774. rctx->crypto_config = tegra234_aes_crypto_cfg(SE_ALG_CBC_MAC,
  775. rctx->encrypt) |
  776. SE_AES_KEY_INDEX(rctx->key_id);
  777. /* Prepare command and submit */
  778. cmdlen = tegra_cbcmac_prep_cmd(ctx, rctx);
  779. return tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  780. }
  781. static int tegra_ccm_set_msg_len(u8 *block, unsigned int msglen, int csize)
  782. {
  783. __be32 data;
  784. memset(block, 0, csize);
  785. block += csize;
  786. if (csize >= 4)
  787. csize = 4;
  788. else if (msglen > (1 << (8 * csize)))
  789. return -EOVERFLOW;
  790. data = cpu_to_be32(msglen);
  791. memcpy(block - csize, (u8 *)&data + 4 - csize, csize);
  792. return 0;
  793. }
  794. static int tegra_ccm_format_nonce(struct tegra_aead_reqctx *rctx, u8 *nonce)
  795. {
  796. unsigned int q, t;
  797. u8 *q_ptr, *iv = (u8 *)rctx->iv;
  798. memcpy(nonce, rctx->iv, 16);
  799. /*** 1. Prepare Flags Octet ***/
  800. /* Encode t (mac length) */
  801. t = rctx->authsize;
  802. nonce[0] |= (((t - 2) / 2) << 3);
  803. /* Adata */
  804. if (rctx->assoclen)
  805. nonce[0] |= (1 << 6);
  806. /*** Encode Q - message length ***/
  807. q = iv[0] + 1;
  808. q_ptr = nonce + 16 - q;
  809. return tegra_ccm_set_msg_len(q_ptr, rctx->cryptlen, q);
  810. }
  811. static int tegra_ccm_format_adata(u8 *adata, unsigned int a)
  812. {
  813. int len = 0;
  814. /* add control info for associated data
  815. * RFC 3610 and NIST Special Publication 800-38C
  816. */
  817. if (a < 65280) {
  818. *(__be16 *)adata = cpu_to_be16(a);
  819. len = 2;
  820. } else {
  821. *(__be16 *)adata = cpu_to_be16(0xfffe);
  822. *(__be32 *)&adata[2] = cpu_to_be32(a);
  823. len = 6;
  824. }
  825. return len;
  826. }
  827. static int tegra_ccm_add_padding(u8 *buf, unsigned int len)
  828. {
  829. unsigned int padlen = 16 - (len % 16);
  830. u8 padding[16] = {0};
  831. if (padlen == 16)
  832. return 0;
  833. memcpy(buf, padding, padlen);
  834. return padlen;
  835. }
  836. static int tegra_ccm_format_blocks(struct tegra_aead_reqctx *rctx)
  837. {
  838. unsigned int alen = 0, offset = 0;
  839. u8 nonce[16], adata[16];
  840. int ret;
  841. ret = tegra_ccm_format_nonce(rctx, nonce);
  842. if (ret)
  843. return ret;
  844. memcpy(rctx->inbuf.buf, nonce, 16);
  845. offset = 16;
  846. if (rctx->assoclen) {
  847. alen = tegra_ccm_format_adata(adata, rctx->assoclen);
  848. memcpy(rctx->inbuf.buf + offset, adata, alen);
  849. offset += alen;
  850. scatterwalk_map_and_copy(rctx->inbuf.buf + offset,
  851. rctx->src_sg, 0, rctx->assoclen, 0);
  852. offset += rctx->assoclen;
  853. offset += tegra_ccm_add_padding(rctx->inbuf.buf + offset,
  854. rctx->assoclen + alen);
  855. }
  856. return offset;
  857. }
  858. static int tegra_ccm_mac_result(struct tegra_se *se, struct tegra_aead_reqctx *rctx)
  859. {
  860. u32 result[16];
  861. int i, ret;
  862. /* Read and clear Result */
  863. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  864. result[i] = readl(se->base + se->hw->regs->result + (i * 4));
  865. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  866. writel(0, se->base + se->hw->regs->result + (i * 4));
  867. if (rctx->encrypt) {
  868. memcpy(rctx->authdata, result, rctx->authsize);
  869. } else {
  870. ret = crypto_memneq(rctx->authdata, result, rctx->authsize);
  871. if (ret)
  872. return -EBADMSG;
  873. }
  874. return 0;
  875. }
  876. static int tegra_ccm_ctr_result(struct tegra_se *se, struct tegra_aead_reqctx *rctx)
  877. {
  878. /* Copy result */
  879. scatterwalk_map_and_copy(rctx->outbuf.buf + 16, rctx->dst_sg,
  880. rctx->assoclen, rctx->cryptlen, 1);
  881. if (rctx->encrypt)
  882. scatterwalk_map_and_copy(rctx->outbuf.buf, rctx->dst_sg,
  883. rctx->assoclen + rctx->cryptlen,
  884. rctx->authsize, 1);
  885. else
  886. memcpy(rctx->authdata, rctx->outbuf.buf, rctx->authsize);
  887. return 0;
  888. }
  889. static int tegra_ccm_compute_auth(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  890. {
  891. struct tegra_se *se = ctx->se;
  892. struct scatterlist *sg;
  893. int offset, ret;
  894. offset = tegra_ccm_format_blocks(rctx);
  895. if (offset < 0)
  896. return -EINVAL;
  897. /* Copy plain text to the buffer */
  898. sg = rctx->encrypt ? rctx->src_sg : rctx->dst_sg;
  899. scatterwalk_map_and_copy(rctx->inbuf.buf + offset,
  900. sg, rctx->assoclen,
  901. rctx->cryptlen, 0);
  902. offset += rctx->cryptlen;
  903. offset += tegra_ccm_add_padding(rctx->inbuf.buf + offset, rctx->cryptlen);
  904. rctx->inbuf.size = offset;
  905. ret = tegra_ccm_do_cbcmac(ctx, rctx);
  906. if (ret)
  907. return ret;
  908. return tegra_ccm_mac_result(se, rctx);
  909. }
  910. static int tegra_ccm_do_ctr(struct tegra_aead_ctx *ctx, struct tegra_aead_reqctx *rctx)
  911. {
  912. struct tegra_se *se = ctx->se;
  913. unsigned int cmdlen, offset = 0;
  914. struct scatterlist *sg = rctx->src_sg;
  915. int ret;
  916. rctx->config = tegra234_aes_cfg(SE_ALG_CTR, rctx->encrypt);
  917. rctx->crypto_config = tegra234_aes_crypto_cfg(SE_ALG_CTR, rctx->encrypt) |
  918. SE_AES_KEY_INDEX(rctx->key_id);
  919. /* Copy authdata in the top of buffer for encryption/decryption */
  920. if (rctx->encrypt)
  921. memcpy(rctx->inbuf.buf, rctx->authdata, rctx->authsize);
  922. else
  923. scatterwalk_map_and_copy(rctx->inbuf.buf, sg,
  924. rctx->assoclen + rctx->cryptlen,
  925. rctx->authsize, 0);
  926. offset += rctx->authsize;
  927. offset += tegra_ccm_add_padding(rctx->inbuf.buf + offset, rctx->authsize);
  928. /* If there is no cryptlen, proceed to submit the task */
  929. if (rctx->cryptlen) {
  930. scatterwalk_map_and_copy(rctx->inbuf.buf + offset, sg,
  931. rctx->assoclen, rctx->cryptlen, 0);
  932. offset += rctx->cryptlen;
  933. offset += tegra_ccm_add_padding(rctx->inbuf.buf + offset, rctx->cryptlen);
  934. }
  935. rctx->inbuf.size = offset;
  936. /* Prepare command and submit */
  937. cmdlen = tegra_ctr_prep_cmd(ctx, rctx);
  938. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  939. if (ret)
  940. return ret;
  941. return tegra_ccm_ctr_result(se, rctx);
  942. }
  943. static int tegra_ccm_crypt_init(struct aead_request *req, struct tegra_se *se,
  944. struct tegra_aead_reqctx *rctx)
  945. {
  946. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  947. u8 *iv = (u8 *)rctx->iv;
  948. int ret, i;
  949. rctx->src_sg = req->src;
  950. rctx->dst_sg = req->dst;
  951. rctx->assoclen = req->assoclen;
  952. rctx->authsize = crypto_aead_authsize(tfm);
  953. if (rctx->encrypt)
  954. rctx->cryptlen = req->cryptlen;
  955. else
  956. rctx->cryptlen = req->cryptlen - rctx->authsize;
  957. memcpy(iv, req->iv, 16);
  958. ret = tegra_ccm_check_iv(iv);
  959. if (ret)
  960. return ret;
  961. /* Note: rfc 3610 and NIST 800-38C require counter (ctr_0) of
  962. * zero to encrypt auth tag.
  963. * req->iv has the formatted ctr_0 (i.e. Flags || N || 0).
  964. */
  965. memset(iv + 15 - iv[0], 0, iv[0] + 1);
  966. /* Clear any previous result */
  967. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  968. writel(0, se->base + se->hw->regs->result + (i * 4));
  969. return 0;
  970. }
  971. static int tegra_ccm_do_one_req(struct crypto_engine *engine, void *areq)
  972. {
  973. struct aead_request *req = container_of(areq, struct aead_request, base);
  974. struct tegra_aead_reqctx *rctx = aead_request_ctx(req);
  975. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  976. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  977. struct tegra_se *se = ctx->se;
  978. int ret;
  979. ret = tegra_ccm_crypt_init(req, se, rctx);
  980. if (ret)
  981. goto out_finalize;
  982. rctx->key_id = ctx->key_id;
  983. /* Allocate buffers required */
  984. rctx->inbuf.size = rctx->assoclen + rctx->authsize + rctx->cryptlen + 100;
  985. rctx->inbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->inbuf.size,
  986. &rctx->inbuf.addr, GFP_KERNEL);
  987. if (!rctx->inbuf.buf)
  988. goto out_finalize;
  989. rctx->outbuf.size = rctx->assoclen + rctx->authsize + rctx->cryptlen + 100;
  990. rctx->outbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->outbuf.size,
  991. &rctx->outbuf.addr, GFP_KERNEL);
  992. if (!rctx->outbuf.buf) {
  993. ret = -ENOMEM;
  994. goto out_free_inbuf;
  995. }
  996. if (!ctx->key_id) {
  997. ret = tegra_key_submit_reserved_aes(ctx->se, ctx->key,
  998. ctx->keylen, ctx->alg, &rctx->key_id);
  999. if (ret)
  1000. goto out;
  1001. }
  1002. if (rctx->encrypt) {
  1003. /* CBC MAC Operation */
  1004. ret = tegra_ccm_compute_auth(ctx, rctx);
  1005. if (ret)
  1006. goto out;
  1007. /* CTR operation */
  1008. ret = tegra_ccm_do_ctr(ctx, rctx);
  1009. if (ret)
  1010. goto out;
  1011. } else {
  1012. /* CTR operation */
  1013. ret = tegra_ccm_do_ctr(ctx, rctx);
  1014. if (ret)
  1015. goto out;
  1016. /* CBC MAC Operation */
  1017. ret = tegra_ccm_compute_auth(ctx, rctx);
  1018. if (ret)
  1019. goto out;
  1020. }
  1021. out:
  1022. dma_free_coherent(ctx->se->dev, rctx->inbuf.size,
  1023. rctx->outbuf.buf, rctx->outbuf.addr);
  1024. out_free_inbuf:
  1025. dma_free_coherent(ctx->se->dev, rctx->outbuf.size,
  1026. rctx->inbuf.buf, rctx->inbuf.addr);
  1027. if (tegra_key_is_reserved(rctx->key_id))
  1028. tegra_key_invalidate_reserved(ctx->se, rctx->key_id, ctx->alg);
  1029. out_finalize:
  1030. crypto_finalize_aead_request(ctx->se->engine, req, ret);
  1031. return 0;
  1032. }
  1033. static int tegra_gcm_do_one_req(struct crypto_engine *engine, void *areq)
  1034. {
  1035. struct aead_request *req = container_of(areq, struct aead_request, base);
  1036. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  1037. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1038. struct tegra_aead_reqctx *rctx = aead_request_ctx(req);
  1039. int ret;
  1040. rctx->src_sg = req->src;
  1041. rctx->dst_sg = req->dst;
  1042. rctx->assoclen = req->assoclen;
  1043. rctx->authsize = crypto_aead_authsize(tfm);
  1044. if (rctx->encrypt)
  1045. rctx->cryptlen = req->cryptlen;
  1046. else
  1047. rctx->cryptlen = req->cryptlen - ctx->authsize;
  1048. memcpy(rctx->iv, req->iv, GCM_AES_IV_SIZE);
  1049. rctx->iv[3] = (1 << 24);
  1050. rctx->key_id = ctx->key_id;
  1051. /* Allocate buffers required */
  1052. rctx->inbuf.size = rctx->assoclen + rctx->authsize + rctx->cryptlen;
  1053. rctx->inbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->inbuf.size,
  1054. &rctx->inbuf.addr, GFP_KERNEL);
  1055. if (!rctx->inbuf.buf) {
  1056. ret = -ENOMEM;
  1057. goto out_finalize;
  1058. }
  1059. rctx->outbuf.size = rctx->assoclen + rctx->authsize + rctx->cryptlen;
  1060. rctx->outbuf.buf = dma_alloc_coherent(ctx->se->dev, rctx->outbuf.size,
  1061. &rctx->outbuf.addr, GFP_KERNEL);
  1062. if (!rctx->outbuf.buf) {
  1063. ret = -ENOMEM;
  1064. goto out_free_inbuf;
  1065. }
  1066. if (!ctx->key_id) {
  1067. ret = tegra_key_submit_reserved_aes(ctx->se, ctx->key,
  1068. ctx->keylen, ctx->alg, &rctx->key_id);
  1069. if (ret)
  1070. goto out;
  1071. }
  1072. /* If there is associated data perform GMAC operation */
  1073. if (rctx->assoclen) {
  1074. ret = tegra_gcm_do_gmac(ctx, rctx);
  1075. if (ret)
  1076. goto out;
  1077. }
  1078. /* GCM Encryption/Decryption operation */
  1079. if (rctx->cryptlen) {
  1080. ret = tegra_gcm_do_crypt(ctx, rctx);
  1081. if (ret)
  1082. goto out;
  1083. }
  1084. /* GCM_FINAL operation */
  1085. ret = tegra_gcm_do_final(ctx, rctx);
  1086. if (ret)
  1087. goto out;
  1088. if (!rctx->encrypt)
  1089. ret = tegra_gcm_do_verify(ctx->se, rctx);
  1090. out:
  1091. dma_free_coherent(ctx->se->dev, rctx->outbuf.size,
  1092. rctx->outbuf.buf, rctx->outbuf.addr);
  1093. out_free_inbuf:
  1094. dma_free_coherent(ctx->se->dev, rctx->inbuf.size,
  1095. rctx->inbuf.buf, rctx->inbuf.addr);
  1096. if (tegra_key_is_reserved(rctx->key_id))
  1097. tegra_key_invalidate_reserved(ctx->se, rctx->key_id, ctx->alg);
  1098. out_finalize:
  1099. crypto_finalize_aead_request(ctx->se->engine, req, ret);
  1100. return 0;
  1101. }
  1102. static int tegra_aead_cra_init(struct crypto_aead *tfm)
  1103. {
  1104. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1105. struct aead_alg *alg = crypto_aead_alg(tfm);
  1106. struct tegra_se_alg *se_alg;
  1107. const char *algname;
  1108. int ret;
  1109. algname = crypto_tfm_alg_name(&tfm->base);
  1110. se_alg = container_of(alg, struct tegra_se_alg, alg.aead.base);
  1111. crypto_aead_set_reqsize(tfm, sizeof(struct tegra_aead_reqctx));
  1112. ctx->se = se_alg->se_dev;
  1113. ctx->key_id = 0;
  1114. ctx->keylen = 0;
  1115. ret = se_algname_to_algid(algname);
  1116. if (ret < 0) {
  1117. dev_err(ctx->se->dev, "invalid algorithm\n");
  1118. return ret;
  1119. }
  1120. ctx->alg = ret;
  1121. return 0;
  1122. }
  1123. static int tegra_ccm_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
  1124. {
  1125. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1126. switch (authsize) {
  1127. case 4:
  1128. case 6:
  1129. case 8:
  1130. case 10:
  1131. case 12:
  1132. case 14:
  1133. case 16:
  1134. break;
  1135. default:
  1136. return -EINVAL;
  1137. }
  1138. ctx->authsize = authsize;
  1139. return 0;
  1140. }
  1141. static int tegra_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
  1142. {
  1143. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1144. int ret;
  1145. ret = crypto_gcm_check_authsize(authsize);
  1146. if (ret)
  1147. return ret;
  1148. ctx->authsize = authsize;
  1149. return 0;
  1150. }
  1151. static void tegra_aead_cra_exit(struct crypto_aead *tfm)
  1152. {
  1153. struct tegra_aead_ctx *ctx = crypto_tfm_ctx(&tfm->base);
  1154. if (ctx->key_id)
  1155. tegra_key_invalidate(ctx->se, ctx->key_id, ctx->alg);
  1156. }
  1157. static int tegra_aead_crypt(struct aead_request *req, bool encrypt)
  1158. {
  1159. struct crypto_aead *tfm = crypto_aead_reqtfm(req);
  1160. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1161. struct tegra_aead_reqctx *rctx = aead_request_ctx(req);
  1162. rctx->encrypt = encrypt;
  1163. return crypto_transfer_aead_request_to_engine(ctx->se->engine, req);
  1164. }
  1165. static int tegra_aead_encrypt(struct aead_request *req)
  1166. {
  1167. return tegra_aead_crypt(req, true);
  1168. }
  1169. static int tegra_aead_decrypt(struct aead_request *req)
  1170. {
  1171. return tegra_aead_crypt(req, false);
  1172. }
  1173. static int tegra_aead_setkey(struct crypto_aead *tfm,
  1174. const u8 *key, u32 keylen)
  1175. {
  1176. struct tegra_aead_ctx *ctx = crypto_aead_ctx(tfm);
  1177. int ret;
  1178. if (aes_check_keylen(keylen)) {
  1179. dev_dbg(ctx->se->dev, "invalid key length (%d)\n", keylen);
  1180. return -EINVAL;
  1181. }
  1182. ret = tegra_key_submit(ctx->se, key, keylen, ctx->alg, &ctx->key_id);
  1183. if (ret) {
  1184. ctx->keylen = keylen;
  1185. memcpy(ctx->key, key, keylen);
  1186. }
  1187. return 0;
  1188. }
  1189. static unsigned int tegra_cmac_prep_cmd(struct tegra_cmac_ctx *ctx,
  1190. struct tegra_cmac_reqctx *rctx)
  1191. {
  1192. unsigned int data_count, res_bits = 0, i = 0, j;
  1193. struct tegra_se *se = ctx->se;
  1194. u32 *cpuvaddr = se->cmdbuf->addr, op;
  1195. data_count = (rctx->datbuf.size / AES_BLOCK_SIZE);
  1196. op = SE_AES_OP_WRSTALL | SE_AES_OP_START | SE_AES_OP_LASTBUF;
  1197. if (!(rctx->task & SHA_UPDATE)) {
  1198. op |= SE_AES_OP_FINAL;
  1199. res_bits = (rctx->datbuf.size % AES_BLOCK_SIZE) * 8;
  1200. }
  1201. if (!res_bits && data_count)
  1202. data_count--;
  1203. if (rctx->task & SHA_FIRST) {
  1204. rctx->task &= ~SHA_FIRST;
  1205. cpuvaddr[i++] = host1x_opcode_setpayload(SE_CRYPTO_CTR_REG_COUNT);
  1206. cpuvaddr[i++] = se_host1x_opcode_incr_w(se->hw->regs->linear_ctr);
  1207. /* Load 0 IV */
  1208. for (j = 0; j < SE_CRYPTO_CTR_REG_COUNT; j++)
  1209. cpuvaddr[i++] = 0;
  1210. }
  1211. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->last_blk, 1);
  1212. cpuvaddr[i++] = SE_LAST_BLOCK_VAL(data_count) |
  1213. SE_LAST_BLOCK_RES_BITS(res_bits);
  1214. cpuvaddr[i++] = se_host1x_opcode_incr(se->hw->regs->config, 6);
  1215. cpuvaddr[i++] = rctx->config;
  1216. cpuvaddr[i++] = rctx->crypto_config;
  1217. /* Source Address */
  1218. cpuvaddr[i++] = lower_32_bits(rctx->datbuf.addr);
  1219. cpuvaddr[i++] = SE_ADDR_HI_MSB(upper_32_bits(rctx->datbuf.addr)) |
  1220. SE_ADDR_HI_SZ(rctx->datbuf.size);
  1221. cpuvaddr[i++] = 0;
  1222. cpuvaddr[i++] = SE_ADDR_HI_SZ(AES_BLOCK_SIZE);
  1223. cpuvaddr[i++] = se_host1x_opcode_nonincr(se->hw->regs->op, 1);
  1224. cpuvaddr[i++] = op;
  1225. cpuvaddr[i++] = se_host1x_opcode_nonincr(host1x_uclass_incr_syncpt_r(), 1);
  1226. cpuvaddr[i++] = host1x_uclass_incr_syncpt_cond_f(1) |
  1227. host1x_uclass_incr_syncpt_indx_f(se->syncpt_id);
  1228. return i;
  1229. }
  1230. static void tegra_cmac_copy_result(struct tegra_se *se, struct tegra_cmac_reqctx *rctx)
  1231. {
  1232. int i;
  1233. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  1234. rctx->result[i] = readl(se->base + se->hw->regs->result + (i * 4));
  1235. }
  1236. static void tegra_cmac_paste_result(struct tegra_se *se, struct tegra_cmac_reqctx *rctx)
  1237. {
  1238. int i;
  1239. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  1240. writel(rctx->result[i],
  1241. se->base + se->hw->regs->result + (i * 4));
  1242. }
  1243. static int tegra_cmac_do_init(struct ahash_request *req)
  1244. {
  1245. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1246. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1247. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1248. struct tegra_se *se = ctx->se;
  1249. int i;
  1250. rctx->total_len = 0;
  1251. rctx->datbuf.size = 0;
  1252. rctx->residue.size = 0;
  1253. rctx->key_id = ctx->key_id;
  1254. rctx->task |= SHA_FIRST;
  1255. rctx->blk_size = crypto_ahash_blocksize(tfm);
  1256. rctx->residue.buf = dma_alloc_coherent(se->dev, rctx->blk_size * 2,
  1257. &rctx->residue.addr, GFP_KERNEL);
  1258. if (!rctx->residue.buf)
  1259. return -ENOMEM;
  1260. rctx->residue.size = 0;
  1261. /* Clear any previous result */
  1262. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  1263. writel(0, se->base + se->hw->regs->result + (i * 4));
  1264. return 0;
  1265. }
  1266. static int tegra_cmac_do_update(struct ahash_request *req)
  1267. {
  1268. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1269. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1270. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1271. struct tegra_se *se = ctx->se;
  1272. unsigned int nblks, nresidue, cmdlen;
  1273. int ret;
  1274. if (!req->nbytes)
  1275. return 0;
  1276. nresidue = (req->nbytes + rctx->residue.size) % rctx->blk_size;
  1277. nblks = (req->nbytes + rctx->residue.size) / rctx->blk_size;
  1278. /*
  1279. * Reserve the last block as residue during final() to process.
  1280. */
  1281. if (!nresidue && nblks) {
  1282. nresidue += rctx->blk_size;
  1283. nblks--;
  1284. }
  1285. rctx->src_sg = req->src;
  1286. rctx->datbuf.size = (req->nbytes + rctx->residue.size) - nresidue;
  1287. rctx->total_len += rctx->datbuf.size;
  1288. rctx->config = tegra234_aes_cfg(SE_ALG_CMAC, 0);
  1289. rctx->crypto_config = SE_AES_KEY_INDEX(rctx->key_id);
  1290. /*
  1291. * Keep one block and residue bytes in residue and
  1292. * return. The bytes will be processed in final()
  1293. */
  1294. if (nblks < 1) {
  1295. scatterwalk_map_and_copy(rctx->residue.buf + rctx->residue.size,
  1296. rctx->src_sg, 0, req->nbytes, 0);
  1297. rctx->residue.size += req->nbytes;
  1298. return 0;
  1299. }
  1300. rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->datbuf.size,
  1301. &rctx->datbuf.addr, GFP_KERNEL);
  1302. if (!rctx->datbuf.buf)
  1303. return -ENOMEM;
  1304. /* Copy the previous residue first */
  1305. if (rctx->residue.size)
  1306. memcpy(rctx->datbuf.buf, rctx->residue.buf, rctx->residue.size);
  1307. scatterwalk_map_and_copy(rctx->datbuf.buf + rctx->residue.size,
  1308. rctx->src_sg, 0, req->nbytes - nresidue, 0);
  1309. scatterwalk_map_and_copy(rctx->residue.buf, rctx->src_sg,
  1310. req->nbytes - nresidue, nresidue, 0);
  1311. /* Update residue value with the residue after current block */
  1312. rctx->residue.size = nresidue;
  1313. /*
  1314. * If this is not the first task, paste the previous copied
  1315. * intermediate results to the registers so that it gets picked up.
  1316. */
  1317. if (!(rctx->task & SHA_FIRST))
  1318. tegra_cmac_paste_result(ctx->se, rctx);
  1319. cmdlen = tegra_cmac_prep_cmd(ctx, rctx);
  1320. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  1321. tegra_cmac_copy_result(ctx->se, rctx);
  1322. dma_free_coherent(ctx->se->dev, rctx->datbuf.size,
  1323. rctx->datbuf.buf, rctx->datbuf.addr);
  1324. return ret;
  1325. }
  1326. static int tegra_cmac_do_final(struct ahash_request *req)
  1327. {
  1328. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1329. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1330. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1331. struct tegra_se *se = ctx->se;
  1332. u32 *result = (u32 *)req->result;
  1333. int ret = 0, i, cmdlen;
  1334. if (!req->nbytes && !rctx->total_len && ctx->fallback_tfm) {
  1335. return crypto_shash_tfm_digest(ctx->fallback_tfm,
  1336. NULL, 0, req->result);
  1337. }
  1338. if (rctx->residue.size) {
  1339. rctx->datbuf.buf = dma_alloc_coherent(se->dev, rctx->residue.size,
  1340. &rctx->datbuf.addr, GFP_KERNEL);
  1341. if (!rctx->datbuf.buf) {
  1342. ret = -ENOMEM;
  1343. goto out_free;
  1344. }
  1345. memcpy(rctx->datbuf.buf, rctx->residue.buf, rctx->residue.size);
  1346. }
  1347. rctx->datbuf.size = rctx->residue.size;
  1348. rctx->total_len += rctx->residue.size;
  1349. rctx->config = tegra234_aes_cfg(SE_ALG_CMAC, 0);
  1350. /*
  1351. * If this is not the first task, paste the previous copied
  1352. * intermediate results to the registers so that it gets picked up.
  1353. */
  1354. if (!(rctx->task & SHA_FIRST))
  1355. tegra_cmac_paste_result(ctx->se, rctx);
  1356. /* Prepare command and submit */
  1357. cmdlen = tegra_cmac_prep_cmd(ctx, rctx);
  1358. ret = tegra_se_host1x_submit(se, se->cmdbuf, cmdlen);
  1359. if (ret)
  1360. goto out;
  1361. /* Read and clear Result register */
  1362. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  1363. result[i] = readl(se->base + se->hw->regs->result + (i * 4));
  1364. for (i = 0; i < CMAC_RESULT_REG_COUNT; i++)
  1365. writel(0, se->base + se->hw->regs->result + (i * 4));
  1366. out:
  1367. if (rctx->residue.size)
  1368. dma_free_coherent(se->dev, rctx->datbuf.size,
  1369. rctx->datbuf.buf, rctx->datbuf.addr);
  1370. out_free:
  1371. dma_free_coherent(se->dev, crypto_ahash_blocksize(tfm) * 2,
  1372. rctx->residue.buf, rctx->residue.addr);
  1373. return ret;
  1374. }
  1375. static int tegra_cmac_do_one_req(struct crypto_engine *engine, void *areq)
  1376. {
  1377. struct ahash_request *req = ahash_request_cast(areq);
  1378. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1379. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1380. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1381. struct tegra_se *se = ctx->se;
  1382. int ret = 0;
  1383. if (rctx->task & SHA_INIT) {
  1384. ret = tegra_cmac_do_init(req);
  1385. if (ret)
  1386. goto out;
  1387. rctx->task &= ~SHA_INIT;
  1388. }
  1389. if (!ctx->key_id) {
  1390. ret = tegra_key_submit_reserved_aes(ctx->se, ctx->key,
  1391. ctx->keylen, ctx->alg, &rctx->key_id);
  1392. if (ret)
  1393. goto out;
  1394. }
  1395. if (rctx->task & SHA_UPDATE) {
  1396. ret = tegra_cmac_do_update(req);
  1397. if (ret)
  1398. goto out;
  1399. rctx->task &= ~SHA_UPDATE;
  1400. }
  1401. if (rctx->task & SHA_FINAL) {
  1402. ret = tegra_cmac_do_final(req);
  1403. if (ret)
  1404. goto out;
  1405. rctx->task &= ~SHA_FINAL;
  1406. }
  1407. out:
  1408. if (tegra_key_is_reserved(rctx->key_id))
  1409. tegra_key_invalidate_reserved(ctx->se, rctx->key_id, ctx->alg);
  1410. crypto_finalize_hash_request(se->engine, req, ret);
  1411. return 0;
  1412. }
  1413. static void tegra_cmac_init_fallback(struct crypto_ahash *tfm, struct tegra_cmac_ctx *ctx,
  1414. const char *algname)
  1415. {
  1416. unsigned int statesize;
  1417. ctx->fallback_tfm = crypto_alloc_shash(algname, 0, CRYPTO_ALG_NEED_FALLBACK);
  1418. if (IS_ERR(ctx->fallback_tfm)) {
  1419. dev_warn(ctx->se->dev, "failed to allocate fallback for %s\n", algname);
  1420. ctx->fallback_tfm = NULL;
  1421. return;
  1422. }
  1423. statesize = crypto_shash_statesize(ctx->fallback_tfm);
  1424. if (statesize > sizeof(struct tegra_cmac_reqctx))
  1425. crypto_ahash_set_statesize(tfm, statesize);
  1426. }
  1427. static int tegra_cmac_cra_init(struct crypto_tfm *tfm)
  1428. {
  1429. struct tegra_cmac_ctx *ctx = crypto_tfm_ctx(tfm);
  1430. struct crypto_ahash *ahash_tfm = __crypto_ahash_cast(tfm);
  1431. struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg);
  1432. struct tegra_se_alg *se_alg;
  1433. const char *algname;
  1434. int ret;
  1435. algname = crypto_tfm_alg_name(tfm);
  1436. se_alg = container_of(alg, struct tegra_se_alg, alg.ahash.base);
  1437. crypto_ahash_set_reqsize(ahash_tfm, sizeof(struct tegra_cmac_reqctx));
  1438. ctx->se = se_alg->se_dev;
  1439. ctx->key_id = 0;
  1440. ctx->keylen = 0;
  1441. ret = se_algname_to_algid(algname);
  1442. if (ret < 0) {
  1443. dev_err(ctx->se->dev, "invalid algorithm\n");
  1444. return ret;
  1445. }
  1446. ctx->alg = ret;
  1447. tegra_cmac_init_fallback(ahash_tfm, ctx, algname);
  1448. return 0;
  1449. }
  1450. static void tegra_cmac_cra_exit(struct crypto_tfm *tfm)
  1451. {
  1452. struct tegra_cmac_ctx *ctx = crypto_tfm_ctx(tfm);
  1453. if (ctx->fallback_tfm)
  1454. crypto_free_shash(ctx->fallback_tfm);
  1455. tegra_key_invalidate(ctx->se, ctx->key_id, ctx->alg);
  1456. }
  1457. static int tegra_cmac_setkey(struct crypto_ahash *tfm, const u8 *key,
  1458. unsigned int keylen)
  1459. {
  1460. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1461. int ret;
  1462. if (aes_check_keylen(keylen)) {
  1463. dev_dbg(ctx->se->dev, "invalid key length (%d)\n", keylen);
  1464. return -EINVAL;
  1465. }
  1466. if (ctx->fallback_tfm)
  1467. crypto_shash_setkey(ctx->fallback_tfm, key, keylen);
  1468. ret = tegra_key_submit(ctx->se, key, keylen, ctx->alg, &ctx->key_id);
  1469. if (ret) {
  1470. ctx->keylen = keylen;
  1471. memcpy(ctx->key, key, keylen);
  1472. }
  1473. return 0;
  1474. }
  1475. static int tegra_cmac_init(struct ahash_request *req)
  1476. {
  1477. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1478. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1479. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1480. rctx->task = SHA_INIT;
  1481. return crypto_transfer_hash_request_to_engine(ctx->se->engine, req);
  1482. }
  1483. static int tegra_cmac_update(struct ahash_request *req)
  1484. {
  1485. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1486. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1487. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1488. rctx->task |= SHA_UPDATE;
  1489. return crypto_transfer_hash_request_to_engine(ctx->se->engine, req);
  1490. }
  1491. static int tegra_cmac_final(struct ahash_request *req)
  1492. {
  1493. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1494. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1495. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1496. rctx->task |= SHA_FINAL;
  1497. return crypto_transfer_hash_request_to_engine(ctx->se->engine, req);
  1498. }
  1499. static int tegra_cmac_finup(struct ahash_request *req)
  1500. {
  1501. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1502. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1503. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1504. rctx->task |= SHA_UPDATE | SHA_FINAL;
  1505. return crypto_transfer_hash_request_to_engine(ctx->se->engine, req);
  1506. }
  1507. static int tegra_cmac_digest(struct ahash_request *req)
  1508. {
  1509. struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
  1510. struct tegra_cmac_ctx *ctx = crypto_ahash_ctx(tfm);
  1511. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1512. rctx->task |= SHA_INIT | SHA_UPDATE | SHA_FINAL;
  1513. return crypto_transfer_hash_request_to_engine(ctx->se->engine, req);
  1514. }
  1515. static int tegra_cmac_export(struct ahash_request *req, void *out)
  1516. {
  1517. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1518. memcpy(out, rctx, sizeof(*rctx));
  1519. return 0;
  1520. }
  1521. static int tegra_cmac_import(struct ahash_request *req, const void *in)
  1522. {
  1523. struct tegra_cmac_reqctx *rctx = ahash_request_ctx(req);
  1524. memcpy(rctx, in, sizeof(*rctx));
  1525. return 0;
  1526. }
  1527. static struct tegra_se_alg tegra_aead_algs[] = {
  1528. {
  1529. .alg.aead.op.do_one_request = tegra_gcm_do_one_req,
  1530. .alg.aead.base = {
  1531. .init = tegra_aead_cra_init,
  1532. .exit = tegra_aead_cra_exit,
  1533. .setkey = tegra_aead_setkey,
  1534. .setauthsize = tegra_gcm_setauthsize,
  1535. .encrypt = tegra_aead_encrypt,
  1536. .decrypt = tegra_aead_decrypt,
  1537. .maxauthsize = AES_BLOCK_SIZE,
  1538. .ivsize = GCM_AES_IV_SIZE,
  1539. .base = {
  1540. .cra_name = "gcm(aes)",
  1541. .cra_driver_name = "gcm-aes-tegra",
  1542. .cra_priority = 500,
  1543. .cra_flags = CRYPTO_ALG_ASYNC,
  1544. .cra_blocksize = 1,
  1545. .cra_ctxsize = sizeof(struct tegra_aead_ctx),
  1546. .cra_alignmask = 0xf,
  1547. .cra_module = THIS_MODULE,
  1548. },
  1549. }
  1550. }, {
  1551. .alg.aead.op.do_one_request = tegra_ccm_do_one_req,
  1552. .alg.aead.base = {
  1553. .init = tegra_aead_cra_init,
  1554. .exit = tegra_aead_cra_exit,
  1555. .setkey = tegra_aead_setkey,
  1556. .setauthsize = tegra_ccm_setauthsize,
  1557. .encrypt = tegra_aead_encrypt,
  1558. .decrypt = tegra_aead_decrypt,
  1559. .maxauthsize = AES_BLOCK_SIZE,
  1560. .ivsize = AES_BLOCK_SIZE,
  1561. .chunksize = AES_BLOCK_SIZE,
  1562. .base = {
  1563. .cra_name = "ccm(aes)",
  1564. .cra_driver_name = "ccm-aes-tegra",
  1565. .cra_priority = 500,
  1566. .cra_flags = CRYPTO_ALG_ASYNC,
  1567. .cra_blocksize = 1,
  1568. .cra_ctxsize = sizeof(struct tegra_aead_ctx),
  1569. .cra_alignmask = 0xf,
  1570. .cra_module = THIS_MODULE,
  1571. },
  1572. }
  1573. }
  1574. };
  1575. static struct tegra_se_alg tegra_cmac_algs[] = {
  1576. {
  1577. .alg.ahash.op.do_one_request = tegra_cmac_do_one_req,
  1578. .alg.ahash.base = {
  1579. .init = tegra_cmac_init,
  1580. .setkey = tegra_cmac_setkey,
  1581. .update = tegra_cmac_update,
  1582. .final = tegra_cmac_final,
  1583. .finup = tegra_cmac_finup,
  1584. .digest = tegra_cmac_digest,
  1585. .export = tegra_cmac_export,
  1586. .import = tegra_cmac_import,
  1587. .halg.digestsize = AES_BLOCK_SIZE,
  1588. .halg.statesize = sizeof(struct tegra_cmac_reqctx),
  1589. .halg.base = {
  1590. .cra_name = "cmac(aes)",
  1591. .cra_driver_name = "tegra-se-cmac",
  1592. .cra_priority = 300,
  1593. .cra_flags = CRYPTO_ALG_ASYNC,
  1594. .cra_blocksize = AES_BLOCK_SIZE,
  1595. .cra_ctxsize = sizeof(struct tegra_cmac_ctx),
  1596. .cra_alignmask = 0,
  1597. .cra_module = THIS_MODULE,
  1598. .cra_init = tegra_cmac_cra_init,
  1599. .cra_exit = tegra_cmac_cra_exit,
  1600. }
  1601. }
  1602. }
  1603. };
  1604. int tegra_init_aes(struct tegra_se *se)
  1605. {
  1606. struct aead_engine_alg *aead_alg;
  1607. struct ahash_engine_alg *ahash_alg;
  1608. struct skcipher_engine_alg *sk_alg;
  1609. int i, ret;
  1610. se->manifest = tegra_aes_kac_manifest;
  1611. for (i = 0; i < ARRAY_SIZE(tegra_aes_algs); i++) {
  1612. sk_alg = &tegra_aes_algs[i].alg.skcipher;
  1613. tegra_aes_algs[i].se_dev = se;
  1614. ret = crypto_engine_register_skcipher(sk_alg);
  1615. if (ret) {
  1616. dev_err(se->dev, "failed to register %s\n",
  1617. sk_alg->base.base.cra_name);
  1618. goto err_aes;
  1619. }
  1620. }
  1621. for (i = 0; i < ARRAY_SIZE(tegra_aead_algs); i++) {
  1622. aead_alg = &tegra_aead_algs[i].alg.aead;
  1623. tegra_aead_algs[i].se_dev = se;
  1624. ret = crypto_engine_register_aead(aead_alg);
  1625. if (ret) {
  1626. dev_err(se->dev, "failed to register %s\n",
  1627. aead_alg->base.base.cra_name);
  1628. goto err_aead;
  1629. }
  1630. }
  1631. for (i = 0; i < ARRAY_SIZE(tegra_cmac_algs); i++) {
  1632. ahash_alg = &tegra_cmac_algs[i].alg.ahash;
  1633. tegra_cmac_algs[i].se_dev = se;
  1634. ret = crypto_engine_register_ahash(ahash_alg);
  1635. if (ret) {
  1636. dev_err(se->dev, "failed to register %s\n",
  1637. ahash_alg->base.halg.base.cra_name);
  1638. goto err_cmac;
  1639. }
  1640. }
  1641. return 0;
  1642. err_cmac:
  1643. while (i--)
  1644. crypto_engine_unregister_ahash(&tegra_cmac_algs[i].alg.ahash);
  1645. i = ARRAY_SIZE(tegra_aead_algs);
  1646. err_aead:
  1647. while (i--)
  1648. crypto_engine_unregister_aead(&tegra_aead_algs[i].alg.aead);
  1649. i = ARRAY_SIZE(tegra_aes_algs);
  1650. err_aes:
  1651. while (i--)
  1652. crypto_engine_unregister_skcipher(&tegra_aes_algs[i].alg.skcipher);
  1653. return ret;
  1654. }
  1655. void tegra_deinit_aes(struct tegra_se *se)
  1656. {
  1657. int i;
  1658. for (i = 0; i < ARRAY_SIZE(tegra_aes_algs); i++)
  1659. crypto_engine_unregister_skcipher(&tegra_aes_algs[i].alg.skcipher);
  1660. for (i = 0; i < ARRAY_SIZE(tegra_aead_algs); i++)
  1661. crypto_engine_unregister_aead(&tegra_aead_algs[i].alg.aead);
  1662. for (i = 0; i < ARRAY_SIZE(tegra_cmac_algs); i++)
  1663. crypto_engine_unregister_ahash(&tegra_cmac_algs[i].alg.ahash);
  1664. }