sun50i-cpufreq-nvmem.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Allwinner CPUFreq nvmem based driver
  4. *
  5. * The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
  6. * provide the OPP framework with required information.
  7. *
  8. * Copyright (C) 2019 Yangtao Li <tiny.windzz@gmail.com>
  9. */
  10. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  11. #include <linux/arm-smccc.h>
  12. #include <linux/cpu.h>
  13. #include <linux/module.h>
  14. #include <linux/nvmem-consumer.h>
  15. #include <linux/of.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/pm_opp.h>
  18. #include <linux/slab.h>
  19. #define NVMEM_MASK 0x7
  20. #define NVMEM_SHIFT 5
  21. #define SUN50I_A100_NVMEM_MASK 0xf
  22. #define SUN50I_A100_NVMEM_SHIFT 12
  23. static struct platform_device *cpufreq_dt_pdev, *sun50i_cpufreq_pdev;
  24. struct sunxi_cpufreq_data {
  25. u32 (*efuse_xlate)(u32 speedbin);
  26. };
  27. static u32 sun50i_h6_efuse_xlate(u32 speedbin)
  28. {
  29. u32 efuse_value;
  30. efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK;
  31. /*
  32. * We treat unexpected efuse values as if the SoC was from
  33. * the slowest bin. Expected efuse values are 1-3, slowest
  34. * to fastest.
  35. */
  36. if (efuse_value >= 1 && efuse_value <= 3)
  37. return efuse_value - 1;
  38. else
  39. return 0;
  40. }
  41. static u32 sun50i_a100_efuse_xlate(u32 speedbin)
  42. {
  43. u32 efuse_value;
  44. efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) &
  45. SUN50I_A100_NVMEM_MASK;
  46. switch (efuse_value) {
  47. case 0b100:
  48. return 2;
  49. case 0b010:
  50. return 1;
  51. default:
  52. return 0;
  53. }
  54. }
  55. static int get_soc_id_revision(void)
  56. {
  57. #ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
  58. return arm_smccc_get_soc_id_revision();
  59. #else
  60. return SMCCC_RET_NOT_SUPPORTED;
  61. #endif
  62. }
  63. /*
  64. * Judging by the OPP tables in the vendor BSP, the quality order of the
  65. * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
  66. * 0 and 2 seem identical from the OPP tables' point of view.
  67. */
  68. static u32 sun50i_h616_efuse_xlate(u32 speedbin)
  69. {
  70. int ver_bits = get_soc_id_revision();
  71. u32 value = 0;
  72. switch (speedbin & 0xffff) {
  73. case 0x2000:
  74. value = 0;
  75. break;
  76. case 0x2400:
  77. case 0x7400:
  78. case 0x2c00:
  79. case 0x7c00:
  80. if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) {
  81. /* ic version A/B */
  82. value = 1;
  83. } else {
  84. /* ic version C and later version */
  85. value = 2;
  86. }
  87. break;
  88. case 0x5000:
  89. case 0x5400:
  90. case 0x6000:
  91. value = 3;
  92. break;
  93. case 0x5c00:
  94. value = 4;
  95. break;
  96. case 0x5d00:
  97. value = 0;
  98. break;
  99. case 0x6c00:
  100. value = 5;
  101. break;
  102. default:
  103. pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",
  104. speedbin & 0xffff);
  105. value = 0;
  106. break;
  107. }
  108. return value;
  109. }
  110. static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
  111. .efuse_xlate = sun50i_h6_efuse_xlate,
  112. };
  113. static struct sunxi_cpufreq_data sun50i_a100_cpufreq_data = {
  114. .efuse_xlate = sun50i_a100_efuse_xlate,
  115. };
  116. static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
  117. .efuse_xlate = sun50i_h616_efuse_xlate,
  118. };
  119. static const struct of_device_id cpu_opp_match_list[] = {
  120. { .compatible = "allwinner,sun50i-h6-operating-points",
  121. .data = &sun50i_h6_cpufreq_data,
  122. },
  123. { .compatible = "allwinner,sun50i-a100-operating-points",
  124. .data = &sun50i_a100_cpufreq_data,
  125. },
  126. { .compatible = "allwinner,sun50i-h616-operating-points",
  127. .data = &sun50i_h616_cpufreq_data,
  128. },
  129. {}
  130. };
  131. /**
  132. * dt_has_supported_hw() - Check if any OPPs use opp-supported-hw
  133. *
  134. * If we ask the cpufreq framework to use the opp-supported-hw feature, it
  135. * will ignore every OPP node without that DT property. If none of the OPPs
  136. * have it, the driver will fail probing, due to the lack of OPPs.
  137. *
  138. * Returns true if we have at least one OPP with the opp-supported-hw property.
  139. */
  140. static bool dt_has_supported_hw(void)
  141. {
  142. bool has_opp_supported_hw = false;
  143. struct device *cpu_dev;
  144. cpu_dev = get_cpu_device(0);
  145. if (!cpu_dev)
  146. return false;
  147. struct device_node *np __free(device_node) =
  148. dev_pm_opp_of_get_opp_desc_node(cpu_dev);
  149. if (!np)
  150. return false;
  151. for_each_child_of_node_scoped(np, opp) {
  152. if (of_property_present(opp, "opp-supported-hw")) {
  153. has_opp_supported_hw = true;
  154. break;
  155. }
  156. }
  157. return has_opp_supported_hw;
  158. }
  159. /**
  160. * sun50i_cpufreq_get_efuse() - Determine speed grade from efuse value
  161. *
  162. * Returns non-negative speed bin index on success, a negative error
  163. * value otherwise.
  164. */
  165. static int sun50i_cpufreq_get_efuse(void)
  166. {
  167. const struct sunxi_cpufreq_data *opp_data;
  168. struct nvmem_cell *speedbin_nvmem;
  169. const struct of_device_id *match;
  170. struct device *cpu_dev;
  171. void *speedbin_ptr;
  172. u32 speedbin = 0;
  173. size_t len;
  174. int ret;
  175. cpu_dev = get_cpu_device(0);
  176. if (!cpu_dev)
  177. return -ENODEV;
  178. struct device_node *np __free(device_node) =
  179. dev_pm_opp_of_get_opp_desc_node(cpu_dev);
  180. if (!np)
  181. return -ENOENT;
  182. match = of_match_node(cpu_opp_match_list, np);
  183. if (!match)
  184. return -ENOENT;
  185. opp_data = match->data;
  186. speedbin_nvmem = of_nvmem_cell_get(np, NULL);
  187. if (IS_ERR(speedbin_nvmem))
  188. return dev_err_probe(cpu_dev, PTR_ERR(speedbin_nvmem),
  189. "Could not get nvmem cell\n");
  190. speedbin_ptr = nvmem_cell_read(speedbin_nvmem, &len);
  191. nvmem_cell_put(speedbin_nvmem);
  192. if (IS_ERR(speedbin_ptr))
  193. return PTR_ERR(speedbin_ptr);
  194. if (len <= 4)
  195. memcpy(&speedbin, speedbin_ptr, len);
  196. speedbin = le32_to_cpu(speedbin);
  197. ret = opp_data->efuse_xlate(speedbin);
  198. kfree(speedbin_ptr);
  199. return ret;
  200. };
  201. static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
  202. {
  203. int *opp_tokens;
  204. char name[] = "speedXXXXXXXXXXX"; /* Integers can take 11 chars max */
  205. unsigned int cpu, supported_hw;
  206. struct dev_pm_opp_config config = {};
  207. int speed;
  208. int ret;
  209. opp_tokens = kzalloc_objs(*opp_tokens, num_possible_cpus());
  210. if (!opp_tokens)
  211. return -ENOMEM;
  212. speed = sun50i_cpufreq_get_efuse();
  213. if (speed < 0) {
  214. kfree(opp_tokens);
  215. return speed;
  216. }
  217. /*
  218. * We need at least one OPP with the "opp-supported-hw" property,
  219. * or else the upper layers will ignore every OPP and will bail out.
  220. */
  221. if (dt_has_supported_hw()) {
  222. supported_hw = 1U << speed;
  223. config.supported_hw = &supported_hw;
  224. config.supported_hw_count = 1;
  225. }
  226. snprintf(name, sizeof(name), "speed%d", speed);
  227. config.prop_name = name;
  228. for_each_present_cpu(cpu) {
  229. struct device *cpu_dev = get_cpu_device(cpu);
  230. if (!cpu_dev) {
  231. ret = -ENODEV;
  232. goto free_opp;
  233. }
  234. ret = dev_pm_opp_set_config(cpu_dev, &config);
  235. if (ret < 0)
  236. goto free_opp;
  237. opp_tokens[cpu] = ret;
  238. }
  239. cpufreq_dt_pdev = platform_device_register_simple("cpufreq-dt", -1,
  240. NULL, 0);
  241. if (!IS_ERR(cpufreq_dt_pdev)) {
  242. platform_set_drvdata(pdev, opp_tokens);
  243. return 0;
  244. }
  245. ret = PTR_ERR(cpufreq_dt_pdev);
  246. pr_err("Failed to register platform device\n");
  247. free_opp:
  248. for_each_present_cpu(cpu)
  249. dev_pm_opp_clear_config(opp_tokens[cpu]);
  250. kfree(opp_tokens);
  251. return ret;
  252. }
  253. static void sun50i_cpufreq_nvmem_remove(struct platform_device *pdev)
  254. {
  255. int *opp_tokens = platform_get_drvdata(pdev);
  256. unsigned int cpu;
  257. platform_device_unregister(cpufreq_dt_pdev);
  258. for_each_present_cpu(cpu)
  259. dev_pm_opp_clear_config(opp_tokens[cpu]);
  260. kfree(opp_tokens);
  261. }
  262. static struct platform_driver sun50i_cpufreq_driver = {
  263. .probe = sun50i_cpufreq_nvmem_probe,
  264. .remove = sun50i_cpufreq_nvmem_remove,
  265. .driver = {
  266. .name = "sun50i-cpufreq-nvmem",
  267. },
  268. };
  269. static const struct of_device_id sun50i_cpufreq_match_list[] = {
  270. { .compatible = "allwinner,sun50i-h6" },
  271. { .compatible = "allwinner,sun50i-a100" },
  272. { .compatible = "allwinner,sun50i-h616" },
  273. { .compatible = "allwinner,sun50i-h618" },
  274. { .compatible = "allwinner,sun50i-h700" },
  275. {}
  276. };
  277. MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
  278. /*
  279. * Since the driver depends on nvmem drivers, which may return EPROBE_DEFER,
  280. * all the real activity is done in the probe, which may be defered as well.
  281. * The init here is only registering the driver and the platform device.
  282. */
  283. static int __init sun50i_cpufreq_init(void)
  284. {
  285. int ret;
  286. if (!of_machine_device_match(sun50i_cpufreq_match_list))
  287. return -ENODEV;
  288. ret = platform_driver_register(&sun50i_cpufreq_driver);
  289. if (unlikely(ret < 0))
  290. return ret;
  291. sun50i_cpufreq_pdev =
  292. platform_device_register_simple("sun50i-cpufreq-nvmem",
  293. -1, NULL, 0);
  294. ret = PTR_ERR_OR_ZERO(sun50i_cpufreq_pdev);
  295. if (ret == 0)
  296. return 0;
  297. platform_driver_unregister(&sun50i_cpufreq_driver);
  298. return ret;
  299. }
  300. module_init(sun50i_cpufreq_init);
  301. static void __exit sun50i_cpufreq_exit(void)
  302. {
  303. platform_device_unregister(sun50i_cpufreq_pdev);
  304. platform_driver_unregister(&sun50i_cpufreq_driver);
  305. }
  306. module_exit(sun50i_cpufreq_exit);
  307. MODULE_DESCRIPTION("Sun50i-h6 cpufreq driver");
  308. MODULE_LICENSE("GPL v2");