powernv-cpufreq.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * POWERNV cpufreq driver for the IBM POWER processors
  4. *
  5. * (C) Copyright IBM 2014
  6. *
  7. * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
  8. */
  9. #define pr_fmt(fmt) "powernv-cpufreq: " fmt
  10. #include <linux/kernel.h>
  11. #include <linux/sysfs.h>
  12. #include <linux/cpumask.h>
  13. #include <linux/module.h>
  14. #include <linux/cpufreq.h>
  15. #include <linux/smp.h>
  16. #include <linux/of.h>
  17. #include <linux/reboot.h>
  18. #include <linux/slab.h>
  19. #include <linux/string_choices.h>
  20. #include <linux/cpu.h>
  21. #include <linux/hashtable.h>
  22. #include <asm/cputhreads.h>
  23. #include <asm/firmware.h>
  24. #include <asm/reg.h>
  25. #include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
  26. #include <asm/opal.h>
  27. #include <linux/timer.h>
  28. #define CREATE_TRACE_POINTS
  29. #include "powernv-trace.h"
  30. #define POWERNV_MAX_PSTATES_ORDER 8
  31. #define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER))
  32. #define PMSR_PSAFE_ENABLE (1UL << 30)
  33. #define PMSR_SPR_EM_DISABLE (1UL << 31)
  34. #define MAX_PSTATE_SHIFT 32
  35. #define LPSTATE_SHIFT 48
  36. #define GPSTATE_SHIFT 56
  37. #define MAX_NR_CHIPS 32
  38. #define MAX_RAMP_DOWN_TIME 5120
  39. /*
  40. * On an idle system we want the global pstate to ramp-down from max value to
  41. * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
  42. * then ramp-down rapidly later on.
  43. *
  44. * This gives a percentage rampdown for time elapsed in milliseconds.
  45. * ramp_down_percentage = ((ms * ms) >> 18)
  46. * ~= 3.8 * (sec * sec)
  47. *
  48. * At 0 ms ramp_down_percent = 0
  49. * At 5120 ms ramp_down_percent = 100
  50. */
  51. #define ramp_down_percent(time) ((time * time) >> 18)
  52. /* Interval after which the timer is queued to bring down global pstate */
  53. #define GPSTATE_TIMER_INTERVAL 2000
  54. /**
  55. * struct global_pstate_info - Per policy data structure to maintain history of
  56. * global pstates
  57. * @highest_lpstate_idx: The local pstate index from which we are
  58. * ramping down
  59. * @elapsed_time: Time in ms spent in ramping down from
  60. * highest_lpstate_idx
  61. * @last_sampled_time: Time from boot in ms when global pstates were
  62. * last set
  63. * @last_lpstate_idx: Last set value of local pstate and global
  64. * @last_gpstate_idx: pstate in terms of cpufreq table index
  65. * @timer: Is used for ramping down if cpu goes idle for
  66. * a long time with global pstate held high
  67. * @gpstate_lock: A spinlock to maintain synchronization between
  68. * routines called by the timer handler and
  69. * governer's target_index calls
  70. * @policy: Associated CPUFreq policy
  71. */
  72. struct global_pstate_info {
  73. int highest_lpstate_idx;
  74. unsigned int elapsed_time;
  75. unsigned int last_sampled_time;
  76. int last_lpstate_idx;
  77. int last_gpstate_idx;
  78. spinlock_t gpstate_lock;
  79. struct timer_list timer;
  80. struct cpufreq_policy *policy;
  81. };
  82. static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
  83. static DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER);
  84. /**
  85. * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap
  86. * indexed by a function of pstate id.
  87. *
  88. * @pstate_id: pstate id for this entry.
  89. *
  90. * @cpufreq_table_idx: Index into the powernv_freqs
  91. * cpufreq_frequency_table for frequency
  92. * corresponding to pstate_id.
  93. *
  94. * @hentry: hlist_node that hooks this entry into the pstate_revmap
  95. * hashtable
  96. */
  97. struct pstate_idx_revmap_data {
  98. u8 pstate_id;
  99. unsigned int cpufreq_table_idx;
  100. struct hlist_node hentry;
  101. };
  102. static bool rebooting, throttled, occ_reset;
  103. static const char * const throttle_reason[] = {
  104. "No throttling",
  105. "Power Cap",
  106. "Processor Over Temperature",
  107. "Power Supply Failure",
  108. "Over Current",
  109. "OCC Reset"
  110. };
  111. enum throttle_reason_type {
  112. NO_THROTTLE = 0,
  113. POWERCAP,
  114. CPU_OVERTEMP,
  115. POWER_SUPPLY_FAILURE,
  116. OVERCURRENT,
  117. OCC_RESET_THROTTLE,
  118. OCC_MAX_REASON
  119. };
  120. static struct chip {
  121. unsigned int id;
  122. bool throttled;
  123. bool restore;
  124. u8 throttle_reason;
  125. cpumask_t mask;
  126. struct work_struct throttle;
  127. int throttle_turbo;
  128. int throttle_sub_turbo;
  129. int reason[OCC_MAX_REASON];
  130. } *chips;
  131. static int nr_chips;
  132. static DEFINE_PER_CPU(struct chip *, chip_info);
  133. /*
  134. * Note:
  135. * The set of pstates consists of contiguous integers.
  136. * powernv_pstate_info stores the index of the frequency table for
  137. * max, min and nominal frequencies. It also stores number of
  138. * available frequencies.
  139. *
  140. * powernv_pstate_info.nominal indicates the index to the highest
  141. * non-turbo frequency.
  142. */
  143. static struct powernv_pstate_info {
  144. unsigned int min;
  145. unsigned int max;
  146. unsigned int nominal;
  147. unsigned int nr_pstates;
  148. bool wof_enabled;
  149. } powernv_pstate_info;
  150. static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift)
  151. {
  152. return ((pmsr_val >> shift) & 0xFF);
  153. }
  154. #define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT)
  155. #define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT)
  156. #define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT)
  157. /* Use following functions for conversions between pstate_id and index */
  158. /*
  159. * idx_to_pstate : Returns the pstate id corresponding to the
  160. * frequency in the cpufreq frequency table
  161. * powernv_freqs indexed by @i.
  162. *
  163. * If @i is out of bound, this will return the pstate
  164. * corresponding to the nominal frequency.
  165. */
  166. static inline u8 idx_to_pstate(unsigned int i)
  167. {
  168. if (unlikely(i >= powernv_pstate_info.nr_pstates)) {
  169. pr_warn_once("idx_to_pstate: index %u is out of bound\n", i);
  170. return powernv_freqs[powernv_pstate_info.nominal].driver_data;
  171. }
  172. return powernv_freqs[i].driver_data;
  173. }
  174. /*
  175. * pstate_to_idx : Returns the index in the cpufreq frequencytable
  176. * powernv_freqs for the frequency whose corresponding
  177. * pstate id is @pstate.
  178. *
  179. * If no frequency corresponding to @pstate is found,
  180. * this will return the index of the nominal
  181. * frequency.
  182. */
  183. static unsigned int pstate_to_idx(u8 pstate)
  184. {
  185. unsigned int key = pstate % POWERNV_MAX_PSTATES;
  186. struct pstate_idx_revmap_data *revmap_data;
  187. hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) {
  188. if (revmap_data->pstate_id == pstate)
  189. return revmap_data->cpufreq_table_idx;
  190. }
  191. pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate);
  192. return powernv_pstate_info.nominal;
  193. }
  194. static inline void reset_gpstates(struct cpufreq_policy *policy)
  195. {
  196. struct global_pstate_info *gpstates = policy->driver_data;
  197. gpstates->highest_lpstate_idx = 0;
  198. gpstates->elapsed_time = 0;
  199. gpstates->last_sampled_time = 0;
  200. gpstates->last_lpstate_idx = 0;
  201. gpstates->last_gpstate_idx = 0;
  202. }
  203. /*
  204. * Initialize the freq table based on data obtained
  205. * from the firmware passed via device-tree
  206. */
  207. static int init_powernv_pstates(void)
  208. {
  209. struct device_node *power_mgt;
  210. int i, nr_pstates = 0;
  211. const __be32 *pstate_ids, *pstate_freqs;
  212. u32 len_ids, len_freqs;
  213. u32 pstate_min, pstate_max, pstate_nominal;
  214. u32 pstate_turbo, pstate_ultra_turbo;
  215. int rc = -ENODEV;
  216. power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
  217. if (!power_mgt) {
  218. pr_warn("power-mgt node not found\n");
  219. return -ENODEV;
  220. }
  221. if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
  222. pr_warn("ibm,pstate-min node not found\n");
  223. goto out;
  224. }
  225. if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
  226. pr_warn("ibm,pstate-max node not found\n");
  227. goto out;
  228. }
  229. if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
  230. &pstate_nominal)) {
  231. pr_warn("ibm,pstate-nominal not found\n");
  232. goto out;
  233. }
  234. if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo",
  235. &pstate_ultra_turbo)) {
  236. powernv_pstate_info.wof_enabled = false;
  237. goto next;
  238. }
  239. if (of_property_read_u32(power_mgt, "ibm,pstate-turbo",
  240. &pstate_turbo)) {
  241. powernv_pstate_info.wof_enabled = false;
  242. goto next;
  243. }
  244. if (pstate_turbo == pstate_ultra_turbo)
  245. powernv_pstate_info.wof_enabled = false;
  246. else
  247. powernv_pstate_info.wof_enabled = true;
  248. next:
  249. pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min,
  250. pstate_nominal, pstate_max);
  251. pr_info("Workload Optimized Frequency is %s in the platform\n",
  252. str_enabled_disabled(powernv_pstate_info.wof_enabled));
  253. pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
  254. if (!pstate_ids) {
  255. pr_warn("ibm,pstate-ids not found\n");
  256. goto out;
  257. }
  258. pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
  259. &len_freqs);
  260. if (!pstate_freqs) {
  261. pr_warn("ibm,pstate-frequencies-mhz not found\n");
  262. goto out;
  263. }
  264. if (len_ids != len_freqs) {
  265. pr_warn("Entries in ibm,pstate-ids and "
  266. "ibm,pstate-frequencies-mhz does not match\n");
  267. }
  268. nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
  269. if (!nr_pstates) {
  270. pr_warn("No PStates found\n");
  271. goto out;
  272. }
  273. powernv_pstate_info.nr_pstates = nr_pstates;
  274. pr_debug("NR PStates %d\n", nr_pstates);
  275. for (i = 0; i < nr_pstates; i++) {
  276. u32 id = be32_to_cpu(pstate_ids[i]);
  277. u32 freq = be32_to_cpu(pstate_freqs[i]);
  278. struct pstate_idx_revmap_data *revmap_data;
  279. unsigned int key;
  280. pr_debug("PState id %d freq %d MHz\n", id, freq);
  281. powernv_freqs[i].frequency = freq * 1000; /* kHz */
  282. powernv_freqs[i].driver_data = id & 0xFF;
  283. revmap_data = kmalloc_obj(*revmap_data);
  284. if (!revmap_data) {
  285. rc = -ENOMEM;
  286. goto out;
  287. }
  288. revmap_data->pstate_id = id & 0xFF;
  289. revmap_data->cpufreq_table_idx = i;
  290. key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES;
  291. hash_add(pstate_revmap, &revmap_data->hentry, key);
  292. if (id == pstate_max)
  293. powernv_pstate_info.max = i;
  294. if (id == pstate_nominal)
  295. powernv_pstate_info.nominal = i;
  296. if (id == pstate_min)
  297. powernv_pstate_info.min = i;
  298. if (powernv_pstate_info.wof_enabled && id == pstate_turbo) {
  299. int j;
  300. for (j = i - 1; j >= (int)powernv_pstate_info.max; j--)
  301. powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ;
  302. }
  303. }
  304. /* End of list marker entry */
  305. powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
  306. of_node_put(power_mgt);
  307. return 0;
  308. out:
  309. of_node_put(power_mgt);
  310. return rc;
  311. }
  312. /* Returns the CPU frequency corresponding to the pstate_id. */
  313. static unsigned int pstate_id_to_freq(u8 pstate_id)
  314. {
  315. int i;
  316. i = pstate_to_idx(pstate_id);
  317. if (i >= powernv_pstate_info.nr_pstates || i < 0) {
  318. pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n",
  319. pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
  320. i = powernv_pstate_info.nominal;
  321. }
  322. return powernv_freqs[i].frequency;
  323. }
  324. /*
  325. * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
  326. * the firmware
  327. */
  328. static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
  329. char *buf)
  330. {
  331. return sprintf(buf, "%u\n",
  332. powernv_freqs[powernv_pstate_info.nominal].frequency);
  333. }
  334. static struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
  335. __ATTR_RO(cpuinfo_nominal_freq);
  336. static struct freq_attr *powernv_cpu_freq_attr[] = {
  337. &cpufreq_freq_attr_cpuinfo_nominal_freq,
  338. NULL,
  339. };
  340. #define throttle_attr(name, member) \
  341. static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
  342. { \
  343. struct chip *chip = per_cpu(chip_info, policy->cpu); \
  344. \
  345. return sprintf(buf, "%u\n", chip->member); \
  346. } \
  347. \
  348. static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
  349. throttle_attr(unthrottle, reason[NO_THROTTLE]);
  350. throttle_attr(powercap, reason[POWERCAP]);
  351. throttle_attr(overtemp, reason[CPU_OVERTEMP]);
  352. throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
  353. throttle_attr(overcurrent, reason[OVERCURRENT]);
  354. throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
  355. throttle_attr(turbo_stat, throttle_turbo);
  356. throttle_attr(sub_turbo_stat, throttle_sub_turbo);
  357. static struct attribute *throttle_attrs[] = {
  358. &throttle_attr_unthrottle.attr,
  359. &throttle_attr_powercap.attr,
  360. &throttle_attr_overtemp.attr,
  361. &throttle_attr_supply_fault.attr,
  362. &throttle_attr_overcurrent.attr,
  363. &throttle_attr_occ_reset.attr,
  364. &throttle_attr_turbo_stat.attr,
  365. &throttle_attr_sub_turbo_stat.attr,
  366. NULL,
  367. };
  368. static const struct attribute_group throttle_attr_grp = {
  369. .name = "throttle_stats",
  370. .attrs = throttle_attrs,
  371. };
  372. /* Helper routines */
  373. /* Access helpers to power mgt SPR */
  374. static inline unsigned long get_pmspr(unsigned long sprn)
  375. {
  376. switch (sprn) {
  377. case SPRN_PMCR:
  378. return mfspr(SPRN_PMCR);
  379. case SPRN_PMICR:
  380. return mfspr(SPRN_PMICR);
  381. case SPRN_PMSR:
  382. return mfspr(SPRN_PMSR);
  383. }
  384. BUG();
  385. }
  386. static inline void set_pmspr(unsigned long sprn, unsigned long val)
  387. {
  388. switch (sprn) {
  389. case SPRN_PMCR:
  390. mtspr(SPRN_PMCR, val);
  391. return;
  392. case SPRN_PMICR:
  393. mtspr(SPRN_PMICR, val);
  394. return;
  395. }
  396. BUG();
  397. }
  398. /*
  399. * Use objects of this type to query/update
  400. * pstates on a remote CPU via smp_call_function.
  401. */
  402. struct powernv_smp_call_data {
  403. unsigned int freq;
  404. u8 pstate_id;
  405. u8 gpstate_id;
  406. };
  407. /*
  408. * powernv_read_cpu_freq: Reads the current frequency on this CPU.
  409. *
  410. * Called via smp_call_function.
  411. *
  412. * Note: The caller of the smp_call_function should pass an argument of
  413. * the type 'struct powernv_smp_call_data *' along with this function.
  414. *
  415. * The current frequency on this CPU will be returned via
  416. * ((struct powernv_smp_call_data *)arg)->freq;
  417. */
  418. static void powernv_read_cpu_freq(void *arg)
  419. {
  420. unsigned long pmspr_val;
  421. struct powernv_smp_call_data *freq_data = arg;
  422. pmspr_val = get_pmspr(SPRN_PMSR);
  423. freq_data->pstate_id = extract_local_pstate(pmspr_val);
  424. freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
  425. pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n",
  426. raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
  427. freq_data->freq);
  428. }
  429. /*
  430. * powernv_cpufreq_get: Returns the CPU frequency as reported by the
  431. * firmware for CPU 'cpu'. This value is reported through the sysfs
  432. * file cpuinfo_cur_freq.
  433. */
  434. static unsigned int powernv_cpufreq_get(unsigned int cpu)
  435. {
  436. struct powernv_smp_call_data freq_data;
  437. smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
  438. &freq_data, 1);
  439. return freq_data.freq;
  440. }
  441. /*
  442. * set_pstate: Sets the pstate on this CPU.
  443. *
  444. * This is called via an smp_call_function.
  445. *
  446. * The caller must ensure that freq_data is of the type
  447. * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
  448. * on this CPU should be present in freq_data->pstate_id.
  449. */
  450. static void set_pstate(void *data)
  451. {
  452. unsigned long val;
  453. struct powernv_smp_call_data *freq_data = data;
  454. unsigned long pstate_ul = freq_data->pstate_id;
  455. unsigned long gpstate_ul = freq_data->gpstate_id;
  456. val = get_pmspr(SPRN_PMCR);
  457. val = val & 0x0000FFFFFFFFFFFFULL;
  458. pstate_ul = pstate_ul & 0xFF;
  459. gpstate_ul = gpstate_ul & 0xFF;
  460. /* Set both global(bits 56..63) and local(bits 48..55) PStates */
  461. val = val | (gpstate_ul << 56) | (pstate_ul << 48);
  462. pr_debug("Setting cpu %d pmcr to %016lX\n",
  463. raw_smp_processor_id(), val);
  464. set_pmspr(SPRN_PMCR, val);
  465. }
  466. /*
  467. * get_nominal_index: Returns the index corresponding to the nominal
  468. * pstate in the cpufreq table
  469. */
  470. static inline unsigned int get_nominal_index(void)
  471. {
  472. return powernv_pstate_info.nominal;
  473. }
  474. static void powernv_cpufreq_throttle_check(void *data)
  475. {
  476. struct chip *chip;
  477. unsigned int cpu = smp_processor_id();
  478. unsigned long pmsr;
  479. u8 pmsr_pmax;
  480. unsigned int pmsr_pmax_idx;
  481. pmsr = get_pmspr(SPRN_PMSR);
  482. chip = this_cpu_read(chip_info);
  483. /* Check for Pmax Capping */
  484. pmsr_pmax = extract_max_pstate(pmsr);
  485. pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
  486. if (pmsr_pmax_idx != powernv_pstate_info.max) {
  487. if (chip->throttled)
  488. goto next;
  489. chip->throttled = true;
  490. if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
  491. pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n",
  492. cpu, chip->id, pmsr_pmax,
  493. idx_to_pstate(powernv_pstate_info.nominal));
  494. chip->throttle_sub_turbo++;
  495. } else {
  496. chip->throttle_turbo++;
  497. }
  498. trace_powernv_throttle(chip->id,
  499. throttle_reason[chip->throttle_reason],
  500. pmsr_pmax);
  501. } else if (chip->throttled) {
  502. chip->throttled = false;
  503. trace_powernv_throttle(chip->id,
  504. throttle_reason[chip->throttle_reason],
  505. pmsr_pmax);
  506. }
  507. /* Check if Psafe_mode_active is set in PMSR. */
  508. next:
  509. if (pmsr & PMSR_PSAFE_ENABLE) {
  510. throttled = true;
  511. pr_info("Pstate set to safe frequency\n");
  512. }
  513. /* Check if SPR_EM_DISABLE is set in PMSR */
  514. if (pmsr & PMSR_SPR_EM_DISABLE) {
  515. throttled = true;
  516. pr_info("Frequency Control disabled from OS\n");
  517. }
  518. if (throttled) {
  519. pr_info("PMSR = %16lx\n", pmsr);
  520. pr_warn("CPU Frequency could be throttled\n");
  521. }
  522. }
  523. /**
  524. * calc_global_pstate - Calculate global pstate
  525. * @elapsed_time: Elapsed time in milliseconds
  526. * @local_pstate_idx: New local pstate
  527. * @highest_lpstate_idx: pstate from which its ramping down
  528. *
  529. * Finds the appropriate global pstate based on the pstate from which its
  530. * ramping down and the time elapsed in ramping down. It follows a quadratic
  531. * equation which ensures that it reaches ramping down to pmin in 5sec.
  532. */
  533. static inline int calc_global_pstate(unsigned int elapsed_time,
  534. int highest_lpstate_idx,
  535. int local_pstate_idx)
  536. {
  537. int index_diff;
  538. /*
  539. * Using ramp_down_percent we get the percentage of rampdown
  540. * that we are expecting to be dropping. Difference between
  541. * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
  542. * number of how many pstates we will drop eventually by the end of
  543. * 5 seconds, then just scale it get the number pstates to be dropped.
  544. */
  545. index_diff = ((int)ramp_down_percent(elapsed_time) *
  546. (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
  547. /* Ensure that global pstate is >= to local pstate */
  548. if (highest_lpstate_idx + index_diff >= local_pstate_idx)
  549. return local_pstate_idx;
  550. else
  551. return highest_lpstate_idx + index_diff;
  552. }
  553. static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
  554. {
  555. unsigned int timer_interval;
  556. /*
  557. * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
  558. * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
  559. * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
  560. * seconds of ramp down time.
  561. */
  562. if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
  563. > MAX_RAMP_DOWN_TIME)
  564. timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
  565. else
  566. timer_interval = GPSTATE_TIMER_INTERVAL;
  567. mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
  568. }
  569. /**
  570. * gpstate_timer_handler
  571. *
  572. * @t: Timer context used to fetch global pstate info struct
  573. *
  574. * This handler brings down the global pstate closer to the local pstate
  575. * according quadratic equation. Queues a new timer if it is still not equal
  576. * to local pstate
  577. */
  578. static void gpstate_timer_handler(struct timer_list *t)
  579. {
  580. struct global_pstate_info *gpstates = timer_container_of(gpstates, t,
  581. timer);
  582. struct cpufreq_policy *policy = gpstates->policy;
  583. int gpstate_idx, lpstate_idx;
  584. unsigned long val;
  585. unsigned int time_diff = jiffies_to_msecs(jiffies)
  586. - gpstates->last_sampled_time;
  587. struct powernv_smp_call_data freq_data;
  588. if (!spin_trylock(&gpstates->gpstate_lock))
  589. return;
  590. /*
  591. * If the timer has migrated to the different cpu then bring
  592. * it back to one of the policy->cpus
  593. */
  594. if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) {
  595. gpstates->timer.expires = jiffies + msecs_to_jiffies(1);
  596. add_timer_on(&gpstates->timer, cpumask_first(policy->cpus));
  597. spin_unlock(&gpstates->gpstate_lock);
  598. return;
  599. }
  600. /*
  601. * If PMCR was last updated was using fast_switch then
  602. * We may have wrong in gpstate->last_lpstate_idx
  603. * value. Hence, read from PMCR to get correct data.
  604. */
  605. val = get_pmspr(SPRN_PMCR);
  606. freq_data.gpstate_id = extract_global_pstate(val);
  607. freq_data.pstate_id = extract_local_pstate(val);
  608. if (freq_data.gpstate_id == freq_data.pstate_id) {
  609. reset_gpstates(policy);
  610. spin_unlock(&gpstates->gpstate_lock);
  611. return;
  612. }
  613. gpstates->last_sampled_time += time_diff;
  614. gpstates->elapsed_time += time_diff;
  615. if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
  616. gpstate_idx = pstate_to_idx(freq_data.pstate_id);
  617. lpstate_idx = gpstate_idx;
  618. reset_gpstates(policy);
  619. gpstates->highest_lpstate_idx = gpstate_idx;
  620. } else {
  621. lpstate_idx = pstate_to_idx(freq_data.pstate_id);
  622. gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
  623. gpstates->highest_lpstate_idx,
  624. lpstate_idx);
  625. }
  626. freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
  627. gpstates->last_gpstate_idx = gpstate_idx;
  628. gpstates->last_lpstate_idx = lpstate_idx;
  629. /*
  630. * If local pstate is equal to global pstate, rampdown is over
  631. * So timer is not required to be queued.
  632. */
  633. if (gpstate_idx != gpstates->last_lpstate_idx)
  634. queue_gpstate_timer(gpstates);
  635. set_pstate(&freq_data);
  636. spin_unlock(&gpstates->gpstate_lock);
  637. }
  638. /*
  639. * powernv_cpufreq_target_index: Sets the frequency corresponding to
  640. * the cpufreq table entry indexed by new_index on the cpus in the
  641. * mask policy->cpus
  642. */
  643. static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
  644. unsigned int new_index)
  645. {
  646. struct powernv_smp_call_data freq_data;
  647. unsigned int cur_msec, gpstate_idx;
  648. struct global_pstate_info *gpstates = policy->driver_data;
  649. if (unlikely(rebooting) && new_index != get_nominal_index())
  650. return 0;
  651. if (!throttled) {
  652. /* we don't want to be preempted while
  653. * checking if the CPU frequency has been throttled
  654. */
  655. preempt_disable();
  656. powernv_cpufreq_throttle_check(NULL);
  657. preempt_enable();
  658. }
  659. cur_msec = jiffies_to_msecs(get_jiffies_64());
  660. freq_data.pstate_id = idx_to_pstate(new_index);
  661. if (!gpstates) {
  662. freq_data.gpstate_id = freq_data.pstate_id;
  663. goto no_gpstate;
  664. }
  665. spin_lock(&gpstates->gpstate_lock);
  666. if (!gpstates->last_sampled_time) {
  667. gpstate_idx = new_index;
  668. gpstates->highest_lpstate_idx = new_index;
  669. goto gpstates_done;
  670. }
  671. if (gpstates->last_gpstate_idx < new_index) {
  672. gpstates->elapsed_time += cur_msec -
  673. gpstates->last_sampled_time;
  674. /*
  675. * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
  676. * we should be resetting all global pstate related data. Set it
  677. * equal to local pstate to start fresh.
  678. */
  679. if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
  680. reset_gpstates(policy);
  681. gpstates->highest_lpstate_idx = new_index;
  682. gpstate_idx = new_index;
  683. } else {
  684. /* Elaspsed_time is less than 5 seconds, continue to rampdown */
  685. gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
  686. gpstates->highest_lpstate_idx,
  687. new_index);
  688. }
  689. } else {
  690. reset_gpstates(policy);
  691. gpstates->highest_lpstate_idx = new_index;
  692. gpstate_idx = new_index;
  693. }
  694. /*
  695. * If local pstate is equal to global pstate, rampdown is over
  696. * So timer is not required to be queued.
  697. */
  698. if (gpstate_idx != new_index)
  699. queue_gpstate_timer(gpstates);
  700. else
  701. timer_delete_sync(&gpstates->timer);
  702. gpstates_done:
  703. freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
  704. gpstates->last_sampled_time = cur_msec;
  705. gpstates->last_gpstate_idx = gpstate_idx;
  706. gpstates->last_lpstate_idx = new_index;
  707. spin_unlock(&gpstates->gpstate_lock);
  708. no_gpstate:
  709. /*
  710. * Use smp_call_function to send IPI and execute the
  711. * mtspr on target CPU. We could do that without IPI
  712. * if current CPU is within policy->cpus (core)
  713. */
  714. smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
  715. return 0;
  716. }
  717. static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
  718. {
  719. int base, i;
  720. struct kernfs_node *kn;
  721. struct global_pstate_info *gpstates;
  722. base = cpu_first_thread_sibling(policy->cpu);
  723. for (i = 0; i < threads_per_core; i++)
  724. cpumask_set_cpu(base + i, policy->cpus);
  725. kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
  726. if (!kn) {
  727. int ret;
  728. ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
  729. if (ret) {
  730. pr_info("Failed to create throttle stats directory for cpu %d\n",
  731. policy->cpu);
  732. return ret;
  733. }
  734. } else {
  735. kernfs_put(kn);
  736. }
  737. policy->freq_table = powernv_freqs;
  738. policy->fast_switch_possible = true;
  739. if (pvr_version_is(PVR_POWER9))
  740. return 0;
  741. /* Initialise Gpstate ramp-down timer only on POWER8 */
  742. gpstates = kzalloc_obj(*gpstates);
  743. if (!gpstates)
  744. return -ENOMEM;
  745. policy->driver_data = gpstates;
  746. /* initialize timer */
  747. gpstates->policy = policy;
  748. timer_setup(&gpstates->timer, gpstate_timer_handler,
  749. TIMER_PINNED | TIMER_DEFERRABLE);
  750. gpstates->timer.expires = jiffies +
  751. msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
  752. spin_lock_init(&gpstates->gpstate_lock);
  753. return 0;
  754. }
  755. static void powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
  756. {
  757. struct powernv_smp_call_data freq_data;
  758. struct global_pstate_info *gpstates = policy->driver_data;
  759. freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
  760. freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
  761. smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
  762. if (gpstates)
  763. timer_delete_sync(&gpstates->timer);
  764. kfree(policy->driver_data);
  765. }
  766. static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
  767. unsigned long action, void *unused)
  768. {
  769. int cpu;
  770. struct cpufreq_policy *cpu_policy;
  771. rebooting = true;
  772. for_each_online_cpu(cpu) {
  773. cpu_policy = cpufreq_cpu_get(cpu);
  774. if (!cpu_policy)
  775. continue;
  776. powernv_cpufreq_target_index(cpu_policy, get_nominal_index());
  777. cpufreq_cpu_put(cpu_policy);
  778. }
  779. return NOTIFY_DONE;
  780. }
  781. static struct notifier_block powernv_cpufreq_reboot_nb = {
  782. .notifier_call = powernv_cpufreq_reboot_notifier,
  783. };
  784. static void powernv_cpufreq_work_fn(struct work_struct *work)
  785. {
  786. struct chip *chip = container_of(work, struct chip, throttle);
  787. struct cpufreq_policy *policy;
  788. unsigned int cpu;
  789. cpumask_t mask;
  790. cpus_read_lock();
  791. cpumask_and(&mask, &chip->mask, cpu_online_mask);
  792. smp_call_function_any(&mask,
  793. powernv_cpufreq_throttle_check, NULL, 0);
  794. if (!chip->restore)
  795. goto out;
  796. chip->restore = false;
  797. for_each_cpu(cpu, &mask) {
  798. int index;
  799. policy = cpufreq_cpu_get(cpu);
  800. if (!policy)
  801. continue;
  802. index = cpufreq_table_find_index_c(policy, policy->cur, false);
  803. powernv_cpufreq_target_index(policy, index);
  804. cpumask_andnot(&mask, &mask, policy->cpus);
  805. cpufreq_cpu_put(policy);
  806. }
  807. out:
  808. cpus_read_unlock();
  809. }
  810. static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
  811. unsigned long msg_type, void *_msg)
  812. {
  813. struct opal_msg *msg = _msg;
  814. struct opal_occ_msg omsg;
  815. int i;
  816. if (msg_type != OPAL_MSG_OCC)
  817. return 0;
  818. omsg.type = be64_to_cpu(msg->params[0]);
  819. switch (omsg.type) {
  820. case OCC_RESET:
  821. occ_reset = true;
  822. pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
  823. /*
  824. * powernv_cpufreq_throttle_check() is called in
  825. * target() callback which can detect the throttle state
  826. * for governors like ondemand.
  827. * But static governors will not call target() often thus
  828. * report throttling here.
  829. */
  830. if (!throttled) {
  831. throttled = true;
  832. pr_warn("CPU frequency is throttled for duration\n");
  833. }
  834. break;
  835. case OCC_LOAD:
  836. pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
  837. break;
  838. case OCC_THROTTLE:
  839. omsg.chip = be64_to_cpu(msg->params[1]);
  840. omsg.throttle_status = be64_to_cpu(msg->params[2]);
  841. if (occ_reset) {
  842. occ_reset = false;
  843. throttled = false;
  844. pr_info("OCC Active, CPU frequency is no longer throttled\n");
  845. for (i = 0; i < nr_chips; i++) {
  846. chips[i].restore = true;
  847. schedule_work(&chips[i].throttle);
  848. }
  849. return 0;
  850. }
  851. for (i = 0; i < nr_chips; i++)
  852. if (chips[i].id == omsg.chip)
  853. break;
  854. if (omsg.throttle_status >= 0 &&
  855. omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
  856. chips[i].throttle_reason = omsg.throttle_status;
  857. chips[i].reason[omsg.throttle_status]++;
  858. }
  859. if (!omsg.throttle_status)
  860. chips[i].restore = true;
  861. schedule_work(&chips[i].throttle);
  862. }
  863. return 0;
  864. }
  865. static struct notifier_block powernv_cpufreq_opal_nb = {
  866. .notifier_call = powernv_cpufreq_occ_msg,
  867. .next = NULL,
  868. .priority = 0,
  869. };
  870. static unsigned int powernv_fast_switch(struct cpufreq_policy *policy,
  871. unsigned int target_freq)
  872. {
  873. int index;
  874. struct powernv_smp_call_data freq_data;
  875. index = cpufreq_table_find_index_dl(policy, target_freq, false);
  876. freq_data.pstate_id = powernv_freqs[index].driver_data;
  877. freq_data.gpstate_id = powernv_freqs[index].driver_data;
  878. set_pstate(&freq_data);
  879. return powernv_freqs[index].frequency;
  880. }
  881. static struct cpufreq_driver powernv_cpufreq_driver = {
  882. .name = "powernv-cpufreq",
  883. .flags = CPUFREQ_CONST_LOOPS,
  884. .init = powernv_cpufreq_cpu_init,
  885. .exit = powernv_cpufreq_cpu_exit,
  886. .verify = cpufreq_generic_frequency_table_verify,
  887. .target_index = powernv_cpufreq_target_index,
  888. .fast_switch = powernv_fast_switch,
  889. .get = powernv_cpufreq_get,
  890. .attr = powernv_cpu_freq_attr,
  891. };
  892. static int init_chip_info(void)
  893. {
  894. unsigned int *chip;
  895. unsigned int cpu, i;
  896. unsigned int prev_chip_id = UINT_MAX;
  897. cpumask_t *chip_cpu_mask;
  898. int ret = 0;
  899. chip = kcalloc(num_possible_cpus(), sizeof(*chip), GFP_KERNEL);
  900. if (!chip)
  901. return -ENOMEM;
  902. /* Allocate a chip cpu mask large enough to fit mask for all chips */
  903. chip_cpu_mask = kzalloc_objs(cpumask_t, MAX_NR_CHIPS);
  904. if (!chip_cpu_mask) {
  905. ret = -ENOMEM;
  906. goto free_and_return;
  907. }
  908. for_each_possible_cpu(cpu) {
  909. unsigned int id = cpu_to_chip_id(cpu);
  910. if (prev_chip_id != id) {
  911. prev_chip_id = id;
  912. chip[nr_chips++] = id;
  913. }
  914. cpumask_set_cpu(cpu, &chip_cpu_mask[nr_chips-1]);
  915. }
  916. chips = kzalloc_objs(struct chip, nr_chips);
  917. if (!chips) {
  918. ret = -ENOMEM;
  919. goto out_free_chip_cpu_mask;
  920. }
  921. for (i = 0; i < nr_chips; i++) {
  922. chips[i].id = chip[i];
  923. cpumask_copy(&chips[i].mask, &chip_cpu_mask[i]);
  924. INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
  925. for_each_cpu(cpu, &chips[i].mask)
  926. per_cpu(chip_info, cpu) = &chips[i];
  927. }
  928. out_free_chip_cpu_mask:
  929. kfree(chip_cpu_mask);
  930. free_and_return:
  931. kfree(chip);
  932. return ret;
  933. }
  934. static inline void clean_chip_info(void)
  935. {
  936. int i;
  937. /* flush any pending work items */
  938. if (chips)
  939. for (i = 0; i < nr_chips; i++)
  940. cancel_work_sync(&chips[i].throttle);
  941. kfree(chips);
  942. }
  943. static inline void unregister_all_notifiers(void)
  944. {
  945. opal_message_notifier_unregister(OPAL_MSG_OCC,
  946. &powernv_cpufreq_opal_nb);
  947. unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
  948. }
  949. static int __init powernv_cpufreq_init(void)
  950. {
  951. int rc = 0;
  952. /* Don't probe on pseries (guest) platforms */
  953. if (!firmware_has_feature(FW_FEATURE_OPAL))
  954. return -ENODEV;
  955. /* Discover pstates from device tree and init */
  956. rc = init_powernv_pstates();
  957. if (rc)
  958. goto out;
  959. /* Populate chip info */
  960. rc = init_chip_info();
  961. if (rc)
  962. goto out;
  963. if (powernv_pstate_info.wof_enabled)
  964. powernv_cpufreq_driver.set_boost = cpufreq_boost_set_sw;
  965. rc = cpufreq_register_driver(&powernv_cpufreq_driver);
  966. if (rc) {
  967. pr_info("Failed to register the cpufreq driver (%d)\n", rc);
  968. goto cleanup;
  969. }
  970. register_reboot_notifier(&powernv_cpufreq_reboot_nb);
  971. opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
  972. return 0;
  973. cleanup:
  974. clean_chip_info();
  975. out:
  976. pr_info("Platform driver disabled. System does not support PState control\n");
  977. return rc;
  978. }
  979. module_init(powernv_cpufreq_init);
  980. static void __exit powernv_cpufreq_exit(void)
  981. {
  982. cpufreq_unregister_driver(&powernv_cpufreq_driver);
  983. unregister_all_notifiers();
  984. clean_chip_info();
  985. }
  986. module_exit(powernv_cpufreq_exit);
  987. MODULE_DESCRIPTION("cpufreq driver for IBM/OpenPOWER powernv systems");
  988. MODULE_LICENSE("GPL");
  989. MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");