clk-gate-grf.c 2.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (c) 2025 Collabora Ltd.
  4. * Author: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
  5. *
  6. * Certain clocks on Rockchip are "gated" behind an additional register bit
  7. * write in a GRF register, such as the SAI MCLKs on RK3576. This code
  8. * implements a clock driver for these types of gates, based on regmaps.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clk-provider.h>
  12. #include <linux/regmap.h>
  13. #include <linux/slab.h>
  14. #include "clk.h"
  15. struct rockchip_gate_grf {
  16. struct clk_hw hw;
  17. struct regmap *regmap;
  18. unsigned int reg;
  19. unsigned int shift;
  20. u8 flags;
  21. };
  22. #define to_gate_grf(_hw) container_of(_hw, struct rockchip_gate_grf, hw)
  23. static int rockchip_gate_grf_enable(struct clk_hw *hw)
  24. {
  25. struct rockchip_gate_grf *gate = to_gate_grf(hw);
  26. u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0;
  27. u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
  28. int ret;
  29. ret = regmap_update_bits(gate->regmap, gate->reg,
  30. hiword | BIT(gate->shift), hiword | val);
  31. return ret;
  32. }
  33. static void rockchip_gate_grf_disable(struct clk_hw *hw)
  34. {
  35. struct rockchip_gate_grf *gate = to_gate_grf(hw);
  36. u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift);
  37. u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
  38. regmap_update_bits(gate->regmap, gate->reg,
  39. hiword | BIT(gate->shift), hiword | val);
  40. }
  41. static int rockchip_gate_grf_is_enabled(struct clk_hw *hw)
  42. {
  43. struct rockchip_gate_grf *gate = to_gate_grf(hw);
  44. bool invert = !!(gate->flags & CLK_GATE_SET_TO_DISABLE);
  45. int ret;
  46. ret = regmap_test_bits(gate->regmap, gate->reg, BIT(gate->shift));
  47. if (ret < 0)
  48. ret = 0;
  49. return invert ? 1 - ret : ret;
  50. }
  51. static const struct clk_ops rockchip_gate_grf_ops = {
  52. .enable = rockchip_gate_grf_enable,
  53. .disable = rockchip_gate_grf_disable,
  54. .is_enabled = rockchip_gate_grf_is_enabled,
  55. };
  56. struct clk *rockchip_clk_register_gate_grf(const char *name,
  57. const char *parent_name, unsigned long flags,
  58. struct regmap *regmap, unsigned int reg, unsigned int shift,
  59. u8 gate_flags)
  60. {
  61. struct rockchip_gate_grf *gate;
  62. struct clk_init_data init;
  63. struct clk *clk;
  64. if (IS_ERR(regmap)) {
  65. pr_err("%s: regmap not available\n", __func__);
  66. return ERR_PTR(-EOPNOTSUPP);
  67. }
  68. gate = kzalloc_obj(*gate);
  69. if (!gate)
  70. return ERR_PTR(-ENOMEM);
  71. init.name = name;
  72. init.flags = flags;
  73. init.num_parents = parent_name ? 1 : 0;
  74. init.parent_names = parent_name ? &parent_name : NULL;
  75. init.ops = &rockchip_gate_grf_ops;
  76. gate->hw.init = &init;
  77. gate->regmap = regmap;
  78. gate->reg = reg;
  79. gate->shift = shift;
  80. gate->flags = gate_flags;
  81. clk = clk_register(NULL, &gate->hw);
  82. if (IS_ERR(clk))
  83. kfree(gate);
  84. return clk;
  85. }