clk-mt7622-eth.c 2.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2017 MediaTek Inc.
  4. * Author: Chen Zhong <chen.zhong@mediatek.com>
  5. * Sean Wang <sean.wang@mediatek.com>
  6. */
  7. #include <linux/clk-provider.h>
  8. #include <linux/mod_devicetable.h>
  9. #include <linux/platform_device.h>
  10. #include "clk-mtk.h"
  11. #include "clk-gate.h"
  12. #include <dt-bindings/clock/mt7622-clk.h>
  13. #define GATE_ETH(_id, _name, _parent, _shift) \
  14. GATE_MTK(_id, _name, _parent, &eth_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
  15. static const struct mtk_gate_regs eth_cg_regs = {
  16. .set_ofs = 0x30,
  17. .clr_ofs = 0x30,
  18. .sta_ofs = 0x30,
  19. };
  20. static const struct mtk_gate eth_clks[] = {
  21. GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
  22. GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
  23. GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
  24. GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
  25. GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
  26. };
  27. static const struct mtk_gate_regs sgmii_cg_regs = {
  28. .set_ofs = 0xE4,
  29. .clr_ofs = 0xE4,
  30. .sta_ofs = 0xE4,
  31. };
  32. #define GATE_SGMII(_id, _name, _parent, _shift) \
  33. GATE_MTK(_id, _name, _parent, &sgmii_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
  34. static const struct mtk_gate sgmii_clks[] = {
  35. GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
  36. "ssusb_tx250m", 2),
  37. GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
  38. "ssusb_eq_rx250m", 3),
  39. GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
  40. "ssusb_cdr_ref", 4),
  41. GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
  42. "ssusb_cdr_fb", 5),
  43. };
  44. static u16 rst_ofs[] = { 0x34, };
  45. static const struct mtk_clk_rst_desc clk_rst_desc = {
  46. .version = MTK_RST_SIMPLE,
  47. .rst_bank_ofs = rst_ofs,
  48. .rst_bank_nr = ARRAY_SIZE(rst_ofs),
  49. };
  50. static const struct mtk_clk_desc eth_desc = {
  51. .clks = eth_clks,
  52. .num_clks = ARRAY_SIZE(eth_clks),
  53. .rst_desc = &clk_rst_desc,
  54. };
  55. static const struct mtk_clk_desc sgmii_desc = {
  56. .clks = sgmii_clks,
  57. .num_clks = ARRAY_SIZE(sgmii_clks),
  58. };
  59. static const struct of_device_id of_match_clk_mt7622_eth[] = {
  60. { .compatible = "mediatek,mt7622-ethsys", .data = &eth_desc },
  61. { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc },
  62. { /* sentinel */ }
  63. };
  64. MODULE_DEVICE_TABLE(of, of_match_clk_mt7622_eth);
  65. static struct platform_driver clk_mt7622_eth_drv = {
  66. .probe = mtk_clk_simple_probe,
  67. .remove = mtk_clk_simple_remove,
  68. .driver = {
  69. .name = "clk-mt7622-eth",
  70. .of_match_table = of_match_clk_mt7622_eth,
  71. },
  72. };
  73. module_platform_driver(clk_mt7622_eth_drv);
  74. MODULE_DESCRIPTION("MediaTek MT7622 Ethernet clocks driver");
  75. MODULE_LICENSE("GPL");