clk-si570.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for Silicon Labs Si570/Si571 Programmable XO/VCXO
  4. *
  5. * Copyright (C) 2010, 2011 Ericsson AB.
  6. * Copyright (C) 2011 Guenter Roeck.
  7. * Copyright (C) 2011 - 2021 Xilinx Inc.
  8. *
  9. * Author: Guenter Roeck <guenter.roeck@ericsson.com>
  10. * Sören Brinkmann <soren.brinkmann@xilinx.com>
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/delay.h>
  15. #include <linux/module.h>
  16. #include <linux/i2c.h>
  17. #include <linux/regmap.h>
  18. #include <linux/slab.h>
  19. /* Si570 registers */
  20. #define SI570_REG_HS_N1 7
  21. #define SI570_REG_N1_RFREQ0 8
  22. #define SI570_REG_RFREQ1 9
  23. #define SI570_REG_RFREQ2 10
  24. #define SI570_REG_RFREQ3 11
  25. #define SI570_REG_RFREQ4 12
  26. #define SI570_REG_CONTROL 135
  27. #define SI570_REG_FREEZE_DCO 137
  28. #define SI570_DIV_OFFSET_7PPM 6
  29. #define HS_DIV_SHIFT 5
  30. #define HS_DIV_MASK 0xe0
  31. #define HS_DIV_OFFSET 4
  32. #define N1_6_2_MASK 0x1f
  33. #define N1_1_0_MASK 0xc0
  34. #define RFREQ_37_32_MASK 0x3f
  35. #define SI570_MIN_FREQ 10000000L
  36. #define SI570_MAX_FREQ 1417500000L
  37. #define SI598_MAX_FREQ 525000000L
  38. #define FDCO_MIN 4850000000LL
  39. #define FDCO_MAX 5670000000LL
  40. #define SI570_CNTRL_RECALL (1 << 0)
  41. #define SI570_CNTRL_FREEZE_M (1 << 5)
  42. #define SI570_CNTRL_NEWFREQ (1 << 6)
  43. #define SI570_FREEZE_DCO (1 << 4)
  44. /**
  45. * struct clk_si570_info:
  46. * @max_freq: Maximum frequency for this device
  47. * @has_temperature_stability: Device support temperature stability
  48. */
  49. struct clk_si570_info {
  50. u64 max_freq;
  51. bool has_temperature_stability;
  52. };
  53. /**
  54. * struct clk_si570:
  55. * @hw: Clock hw struct
  56. * @regmap: Device's regmap
  57. * @div_offset: Register offset for dividers
  58. * @info: Device info
  59. * @fxtal: Factory xtal frequency
  60. * @n1: Clock divider N1
  61. * @hs_div: Clock divider HSDIV
  62. * @rfreq: Clock multiplier RFREQ
  63. * @frequency: Current output frequency
  64. * @i2c_client: I2C client pointer
  65. */
  66. struct clk_si570 {
  67. struct clk_hw hw;
  68. struct regmap *regmap;
  69. unsigned int div_offset;
  70. const struct clk_si570_info *info;
  71. u64 fxtal;
  72. unsigned int n1;
  73. unsigned int hs_div;
  74. u64 rfreq;
  75. u64 frequency;
  76. struct i2c_client *i2c_client;
  77. };
  78. #define to_clk_si570(_hw) container_of(_hw, struct clk_si570, hw)
  79. /**
  80. * si570_get_divs() - Read clock dividers from HW
  81. * @data: Pointer to struct clk_si570
  82. * @rfreq: Fractional multiplier (output)
  83. * @n1: Divider N1 (output)
  84. * @hs_div: Divider HSDIV (output)
  85. * Returns 0 on success, negative errno otherwise.
  86. *
  87. * Retrieve clock dividers and multipliers from the HW.
  88. */
  89. static int si570_get_divs(struct clk_si570 *data, u64 *rfreq,
  90. unsigned int *n1, unsigned int *hs_div)
  91. {
  92. int err;
  93. u8 reg[6];
  94. u64 tmp;
  95. err = regmap_bulk_read(data->regmap, SI570_REG_HS_N1 + data->div_offset,
  96. reg, ARRAY_SIZE(reg));
  97. if (err)
  98. return err;
  99. *hs_div = ((reg[0] & HS_DIV_MASK) >> HS_DIV_SHIFT) + HS_DIV_OFFSET;
  100. *n1 = ((reg[0] & N1_6_2_MASK) << 2) + ((reg[1] & N1_1_0_MASK) >> 6) + 1;
  101. /* Handle invalid cases */
  102. if (*n1 > 1)
  103. *n1 &= ~1;
  104. tmp = reg[1] & RFREQ_37_32_MASK;
  105. tmp = (tmp << 8) + reg[2];
  106. tmp = (tmp << 8) + reg[3];
  107. tmp = (tmp << 8) + reg[4];
  108. tmp = (tmp << 8) + reg[5];
  109. *rfreq = tmp;
  110. return 0;
  111. }
  112. /**
  113. * si570_get_defaults() - Get default values
  114. * @data: Driver data structure
  115. * @fout: Factory frequency output
  116. * @skip_recall: If true, don't recall NVM into RAM
  117. * Returns 0 on success, negative errno otherwise.
  118. */
  119. static int si570_get_defaults(struct clk_si570 *data, u64 fout,
  120. bool skip_recall)
  121. {
  122. int err;
  123. u64 fdco;
  124. if (!skip_recall)
  125. regmap_write(data->regmap, SI570_REG_CONTROL,
  126. SI570_CNTRL_RECALL);
  127. err = si570_get_divs(data, &data->rfreq, &data->n1, &data->hs_div);
  128. if (err)
  129. return err;
  130. /*
  131. * Accept optional precision loss to avoid arithmetic overflows.
  132. * Acceptable per Silicon Labs Application Note AN334.
  133. */
  134. fdco = fout * data->n1 * data->hs_div;
  135. if (fdco >= (1LL << 36))
  136. data->fxtal = div64_u64(fdco << 24, data->rfreq >> 4);
  137. else
  138. data->fxtal = div64_u64(fdco << 28, data->rfreq);
  139. data->frequency = fout;
  140. return 0;
  141. }
  142. /**
  143. * si570_update_rfreq() - Update clock multiplier
  144. * @data: Driver data structure
  145. * Passes on regmap_bulk_write() return value.
  146. */
  147. static int si570_update_rfreq(struct clk_si570 *data)
  148. {
  149. u8 reg[5];
  150. reg[0] = ((data->n1 - 1) << 6) |
  151. ((data->rfreq >> 32) & RFREQ_37_32_MASK);
  152. reg[1] = (data->rfreq >> 24) & 0xff;
  153. reg[2] = (data->rfreq >> 16) & 0xff;
  154. reg[3] = (data->rfreq >> 8) & 0xff;
  155. reg[4] = data->rfreq & 0xff;
  156. return regmap_bulk_write(data->regmap, SI570_REG_N1_RFREQ0 +
  157. data->div_offset, reg, ARRAY_SIZE(reg));
  158. }
  159. /**
  160. * si570_calc_divs() - Calculate clock dividers
  161. * @frequency: Target frequency
  162. * @data: Driver data structure
  163. * @out_rfreq: RFREG fractional multiplier (output)
  164. * @out_n1: Clock divider N1 (output)
  165. * @out_hs_div: Clock divider HSDIV (output)
  166. * Returns 0 on success, negative errno otherwise.
  167. *
  168. * Calculate the clock dividers (@out_hs_div, @out_n1) and clock multiplier
  169. * (@out_rfreq) for a given target @frequency.
  170. */
  171. static int si570_calc_divs(unsigned long frequency, struct clk_si570 *data,
  172. u64 *out_rfreq, unsigned int *out_n1, unsigned int *out_hs_div)
  173. {
  174. int i;
  175. unsigned int n1, hs_div;
  176. u64 fdco, best_fdco = ULLONG_MAX;
  177. static const uint8_t si570_hs_div_values[] = { 11, 9, 7, 6, 5, 4 };
  178. for (i = 0; i < ARRAY_SIZE(si570_hs_div_values); i++) {
  179. hs_div = si570_hs_div_values[i];
  180. /* Calculate lowest possible value for n1 */
  181. n1 = div_u64(div_u64(FDCO_MIN, hs_div), frequency);
  182. if (!n1 || (n1 & 1))
  183. n1++;
  184. while (n1 <= 128) {
  185. fdco = (u64)frequency * (u64)hs_div * (u64)n1;
  186. if (fdco > FDCO_MAX)
  187. break;
  188. if (fdco >= FDCO_MIN && fdco < best_fdco) {
  189. *out_n1 = n1;
  190. *out_hs_div = hs_div;
  191. *out_rfreq = div64_u64(fdco << 28, data->fxtal);
  192. best_fdco = fdco;
  193. }
  194. n1 += (n1 == 1 ? 1 : 2);
  195. }
  196. }
  197. if (best_fdco == ULLONG_MAX)
  198. return -EINVAL;
  199. return 0;
  200. }
  201. static unsigned long si570_recalc_rate(struct clk_hw *hw,
  202. unsigned long parent_rate)
  203. {
  204. int err;
  205. u64 rfreq, rate;
  206. unsigned int n1, hs_div;
  207. struct clk_si570 *data = to_clk_si570(hw);
  208. err = si570_get_divs(data, &rfreq, &n1, &hs_div);
  209. if (err) {
  210. dev_err(&data->i2c_client->dev, "unable to recalc rate\n");
  211. return data->frequency;
  212. }
  213. rfreq = div_u64(rfreq, hs_div * n1);
  214. rate = (data->fxtal * rfreq) >> 28;
  215. return rate;
  216. }
  217. static int si570_determine_rate(struct clk_hw *hw,
  218. struct clk_rate_request *req)
  219. {
  220. int err;
  221. u64 rfreq;
  222. unsigned int n1, hs_div;
  223. struct clk_si570 *data = to_clk_si570(hw);
  224. if (!req->rate) {
  225. req->rate = 0;
  226. return 0;
  227. }
  228. if (div64_u64(abs(req->rate - data->frequency) * 10000LL,
  229. data->frequency) < 35) {
  230. rfreq = div64_u64((data->rfreq * req->rate) +
  231. div64_u64(data->frequency, 2),
  232. data->frequency);
  233. n1 = data->n1;
  234. hs_div = data->hs_div;
  235. } else {
  236. err = si570_calc_divs(req->rate, data, &rfreq, &n1, &hs_div);
  237. if (err) {
  238. dev_err(&data->i2c_client->dev,
  239. "unable to round rate\n");
  240. req->rate = 0;
  241. return 0;
  242. }
  243. }
  244. return 0;
  245. }
  246. /**
  247. * si570_set_frequency() - Adjust output frequency
  248. * @data: Driver data structure
  249. * @frequency: Target frequency
  250. * Returns 0 on success.
  251. *
  252. * Update output frequency for big frequency changes (> 3,500 ppm).
  253. */
  254. static int si570_set_frequency(struct clk_si570 *data, unsigned long frequency)
  255. {
  256. int err;
  257. err = si570_calc_divs(frequency, data, &data->rfreq, &data->n1,
  258. &data->hs_div);
  259. if (err)
  260. return err;
  261. /*
  262. * The DCO reg should be accessed with a read-modify-write operation
  263. * per AN334
  264. */
  265. regmap_write(data->regmap, SI570_REG_FREEZE_DCO, SI570_FREEZE_DCO);
  266. regmap_write(data->regmap, SI570_REG_HS_N1 + data->div_offset,
  267. ((data->hs_div - HS_DIV_OFFSET) << HS_DIV_SHIFT) |
  268. (((data->n1 - 1) >> 2) & N1_6_2_MASK));
  269. si570_update_rfreq(data);
  270. regmap_write(data->regmap, SI570_REG_FREEZE_DCO, 0);
  271. regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_NEWFREQ);
  272. /* Applying a new frequency can take up to 10ms */
  273. usleep_range(10000, 12000);
  274. return 0;
  275. }
  276. /**
  277. * si570_set_frequency_small() - Adjust output frequency
  278. * @data: Driver data structure
  279. * @frequency: Target frequency
  280. * Returns 0 on success.
  281. *
  282. * Update output frequency for small frequency changes (< 3,500 ppm).
  283. */
  284. static int si570_set_frequency_small(struct clk_si570 *data,
  285. unsigned long frequency)
  286. {
  287. /*
  288. * This is a re-implementation of DIV_ROUND_CLOSEST
  289. * using the div64_u64 function lieu of letting the compiler
  290. * insert EABI calls
  291. */
  292. data->rfreq = div64_u64((data->rfreq * frequency) +
  293. div_u64(data->frequency, 2), data->frequency);
  294. regmap_write(data->regmap, SI570_REG_CONTROL, SI570_CNTRL_FREEZE_M);
  295. si570_update_rfreq(data);
  296. regmap_write(data->regmap, SI570_REG_CONTROL, 0);
  297. /* Applying a new frequency (small change) can take up to 100us */
  298. usleep_range(100, 200);
  299. return 0;
  300. }
  301. static int si570_set_rate(struct clk_hw *hw, unsigned long rate,
  302. unsigned long parent_rate)
  303. {
  304. struct clk_si570 *data = to_clk_si570(hw);
  305. struct i2c_client *client = data->i2c_client;
  306. int err;
  307. if (rate < SI570_MIN_FREQ || rate > data->info->max_freq) {
  308. dev_err(&client->dev,
  309. "requested frequency %lu Hz is out of range\n", rate);
  310. return -EINVAL;
  311. }
  312. if (div64_u64(abs(rate - data->frequency) * 10000LL,
  313. data->frequency) < 35)
  314. err = si570_set_frequency_small(data, rate);
  315. else
  316. err = si570_set_frequency(data, rate);
  317. if (err)
  318. return err;
  319. data->frequency = rate;
  320. return 0;
  321. }
  322. static const struct clk_ops si570_clk_ops = {
  323. .recalc_rate = si570_recalc_rate,
  324. .determine_rate = si570_determine_rate,
  325. .set_rate = si570_set_rate,
  326. };
  327. static bool si570_regmap_is_volatile(struct device *dev, unsigned int reg)
  328. {
  329. switch (reg) {
  330. case SI570_REG_CONTROL:
  331. return true;
  332. default:
  333. return false;
  334. }
  335. }
  336. static bool si570_regmap_is_writeable(struct device *dev, unsigned int reg)
  337. {
  338. switch (reg) {
  339. case SI570_REG_HS_N1 ... (SI570_REG_RFREQ4 + SI570_DIV_OFFSET_7PPM):
  340. case SI570_REG_CONTROL:
  341. case SI570_REG_FREEZE_DCO:
  342. return true;
  343. default:
  344. return false;
  345. }
  346. }
  347. static const struct regmap_config si570_regmap_config = {
  348. .reg_bits = 8,
  349. .val_bits = 8,
  350. .cache_type = REGCACHE_MAPLE,
  351. .max_register = 137,
  352. .writeable_reg = si570_regmap_is_writeable,
  353. .volatile_reg = si570_regmap_is_volatile,
  354. };
  355. static int si570_probe(struct i2c_client *client)
  356. {
  357. struct clk_si570 *data;
  358. struct clk_init_data init;
  359. u32 initial_fout, factory_fout, stability;
  360. bool skip_recall;
  361. int err;
  362. data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
  363. if (!data)
  364. return -ENOMEM;
  365. init.ops = &si570_clk_ops;
  366. init.flags = 0;
  367. init.num_parents = 0;
  368. data->hw.init = &init;
  369. data->i2c_client = client;
  370. data->info = i2c_get_match_data(client);
  371. if (data->info->has_temperature_stability) {
  372. err = of_property_read_u32(client->dev.of_node,
  373. "temperature-stability", &stability);
  374. if (err) {
  375. dev_err(&client->dev,
  376. "'temperature-stability' property missing\n");
  377. return err;
  378. }
  379. /* adjust register offsets for 7ppm devices */
  380. if (stability == 7)
  381. data->div_offset = SI570_DIV_OFFSET_7PPM;
  382. }
  383. if (of_property_read_string(client->dev.of_node, "clock-output-names",
  384. &init.name))
  385. init.name = client->dev.of_node->name;
  386. err = of_property_read_u32(client->dev.of_node, "factory-fout",
  387. &factory_fout);
  388. if (err) {
  389. dev_err(&client->dev, "'factory-fout' property missing\n");
  390. return err;
  391. }
  392. skip_recall = of_property_read_bool(client->dev.of_node,
  393. "silabs,skip-recall");
  394. data->regmap = devm_regmap_init_i2c(client, &si570_regmap_config);
  395. if (IS_ERR(data->regmap)) {
  396. dev_err(&client->dev, "failed to allocate register map\n");
  397. return PTR_ERR(data->regmap);
  398. }
  399. i2c_set_clientdata(client, data);
  400. err = si570_get_defaults(data, factory_fout, skip_recall);
  401. if (err)
  402. return err;
  403. err = devm_clk_hw_register(&client->dev, &data->hw);
  404. if (err) {
  405. dev_err(&client->dev, "clock registration failed\n");
  406. return err;
  407. }
  408. err = devm_of_clk_add_hw_provider(&client->dev, of_clk_hw_simple_get,
  409. &data->hw);
  410. if (err) {
  411. dev_err(&client->dev, "unable to add clk provider\n");
  412. return err;
  413. }
  414. /* Read the requested initial output frequency from device tree */
  415. if (!of_property_read_u32(client->dev.of_node, "clock-frequency",
  416. &initial_fout)) {
  417. err = clk_set_rate(data->hw.clk, initial_fout);
  418. if (err)
  419. return err;
  420. }
  421. /* Display a message indicating that we've successfully registered */
  422. dev_info(&client->dev, "registered, current frequency %llu Hz\n",
  423. data->frequency);
  424. return 0;
  425. }
  426. static const struct clk_si570_info clk_si570_info = {
  427. .max_freq = SI570_MAX_FREQ,
  428. .has_temperature_stability = true,
  429. };
  430. static const struct clk_si570_info clk_si590_info = {
  431. .max_freq = SI598_MAX_FREQ,
  432. };
  433. static const struct i2c_device_id si570_id[] = {
  434. { "si570", (kernel_ulong_t)&clk_si570_info },
  435. { "si571", (kernel_ulong_t)&clk_si570_info },
  436. { "si598", (kernel_ulong_t)&clk_si590_info },
  437. { "si599", (kernel_ulong_t)&clk_si590_info },
  438. { }
  439. };
  440. MODULE_DEVICE_TABLE(i2c, si570_id);
  441. static const struct of_device_id clk_si570_of_match[] = {
  442. { .compatible = "silabs,si570", .data = &clk_si570_info },
  443. { .compatible = "silabs,si571", .data = &clk_si570_info },
  444. { .compatible = "silabs,si598", .data = &clk_si590_info },
  445. { .compatible = "silabs,si599", .data = &clk_si590_info },
  446. { }
  447. };
  448. MODULE_DEVICE_TABLE(of, clk_si570_of_match);
  449. static struct i2c_driver si570_driver = {
  450. .driver = {
  451. .name = "si570",
  452. .of_match_table = clk_si570_of_match,
  453. },
  454. .probe = si570_probe,
  455. .id_table = si570_id,
  456. };
  457. module_i2c_driver(si570_driver);
  458. MODULE_AUTHOR("Guenter Roeck <guenter.roeck@ericsson.com>");
  459. MODULE_AUTHOR("Soeren Brinkmann <soren.brinkmann@xilinx.com>");
  460. MODULE_DESCRIPTION("Si570 driver");
  461. MODULE_LICENSE("GPL");