hci_qca.c 71 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Bluetooth Software UART Qualcomm protocol
  4. *
  5. * HCI_IBS (HCI In-Band Sleep) is Qualcomm's power management
  6. * protocol extension to H4.
  7. *
  8. * Copyright (C) 2007 Texas Instruments, Inc.
  9. * Copyright (c) 2010, 2012, 2018 The Linux Foundation. All rights reserved.
  10. *
  11. * Acknowledgements:
  12. * This file is based on hci_ll.c, which was...
  13. * Written by Ohad Ben-Cohen <ohad@bencohen.org>
  14. * which was in turn based on hci_h4.c, which was written
  15. * by Maxim Krasnyansky and Marcel Holtmann.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/clk.h>
  19. #include <linux/completion.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/delay.h>
  22. #include <linux/devcoredump.h>
  23. #include <linux/device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/mod_devicetable.h>
  26. #include <linux/module.h>
  27. #include <linux/of.h>
  28. #include <linux/acpi.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/pwrseq/consumer.h>
  31. #include <linux/regulator/consumer.h>
  32. #include <linux/serdev.h>
  33. #include <linux/string_choices.h>
  34. #include <linux/mutex.h>
  35. #include <linux/unaligned.h>
  36. #include <net/bluetooth/bluetooth.h>
  37. #include <net/bluetooth/hci_core.h>
  38. #include "hci_uart.h"
  39. #include "btqca.h"
  40. /* HCI_IBS protocol messages */
  41. #define HCI_IBS_SLEEP_IND 0xFE
  42. #define HCI_IBS_WAKE_IND 0xFD
  43. #define HCI_IBS_WAKE_ACK 0xFC
  44. #define HCI_MAX_IBS_SIZE 10
  45. #define IBS_WAKE_RETRANS_TIMEOUT_MS 100
  46. #define IBS_BTSOC_TX_IDLE_TIMEOUT_MS 200
  47. #define IBS_HOST_TX_IDLE_TIMEOUT_MS 2000
  48. #define CMD_TRANS_TIMEOUT_MS 100
  49. #define MEMDUMP_TIMEOUT_MS 8000
  50. #define IBS_DISABLE_SSR_TIMEOUT_MS \
  51. (MEMDUMP_TIMEOUT_MS + FW_DOWNLOAD_TIMEOUT_MS)
  52. #define FW_DOWNLOAD_TIMEOUT_MS 3000
  53. /* susclk rate */
  54. #define SUSCLK_RATE_32KHZ 32768
  55. /* Controller debug log header */
  56. #define QCA_DEBUG_HANDLE 0x2EDC
  57. /* max retry count when init fails */
  58. #define MAX_INIT_RETRIES 3
  59. /* Controller dump header */
  60. #define QCA_SSR_DUMP_HANDLE 0x0108
  61. #define QCA_DUMP_PACKET_SIZE 255
  62. #define QCA_LAST_SEQUENCE_NUM 0xFFFF
  63. #define QCA_CRASHBYTE_PACKET_LEN 1096
  64. #define QCA_MEMDUMP_BYTE 0xFB
  65. enum qca_flags {
  66. QCA_IBS_DISABLED,
  67. QCA_DROP_VENDOR_EVENT,
  68. QCA_SUSPENDING,
  69. QCA_MEMDUMP_COLLECTION,
  70. QCA_HW_ERROR_EVENT,
  71. QCA_SSR_TRIGGERED,
  72. QCA_BT_OFF,
  73. QCA_ROM_FW,
  74. QCA_DEBUGFS_CREATED,
  75. };
  76. enum qca_capabilities {
  77. QCA_CAP_WIDEBAND_SPEECH = BIT(0),
  78. QCA_CAP_VALID_LE_STATES = BIT(1),
  79. QCA_CAP_HFP_HW_OFFLOAD = BIT(2),
  80. };
  81. /* HCI_IBS transmit side sleep protocol states */
  82. enum tx_ibs_states {
  83. HCI_IBS_TX_ASLEEP,
  84. HCI_IBS_TX_WAKING,
  85. HCI_IBS_TX_AWAKE,
  86. };
  87. /* HCI_IBS receive side sleep protocol states */
  88. enum rx_states {
  89. HCI_IBS_RX_ASLEEP,
  90. HCI_IBS_RX_AWAKE,
  91. };
  92. /* HCI_IBS transmit and receive side clock state vote */
  93. enum hci_ibs_clock_state_vote {
  94. HCI_IBS_VOTE_STATS_UPDATE,
  95. HCI_IBS_TX_VOTE_CLOCK_ON,
  96. HCI_IBS_TX_VOTE_CLOCK_OFF,
  97. HCI_IBS_RX_VOTE_CLOCK_ON,
  98. HCI_IBS_RX_VOTE_CLOCK_OFF,
  99. };
  100. /* Controller memory dump states */
  101. enum qca_memdump_states {
  102. QCA_MEMDUMP_IDLE,
  103. QCA_MEMDUMP_COLLECTING,
  104. QCA_MEMDUMP_COLLECTED,
  105. QCA_MEMDUMP_TIMEOUT,
  106. };
  107. struct qca_memdump_info {
  108. u32 current_seq_no;
  109. u32 received_dump;
  110. u32 ram_dump_size;
  111. };
  112. struct qca_memdump_event_hdr {
  113. __u8 evt;
  114. __u8 plen;
  115. __u16 opcode;
  116. __le16 seq_no;
  117. __u8 reserved;
  118. } __packed;
  119. struct qca_dump_size {
  120. __le32 dump_size;
  121. } __packed;
  122. struct qca_data {
  123. struct hci_uart *hu;
  124. struct sk_buff *rx_skb;
  125. struct sk_buff_head txq;
  126. struct sk_buff_head tx_wait_q; /* HCI_IBS wait queue */
  127. struct sk_buff_head rx_memdump_q; /* Memdump wait queue */
  128. spinlock_t hci_ibs_lock; /* HCI_IBS state lock */
  129. u8 tx_ibs_state; /* HCI_IBS transmit side power state*/
  130. u8 rx_ibs_state; /* HCI_IBS receive side power state */
  131. bool tx_vote; /* Clock must be on for TX */
  132. bool rx_vote; /* Clock must be on for RX */
  133. struct timer_list tx_idle_timer;
  134. u32 tx_idle_delay;
  135. struct timer_list wake_retrans_timer;
  136. u32 wake_retrans;
  137. struct workqueue_struct *workqueue;
  138. struct work_struct ws_awake_rx;
  139. struct work_struct ws_awake_device;
  140. struct work_struct ws_rx_vote_off;
  141. struct work_struct ws_tx_vote_off;
  142. struct work_struct ctrl_memdump_evt;
  143. struct delayed_work ctrl_memdump_timeout;
  144. struct qca_memdump_info *qca_memdump;
  145. unsigned long flags;
  146. struct completion drop_ev_comp;
  147. wait_queue_head_t suspend_wait_q;
  148. enum qca_memdump_states memdump_state;
  149. struct mutex hci_memdump_lock;
  150. u16 fw_version;
  151. u16 controller_id;
  152. /* For debugging purpose */
  153. u64 ibs_sent_wacks;
  154. u64 ibs_sent_slps;
  155. u64 ibs_sent_wakes;
  156. u64 ibs_recv_wacks;
  157. u64 ibs_recv_slps;
  158. u64 ibs_recv_wakes;
  159. u64 vote_last_jif;
  160. u32 vote_on_ms;
  161. u32 vote_off_ms;
  162. u64 tx_votes_on;
  163. u64 rx_votes_on;
  164. u64 tx_votes_off;
  165. u64 rx_votes_off;
  166. u64 votes_on;
  167. u64 votes_off;
  168. };
  169. enum qca_speed_type {
  170. QCA_INIT_SPEED = 1,
  171. QCA_OPER_SPEED
  172. };
  173. /*
  174. * Voltage regulator information required for configuring the
  175. * QCA Bluetooth chipset
  176. */
  177. struct qca_vreg {
  178. const char *name;
  179. unsigned int load_uA;
  180. };
  181. struct qca_device_data {
  182. enum qca_btsoc_type soc_type;
  183. struct qca_vreg *vregs;
  184. size_t num_vregs;
  185. uint32_t capabilities;
  186. };
  187. /*
  188. * Platform data for the QCA Bluetooth power driver.
  189. */
  190. struct qca_power {
  191. struct device *dev;
  192. struct regulator_bulk_data *vreg_bulk;
  193. int num_vregs;
  194. bool vregs_on;
  195. struct pwrseq_desc *pwrseq;
  196. };
  197. struct qca_serdev {
  198. struct hci_uart serdev_hu;
  199. struct gpio_desc *bt_en;
  200. struct gpio_desc *sw_ctrl;
  201. struct clk *susclk;
  202. enum qca_btsoc_type btsoc_type;
  203. struct qca_power *bt_power;
  204. u32 init_speed;
  205. u32 oper_speed;
  206. bool bdaddr_property_broken;
  207. bool support_hfp_hw_offload;
  208. const char *firmware_name[2];
  209. };
  210. static int qca_regulator_enable(struct qca_serdev *qcadev);
  211. static void qca_regulator_disable(struct qca_serdev *qcadev);
  212. static void qca_power_shutdown(struct hci_uart *hu);
  213. static int qca_power_off(struct hci_dev *hdev);
  214. static void qca_controller_memdump(struct work_struct *work);
  215. static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb);
  216. static enum qca_btsoc_type qca_soc_type(struct hci_uart *hu)
  217. {
  218. enum qca_btsoc_type soc_type;
  219. if (hu->serdev) {
  220. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  221. soc_type = qsd->btsoc_type;
  222. } else {
  223. soc_type = QCA_ROME;
  224. }
  225. return soc_type;
  226. }
  227. static const char *qca_get_firmware_name(struct hci_uart *hu)
  228. {
  229. if (hu->serdev) {
  230. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  231. return qsd->firmware_name[0];
  232. } else {
  233. return NULL;
  234. }
  235. }
  236. static const char *qca_get_rampatch_name(struct hci_uart *hu)
  237. {
  238. if (hu->serdev) {
  239. struct qca_serdev *qsd = serdev_device_get_drvdata(hu->serdev);
  240. return qsd->firmware_name[1];
  241. } else {
  242. return NULL;
  243. }
  244. }
  245. static void __serial_clock_on(struct tty_struct *tty)
  246. {
  247. /* TODO: Some chipset requires to enable UART clock on client
  248. * side to save power consumption or manual work is required.
  249. * Please put your code to control UART clock here if needed
  250. */
  251. }
  252. static void __serial_clock_off(struct tty_struct *tty)
  253. {
  254. /* TODO: Some chipset requires to disable UART clock on client
  255. * side to save power consumption or manual work is required.
  256. * Please put your code to control UART clock off here if needed
  257. */
  258. }
  259. /* serial_clock_vote needs to be called with the ibs lock held */
  260. static void serial_clock_vote(unsigned long vote, struct hci_uart *hu)
  261. {
  262. struct qca_data *qca = hu->priv;
  263. unsigned int diff;
  264. bool old_vote = (qca->tx_vote | qca->rx_vote);
  265. bool new_vote;
  266. switch (vote) {
  267. case HCI_IBS_VOTE_STATS_UPDATE:
  268. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  269. if (old_vote)
  270. qca->vote_off_ms += diff;
  271. else
  272. qca->vote_on_ms += diff;
  273. return;
  274. case HCI_IBS_TX_VOTE_CLOCK_ON:
  275. qca->tx_vote = true;
  276. qca->tx_votes_on++;
  277. break;
  278. case HCI_IBS_RX_VOTE_CLOCK_ON:
  279. qca->rx_vote = true;
  280. qca->rx_votes_on++;
  281. break;
  282. case HCI_IBS_TX_VOTE_CLOCK_OFF:
  283. qca->tx_vote = false;
  284. qca->tx_votes_off++;
  285. break;
  286. case HCI_IBS_RX_VOTE_CLOCK_OFF:
  287. qca->rx_vote = false;
  288. qca->rx_votes_off++;
  289. break;
  290. default:
  291. BT_ERR("Voting irregularity");
  292. return;
  293. }
  294. new_vote = qca->rx_vote | qca->tx_vote;
  295. if (new_vote != old_vote) {
  296. if (new_vote)
  297. __serial_clock_on(hu->tty);
  298. else
  299. __serial_clock_off(hu->tty);
  300. BT_DBG("Vote serial clock %s(%s)", str_true_false(new_vote),
  301. str_true_false(vote));
  302. diff = jiffies_to_msecs(jiffies - qca->vote_last_jif);
  303. if (new_vote) {
  304. qca->votes_on++;
  305. qca->vote_off_ms += diff;
  306. } else {
  307. qca->votes_off++;
  308. qca->vote_on_ms += diff;
  309. }
  310. qca->vote_last_jif = jiffies;
  311. }
  312. }
  313. /* Builds and sends an HCI_IBS command packet.
  314. * These are very simple packets with only 1 cmd byte.
  315. */
  316. static int send_hci_ibs_cmd(u8 cmd, struct hci_uart *hu)
  317. {
  318. int err = 0;
  319. struct sk_buff *skb = NULL;
  320. struct qca_data *qca = hu->priv;
  321. BT_DBG("hu %p send hci ibs cmd 0x%x", hu, cmd);
  322. skb = bt_skb_alloc(1, GFP_ATOMIC);
  323. if (!skb) {
  324. BT_ERR("Failed to allocate memory for HCI_IBS packet");
  325. return -ENOMEM;
  326. }
  327. /* Assign HCI_IBS type */
  328. skb_put_u8(skb, cmd);
  329. skb_queue_tail(&qca->txq, skb);
  330. return err;
  331. }
  332. static void qca_wq_awake_device(struct work_struct *work)
  333. {
  334. struct qca_data *qca = container_of(work, struct qca_data,
  335. ws_awake_device);
  336. struct hci_uart *hu = qca->hu;
  337. unsigned long retrans_delay;
  338. unsigned long flags;
  339. BT_DBG("hu %p wq awake device", hu);
  340. /* Vote for serial clock */
  341. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_ON, hu);
  342. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  343. /* Send wake indication to device */
  344. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0)
  345. BT_ERR("Failed to send WAKE to device");
  346. qca->ibs_sent_wakes++;
  347. /* Start retransmit timer */
  348. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  349. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  350. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  351. /* Actually send the packets */
  352. hci_uart_tx_wakeup(hu);
  353. }
  354. static void qca_wq_awake_rx(struct work_struct *work)
  355. {
  356. struct qca_data *qca = container_of(work, struct qca_data,
  357. ws_awake_rx);
  358. struct hci_uart *hu = qca->hu;
  359. unsigned long flags;
  360. BT_DBG("hu %p wq awake rx", hu);
  361. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_ON, hu);
  362. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  363. qca->rx_ibs_state = HCI_IBS_RX_AWAKE;
  364. /* Always acknowledge device wake up,
  365. * sending IBS message doesn't count as TX ON.
  366. */
  367. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0)
  368. BT_ERR("Failed to acknowledge device wake up");
  369. qca->ibs_sent_wacks++;
  370. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  371. /* Actually send the packets */
  372. hci_uart_tx_wakeup(hu);
  373. }
  374. static void qca_wq_serial_rx_clock_vote_off(struct work_struct *work)
  375. {
  376. struct qca_data *qca = container_of(work, struct qca_data,
  377. ws_rx_vote_off);
  378. struct hci_uart *hu = qca->hu;
  379. BT_DBG("hu %p rx clock vote off", hu);
  380. serial_clock_vote(HCI_IBS_RX_VOTE_CLOCK_OFF, hu);
  381. }
  382. static void qca_wq_serial_tx_clock_vote_off(struct work_struct *work)
  383. {
  384. struct qca_data *qca = container_of(work, struct qca_data,
  385. ws_tx_vote_off);
  386. struct hci_uart *hu = qca->hu;
  387. BT_DBG("hu %p tx clock vote off", hu);
  388. /* Run HCI tx handling unlocked */
  389. hci_uart_tx_wakeup(hu);
  390. /* Now that message queued to tty driver, vote for tty clocks off.
  391. * It is up to the tty driver to pend the clocks off until tx done.
  392. */
  393. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  394. }
  395. static void hci_ibs_tx_idle_timeout(struct timer_list *t)
  396. {
  397. struct qca_data *qca = timer_container_of(qca, t, tx_idle_timer);
  398. struct hci_uart *hu = qca->hu;
  399. unsigned long flags;
  400. BT_DBG("hu %p idle timeout in %d state", hu, qca->tx_ibs_state);
  401. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  402. flags, SINGLE_DEPTH_NESTING);
  403. switch (qca->tx_ibs_state) {
  404. case HCI_IBS_TX_AWAKE:
  405. /* TX_IDLE, go to SLEEP */
  406. if (send_hci_ibs_cmd(HCI_IBS_SLEEP_IND, hu) < 0) {
  407. BT_ERR("Failed to send SLEEP to device");
  408. break;
  409. }
  410. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  411. qca->ibs_sent_slps++;
  412. queue_work(qca->workqueue, &qca->ws_tx_vote_off);
  413. break;
  414. case HCI_IBS_TX_ASLEEP:
  415. case HCI_IBS_TX_WAKING:
  416. default:
  417. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  418. break;
  419. }
  420. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  421. }
  422. static void hci_ibs_wake_retrans_timeout(struct timer_list *t)
  423. {
  424. struct qca_data *qca = timer_container_of(qca, t, wake_retrans_timer);
  425. struct hci_uart *hu = qca->hu;
  426. unsigned long flags, retrans_delay;
  427. bool retransmit = false;
  428. BT_DBG("hu %p wake retransmit timeout in %d state",
  429. hu, qca->tx_ibs_state);
  430. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  431. flags, SINGLE_DEPTH_NESTING);
  432. /* Don't retransmit the HCI_IBS_WAKE_IND when suspending. */
  433. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  434. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  435. return;
  436. }
  437. switch (qca->tx_ibs_state) {
  438. case HCI_IBS_TX_WAKING:
  439. /* No WAKE_ACK, retransmit WAKE */
  440. retransmit = true;
  441. if (send_hci_ibs_cmd(HCI_IBS_WAKE_IND, hu) < 0) {
  442. BT_ERR("Failed to acknowledge device wake up");
  443. break;
  444. }
  445. qca->ibs_sent_wakes++;
  446. retrans_delay = msecs_to_jiffies(qca->wake_retrans);
  447. mod_timer(&qca->wake_retrans_timer, jiffies + retrans_delay);
  448. break;
  449. case HCI_IBS_TX_ASLEEP:
  450. case HCI_IBS_TX_AWAKE:
  451. default:
  452. BT_ERR("Spurious timeout tx state %d", qca->tx_ibs_state);
  453. break;
  454. }
  455. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  456. if (retransmit)
  457. hci_uart_tx_wakeup(hu);
  458. }
  459. static void qca_controller_memdump_timeout(struct work_struct *work)
  460. {
  461. struct qca_data *qca = container_of(work, struct qca_data,
  462. ctrl_memdump_timeout.work);
  463. struct hci_uart *hu = qca->hu;
  464. mutex_lock(&qca->hci_memdump_lock);
  465. if (test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
  466. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  467. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  468. /* Inject hw error event to reset the device
  469. * and driver.
  470. */
  471. hci_reset_dev(hu->hdev);
  472. }
  473. }
  474. mutex_unlock(&qca->hci_memdump_lock);
  475. }
  476. /* Initialize protocol */
  477. static int qca_open(struct hci_uart *hu)
  478. {
  479. struct qca_serdev *qcadev;
  480. struct qca_data *qca;
  481. BT_DBG("hu %p qca_open", hu);
  482. if (!hci_uart_has_flow_control(hu))
  483. return -EOPNOTSUPP;
  484. qca = kzalloc_obj(*qca);
  485. if (!qca)
  486. return -ENOMEM;
  487. skb_queue_head_init(&qca->txq);
  488. skb_queue_head_init(&qca->tx_wait_q);
  489. skb_queue_head_init(&qca->rx_memdump_q);
  490. spin_lock_init(&qca->hci_ibs_lock);
  491. mutex_init(&qca->hci_memdump_lock);
  492. qca->workqueue = alloc_ordered_workqueue("qca_wq", 0);
  493. if (!qca->workqueue) {
  494. BT_ERR("QCA Workqueue not initialized properly");
  495. kfree(qca);
  496. return -ENOMEM;
  497. }
  498. INIT_WORK(&qca->ws_awake_rx, qca_wq_awake_rx);
  499. INIT_WORK(&qca->ws_awake_device, qca_wq_awake_device);
  500. INIT_WORK(&qca->ws_rx_vote_off, qca_wq_serial_rx_clock_vote_off);
  501. INIT_WORK(&qca->ws_tx_vote_off, qca_wq_serial_tx_clock_vote_off);
  502. INIT_WORK(&qca->ctrl_memdump_evt, qca_controller_memdump);
  503. INIT_DELAYED_WORK(&qca->ctrl_memdump_timeout,
  504. qca_controller_memdump_timeout);
  505. init_waitqueue_head(&qca->suspend_wait_q);
  506. qca->hu = hu;
  507. init_completion(&qca->drop_ev_comp);
  508. /* Assume we start with both sides asleep -- extra wakes OK */
  509. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  510. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  511. qca->vote_last_jif = jiffies;
  512. hu->priv = qca;
  513. if (hu->serdev) {
  514. qcadev = serdev_device_get_drvdata(hu->serdev);
  515. switch (qcadev->btsoc_type) {
  516. case QCA_WCN3950:
  517. case QCA_WCN3988:
  518. case QCA_WCN3990:
  519. case QCA_WCN3991:
  520. case QCA_WCN3998:
  521. case QCA_WCN6750:
  522. hu->init_speed = qcadev->init_speed;
  523. break;
  524. default:
  525. break;
  526. }
  527. if (qcadev->oper_speed)
  528. hu->oper_speed = qcadev->oper_speed;
  529. }
  530. timer_setup(&qca->wake_retrans_timer, hci_ibs_wake_retrans_timeout, 0);
  531. qca->wake_retrans = IBS_WAKE_RETRANS_TIMEOUT_MS;
  532. timer_setup(&qca->tx_idle_timer, hci_ibs_tx_idle_timeout, 0);
  533. qca->tx_idle_delay = IBS_HOST_TX_IDLE_TIMEOUT_MS;
  534. BT_DBG("HCI_UART_QCA open, tx_idle_delay=%u, wake_retrans=%u",
  535. qca->tx_idle_delay, qca->wake_retrans);
  536. return 0;
  537. }
  538. static void qca_debugfs_init(struct hci_dev *hdev)
  539. {
  540. struct hci_uart *hu = hci_get_drvdata(hdev);
  541. struct qca_data *qca = hu->priv;
  542. struct dentry *ibs_dir;
  543. umode_t mode;
  544. if (!hdev->debugfs)
  545. return;
  546. if (test_and_set_bit(QCA_DEBUGFS_CREATED, &qca->flags))
  547. return;
  548. ibs_dir = debugfs_create_dir("ibs", hdev->debugfs);
  549. /* read only */
  550. mode = 0444;
  551. debugfs_create_u8("tx_ibs_state", mode, ibs_dir, &qca->tx_ibs_state);
  552. debugfs_create_u8("rx_ibs_state", mode, ibs_dir, &qca->rx_ibs_state);
  553. debugfs_create_u64("ibs_sent_sleeps", mode, ibs_dir,
  554. &qca->ibs_sent_slps);
  555. debugfs_create_u64("ibs_sent_wakes", mode, ibs_dir,
  556. &qca->ibs_sent_wakes);
  557. debugfs_create_u64("ibs_sent_wake_acks", mode, ibs_dir,
  558. &qca->ibs_sent_wacks);
  559. debugfs_create_u64("ibs_recv_sleeps", mode, ibs_dir,
  560. &qca->ibs_recv_slps);
  561. debugfs_create_u64("ibs_recv_wakes", mode, ibs_dir,
  562. &qca->ibs_recv_wakes);
  563. debugfs_create_u64("ibs_recv_wake_acks", mode, ibs_dir,
  564. &qca->ibs_recv_wacks);
  565. debugfs_create_bool("tx_vote", mode, ibs_dir, &qca->tx_vote);
  566. debugfs_create_u64("tx_votes_on", mode, ibs_dir, &qca->tx_votes_on);
  567. debugfs_create_u64("tx_votes_off", mode, ibs_dir, &qca->tx_votes_off);
  568. debugfs_create_bool("rx_vote", mode, ibs_dir, &qca->rx_vote);
  569. debugfs_create_u64("rx_votes_on", mode, ibs_dir, &qca->rx_votes_on);
  570. debugfs_create_u64("rx_votes_off", mode, ibs_dir, &qca->rx_votes_off);
  571. debugfs_create_u64("votes_on", mode, ibs_dir, &qca->votes_on);
  572. debugfs_create_u64("votes_off", mode, ibs_dir, &qca->votes_off);
  573. debugfs_create_u32("vote_on_ms", mode, ibs_dir, &qca->vote_on_ms);
  574. debugfs_create_u32("vote_off_ms", mode, ibs_dir, &qca->vote_off_ms);
  575. /* read/write */
  576. mode = 0644;
  577. debugfs_create_u32("wake_retrans", mode, ibs_dir, &qca->wake_retrans);
  578. debugfs_create_u32("tx_idle_delay", mode, ibs_dir,
  579. &qca->tx_idle_delay);
  580. }
  581. /* Flush protocol data */
  582. static int qca_flush(struct hci_uart *hu)
  583. {
  584. struct qca_data *qca = hu->priv;
  585. BT_DBG("hu %p qca flush", hu);
  586. skb_queue_purge(&qca->tx_wait_q);
  587. skb_queue_purge(&qca->txq);
  588. return 0;
  589. }
  590. /* Close protocol */
  591. static int qca_close(struct hci_uart *hu)
  592. {
  593. struct qca_data *qca = hu->priv;
  594. BT_DBG("hu %p qca close", hu);
  595. serial_clock_vote(HCI_IBS_VOTE_STATS_UPDATE, hu);
  596. skb_queue_purge(&qca->tx_wait_q);
  597. skb_queue_purge(&qca->txq);
  598. skb_queue_purge(&qca->rx_memdump_q);
  599. /*
  600. * Shut the timers down so they can't be rearmed when
  601. * destroy_workqueue() drains pending work which in turn might try
  602. * to arm a timer. After shutdown rearm attempts are silently
  603. * ignored by the timer core code.
  604. */
  605. timer_shutdown_sync(&qca->tx_idle_timer);
  606. timer_shutdown_sync(&qca->wake_retrans_timer);
  607. destroy_workqueue(qca->workqueue);
  608. qca->hu = NULL;
  609. kfree_skb(qca->rx_skb);
  610. hu->priv = NULL;
  611. kfree(qca);
  612. return 0;
  613. }
  614. /* Called upon a wake-up-indication from the device.
  615. */
  616. static void device_want_to_wakeup(struct hci_uart *hu)
  617. {
  618. unsigned long flags;
  619. struct qca_data *qca = hu->priv;
  620. BT_DBG("hu %p want to wake up", hu);
  621. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  622. qca->ibs_recv_wakes++;
  623. /* Don't wake the rx up when suspending. */
  624. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  625. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  626. return;
  627. }
  628. switch (qca->rx_ibs_state) {
  629. case HCI_IBS_RX_ASLEEP:
  630. /* Make sure clock is on - we may have turned clock off since
  631. * receiving the wake up indicator awake rx clock.
  632. */
  633. queue_work(qca->workqueue, &qca->ws_awake_rx);
  634. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  635. return;
  636. case HCI_IBS_RX_AWAKE:
  637. /* Always acknowledge device wake up,
  638. * sending IBS message doesn't count as TX ON.
  639. */
  640. if (send_hci_ibs_cmd(HCI_IBS_WAKE_ACK, hu) < 0) {
  641. BT_ERR("Failed to acknowledge device wake up");
  642. break;
  643. }
  644. qca->ibs_sent_wacks++;
  645. break;
  646. default:
  647. /* Any other state is illegal */
  648. BT_ERR("Received HCI_IBS_WAKE_IND in rx state %d",
  649. qca->rx_ibs_state);
  650. break;
  651. }
  652. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  653. /* Actually send the packets */
  654. hci_uart_tx_wakeup(hu);
  655. }
  656. /* Called upon a sleep-indication from the device.
  657. */
  658. static void device_want_to_sleep(struct hci_uart *hu)
  659. {
  660. unsigned long flags;
  661. struct qca_data *qca = hu->priv;
  662. BT_DBG("hu %p want to sleep in %d state", hu, qca->rx_ibs_state);
  663. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  664. qca->ibs_recv_slps++;
  665. switch (qca->rx_ibs_state) {
  666. case HCI_IBS_RX_AWAKE:
  667. /* Update state */
  668. qca->rx_ibs_state = HCI_IBS_RX_ASLEEP;
  669. /* Vote off rx clock under workqueue */
  670. queue_work(qca->workqueue, &qca->ws_rx_vote_off);
  671. break;
  672. case HCI_IBS_RX_ASLEEP:
  673. break;
  674. default:
  675. /* Any other state is illegal */
  676. BT_ERR("Received HCI_IBS_SLEEP_IND in rx state %d",
  677. qca->rx_ibs_state);
  678. break;
  679. }
  680. wake_up_interruptible(&qca->suspend_wait_q);
  681. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  682. }
  683. /* Called upon wake-up-acknowledgement from the device
  684. */
  685. static void device_woke_up(struct hci_uart *hu)
  686. {
  687. unsigned long flags, idle_delay;
  688. struct qca_data *qca = hu->priv;
  689. struct sk_buff *skb = NULL;
  690. BT_DBG("hu %p woke up", hu);
  691. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  692. qca->ibs_recv_wacks++;
  693. /* Don't react to the wake-up-acknowledgment when suspending. */
  694. if (test_bit(QCA_SUSPENDING, &qca->flags)) {
  695. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  696. return;
  697. }
  698. switch (qca->tx_ibs_state) {
  699. case HCI_IBS_TX_AWAKE:
  700. /* Expect one if we send 2 WAKEs */
  701. BT_DBG("Received HCI_IBS_WAKE_ACK in tx state %d",
  702. qca->tx_ibs_state);
  703. break;
  704. case HCI_IBS_TX_WAKING:
  705. /* Send pending packets */
  706. while ((skb = skb_dequeue(&qca->tx_wait_q)))
  707. skb_queue_tail(&qca->txq, skb);
  708. /* Switch timers and change state to HCI_IBS_TX_AWAKE */
  709. timer_delete(&qca->wake_retrans_timer);
  710. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  711. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  712. qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
  713. break;
  714. case HCI_IBS_TX_ASLEEP:
  715. default:
  716. BT_ERR("Received HCI_IBS_WAKE_ACK in tx state %d",
  717. qca->tx_ibs_state);
  718. break;
  719. }
  720. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  721. /* Actually send the packets */
  722. hci_uart_tx_wakeup(hu);
  723. }
  724. /* Enqueue frame for transmission (padding, crc, etc) may be called from
  725. * two simultaneous tasklets.
  726. */
  727. static int qca_enqueue(struct hci_uart *hu, struct sk_buff *skb)
  728. {
  729. unsigned long flags = 0, idle_delay;
  730. struct qca_data *qca = hu->priv;
  731. BT_DBG("hu %p qca enq skb %p tx_ibs_state %d", hu, skb,
  732. qca->tx_ibs_state);
  733. if (test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  734. /* As SSR is in progress, ignore the packets */
  735. bt_dev_dbg(hu->hdev, "SSR is in progress");
  736. kfree_skb(skb);
  737. return 0;
  738. }
  739. /* Prepend skb with frame type */
  740. memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
  741. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  742. /* Don't go to sleep in middle of patch download or
  743. * Out-Of-Band(GPIOs control) sleep is selected.
  744. * Don't wake the device up when suspending.
  745. */
  746. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  747. test_bit(QCA_SUSPENDING, &qca->flags)) {
  748. skb_queue_tail(&qca->txq, skb);
  749. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  750. return 0;
  751. }
  752. /* Act according to current state */
  753. switch (qca->tx_ibs_state) {
  754. case HCI_IBS_TX_AWAKE:
  755. BT_DBG("Device awake, sending normally");
  756. skb_queue_tail(&qca->txq, skb);
  757. idle_delay = msecs_to_jiffies(qca->tx_idle_delay);
  758. mod_timer(&qca->tx_idle_timer, jiffies + idle_delay);
  759. break;
  760. case HCI_IBS_TX_ASLEEP:
  761. BT_DBG("Device asleep, waking up and queueing packet");
  762. /* Save packet for later */
  763. skb_queue_tail(&qca->tx_wait_q, skb);
  764. qca->tx_ibs_state = HCI_IBS_TX_WAKING;
  765. /* Schedule a work queue to wake up device */
  766. queue_work(qca->workqueue, &qca->ws_awake_device);
  767. break;
  768. case HCI_IBS_TX_WAKING:
  769. BT_DBG("Device waking up, queueing packet");
  770. /* Transient state; just keep packet for later */
  771. skb_queue_tail(&qca->tx_wait_q, skb);
  772. break;
  773. default:
  774. BT_ERR("Illegal tx state: %d (losing packet)",
  775. qca->tx_ibs_state);
  776. dev_kfree_skb_irq(skb);
  777. break;
  778. }
  779. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  780. return 0;
  781. }
  782. static int qca_ibs_sleep_ind(struct hci_dev *hdev, struct sk_buff *skb)
  783. {
  784. struct hci_uart *hu = hci_get_drvdata(hdev);
  785. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_SLEEP_IND);
  786. device_want_to_sleep(hu);
  787. kfree_skb(skb);
  788. return 0;
  789. }
  790. static int qca_ibs_wake_ind(struct hci_dev *hdev, struct sk_buff *skb)
  791. {
  792. struct hci_uart *hu = hci_get_drvdata(hdev);
  793. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_IND);
  794. device_want_to_wakeup(hu);
  795. kfree_skb(skb);
  796. return 0;
  797. }
  798. static int qca_ibs_wake_ack(struct hci_dev *hdev, struct sk_buff *skb)
  799. {
  800. struct hci_uart *hu = hci_get_drvdata(hdev);
  801. BT_DBG("hu %p recv hci ibs cmd 0x%x", hu, HCI_IBS_WAKE_ACK);
  802. device_woke_up(hu);
  803. kfree_skb(skb);
  804. return 0;
  805. }
  806. static int qca_recv_acl_data(struct hci_dev *hdev, struct sk_buff *skb)
  807. {
  808. /* We receive debug logs from chip as an ACL packets.
  809. * Instead of sending the data to ACL to decode the
  810. * received data, we are pushing them to the above layers
  811. * as a diagnostic packet.
  812. */
  813. if (get_unaligned_le16(skb->data) == QCA_DEBUG_HANDLE)
  814. return hci_recv_diag(hdev, skb);
  815. return hci_recv_frame(hdev, skb);
  816. }
  817. static void qca_dmp_hdr(struct hci_dev *hdev, struct sk_buff *skb)
  818. {
  819. struct hci_uart *hu = hci_get_drvdata(hdev);
  820. struct qca_data *qca = hu->priv;
  821. char buf[80];
  822. snprintf(buf, sizeof(buf), "Controller Name: 0x%x\n",
  823. qca->controller_id);
  824. skb_put_data(skb, buf, strlen(buf));
  825. snprintf(buf, sizeof(buf), "Firmware Version: 0x%x\n",
  826. qca->fw_version);
  827. skb_put_data(skb, buf, strlen(buf));
  828. snprintf(buf, sizeof(buf), "Vendor:Qualcomm\n");
  829. skb_put_data(skb, buf, strlen(buf));
  830. snprintf(buf, sizeof(buf), "Driver: %s\n",
  831. hu->serdev->dev.driver->name);
  832. skb_put_data(skb, buf, strlen(buf));
  833. }
  834. static void qca_controller_memdump(struct work_struct *work)
  835. {
  836. struct qca_data *qca = container_of(work, struct qca_data,
  837. ctrl_memdump_evt);
  838. struct hci_uart *hu = qca->hu;
  839. struct sk_buff *skb;
  840. struct qca_memdump_event_hdr *cmd_hdr;
  841. struct qca_memdump_info *qca_memdump = qca->qca_memdump;
  842. struct qca_dump_size *dump;
  843. u16 seq_no;
  844. u32 rx_size;
  845. int ret = 0;
  846. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  847. while ((skb = skb_dequeue(&qca->rx_memdump_q))) {
  848. mutex_lock(&qca->hci_memdump_lock);
  849. /* Skip processing the received packets if timeout detected
  850. * or memdump collection completed.
  851. */
  852. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  853. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  854. mutex_unlock(&qca->hci_memdump_lock);
  855. return;
  856. }
  857. if (!qca_memdump) {
  858. qca_memdump = kzalloc_obj(*qca_memdump, GFP_ATOMIC);
  859. if (!qca_memdump) {
  860. mutex_unlock(&qca->hci_memdump_lock);
  861. return;
  862. }
  863. qca->qca_memdump = qca_memdump;
  864. }
  865. qca->memdump_state = QCA_MEMDUMP_COLLECTING;
  866. cmd_hdr = (void *) skb->data;
  867. seq_no = __le16_to_cpu(cmd_hdr->seq_no);
  868. skb_pull(skb, sizeof(struct qca_memdump_event_hdr));
  869. if (!seq_no) {
  870. /* This is the first frame of memdump packet from
  871. * the controller, Disable IBS to receive dump
  872. * with out any interruption, ideally time required for
  873. * the controller to send the dump is 8 seconds. let us
  874. * start timer to handle this asynchronous activity.
  875. */
  876. set_bit(QCA_IBS_DISABLED, &qca->flags);
  877. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  878. dump = (void *) skb->data;
  879. qca_memdump->ram_dump_size = __le32_to_cpu(dump->dump_size);
  880. if (!(qca_memdump->ram_dump_size)) {
  881. bt_dev_err(hu->hdev, "Rx invalid memdump size");
  882. kfree(qca_memdump);
  883. kfree_skb(skb);
  884. mutex_unlock(&qca->hci_memdump_lock);
  885. return;
  886. }
  887. queue_delayed_work(qca->workqueue,
  888. &qca->ctrl_memdump_timeout,
  889. msecs_to_jiffies(MEMDUMP_TIMEOUT_MS));
  890. skb_pull(skb, sizeof(qca_memdump->ram_dump_size));
  891. qca_memdump->current_seq_no = 0;
  892. qca_memdump->received_dump = 0;
  893. ret = hci_devcd_init(hu->hdev, qca_memdump->ram_dump_size);
  894. bt_dev_info(hu->hdev, "hci_devcd_init Return:%d",
  895. ret);
  896. if (ret < 0) {
  897. kfree(qca->qca_memdump);
  898. qca->qca_memdump = NULL;
  899. qca->memdump_state = QCA_MEMDUMP_COLLECTED;
  900. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  901. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  902. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  903. mutex_unlock(&qca->hci_memdump_lock);
  904. return;
  905. }
  906. bt_dev_info(hu->hdev, "QCA collecting dump of size:%u",
  907. qca_memdump->ram_dump_size);
  908. }
  909. /* If sequence no 0 is missed then there is no point in
  910. * accepting the other sequences.
  911. */
  912. if (!test_bit(QCA_MEMDUMP_COLLECTION, &qca->flags)) {
  913. bt_dev_err(hu->hdev, "QCA: Discarding other packets");
  914. kfree(qca_memdump);
  915. kfree_skb(skb);
  916. mutex_unlock(&qca->hci_memdump_lock);
  917. return;
  918. }
  919. /* There could be chance of missing some packets from
  920. * the controller. In such cases let us store the dummy
  921. * packets in the buffer.
  922. */
  923. /* For QCA6390, controller does not lost packets but
  924. * sequence number field of packet sometimes has error
  925. * bits, so skip this checking for missing packet.
  926. */
  927. while ((seq_no > qca_memdump->current_seq_no + 1) &&
  928. (soc_type != QCA_QCA6390) &&
  929. seq_no != QCA_LAST_SEQUENCE_NUM) {
  930. bt_dev_err(hu->hdev, "QCA controller missed packet:%d",
  931. qca_memdump->current_seq_no);
  932. rx_size = qca_memdump->received_dump;
  933. rx_size += QCA_DUMP_PACKET_SIZE;
  934. if (rx_size > qca_memdump->ram_dump_size) {
  935. bt_dev_err(hu->hdev,
  936. "QCA memdump received %d, no space for missed packet",
  937. qca_memdump->received_dump);
  938. break;
  939. }
  940. hci_devcd_append_pattern(hu->hdev, 0x00,
  941. QCA_DUMP_PACKET_SIZE);
  942. qca_memdump->received_dump += QCA_DUMP_PACKET_SIZE;
  943. qca_memdump->current_seq_no++;
  944. }
  945. rx_size = qca_memdump->received_dump + skb->len;
  946. if (rx_size <= qca_memdump->ram_dump_size) {
  947. if ((seq_no != QCA_LAST_SEQUENCE_NUM) &&
  948. (seq_no != qca_memdump->current_seq_no)) {
  949. bt_dev_err(hu->hdev,
  950. "QCA memdump unexpected packet %d",
  951. seq_no);
  952. }
  953. bt_dev_dbg(hu->hdev,
  954. "QCA memdump packet %d with length %d",
  955. seq_no, skb->len);
  956. hci_devcd_append(hu->hdev, skb);
  957. qca_memdump->current_seq_no += 1;
  958. qca_memdump->received_dump = rx_size;
  959. } else {
  960. bt_dev_err(hu->hdev,
  961. "QCA memdump received no space for packet %d",
  962. qca_memdump->current_seq_no);
  963. }
  964. if (seq_no == QCA_LAST_SEQUENCE_NUM) {
  965. bt_dev_info(hu->hdev,
  966. "QCA memdump Done, received %d, total %d",
  967. qca_memdump->received_dump,
  968. qca_memdump->ram_dump_size);
  969. hci_devcd_complete(hu->hdev);
  970. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  971. kfree(qca->qca_memdump);
  972. qca->qca_memdump = NULL;
  973. qca->memdump_state = QCA_MEMDUMP_COLLECTED;
  974. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  975. }
  976. mutex_unlock(&qca->hci_memdump_lock);
  977. }
  978. }
  979. static int qca_controller_memdump_event(struct hci_dev *hdev,
  980. struct sk_buff *skb)
  981. {
  982. struct hci_uart *hu = hci_get_drvdata(hdev);
  983. struct qca_data *qca = hu->priv;
  984. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  985. skb_queue_tail(&qca->rx_memdump_q, skb);
  986. queue_work(qca->workqueue, &qca->ctrl_memdump_evt);
  987. return 0;
  988. }
  989. static int qca_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
  990. {
  991. struct hci_uart *hu = hci_get_drvdata(hdev);
  992. struct qca_data *qca = hu->priv;
  993. if (test_bit(QCA_DROP_VENDOR_EVENT, &qca->flags)) {
  994. struct hci_event_hdr *hdr = (void *)skb->data;
  995. /* For the WCN3990 the vendor command for a baudrate change
  996. * isn't sent as synchronous HCI command, because the
  997. * controller sends the corresponding vendor event with the
  998. * new baudrate. The event is received and properly decoded
  999. * after changing the baudrate of the host port. It needs to
  1000. * be dropped, otherwise it can be misinterpreted as
  1001. * response to a later firmware download command (also a
  1002. * vendor command).
  1003. */
  1004. if (hdr->evt == HCI_EV_VENDOR)
  1005. complete(&qca->drop_ev_comp);
  1006. kfree_skb(skb);
  1007. return 0;
  1008. }
  1009. /* We receive chip memory dump as an event packet, With a dedicated
  1010. * handler followed by a hardware error event. When this event is
  1011. * received we store dump into a file before closing hci. This
  1012. * dump will help in triaging the issues.
  1013. */
  1014. if ((skb->data[0] == HCI_VENDOR_PKT) &&
  1015. (get_unaligned_be16(skb->data + 2) == QCA_SSR_DUMP_HANDLE))
  1016. return qca_controller_memdump_event(hdev, skb);
  1017. return hci_recv_frame(hdev, skb);
  1018. }
  1019. #define QCA_IBS_SLEEP_IND_EVENT \
  1020. .type = HCI_IBS_SLEEP_IND, \
  1021. .hlen = 0, \
  1022. .loff = 0, \
  1023. .lsize = 0, \
  1024. .maxlen = HCI_MAX_IBS_SIZE
  1025. #define QCA_IBS_WAKE_IND_EVENT \
  1026. .type = HCI_IBS_WAKE_IND, \
  1027. .hlen = 0, \
  1028. .loff = 0, \
  1029. .lsize = 0, \
  1030. .maxlen = HCI_MAX_IBS_SIZE
  1031. #define QCA_IBS_WAKE_ACK_EVENT \
  1032. .type = HCI_IBS_WAKE_ACK, \
  1033. .hlen = 0, \
  1034. .loff = 0, \
  1035. .lsize = 0, \
  1036. .maxlen = HCI_MAX_IBS_SIZE
  1037. static const struct h4_recv_pkt qca_recv_pkts[] = {
  1038. { H4_RECV_ACL, .recv = qca_recv_acl_data },
  1039. { H4_RECV_SCO, .recv = hci_recv_frame },
  1040. { H4_RECV_EVENT, .recv = qca_recv_event },
  1041. { H4_RECV_ISO, .recv = hci_recv_frame },
  1042. { QCA_IBS_WAKE_IND_EVENT, .recv = qca_ibs_wake_ind },
  1043. { QCA_IBS_WAKE_ACK_EVENT, .recv = qca_ibs_wake_ack },
  1044. { QCA_IBS_SLEEP_IND_EVENT, .recv = qca_ibs_sleep_ind },
  1045. };
  1046. static int qca_recv(struct hci_uart *hu, const void *data, int count)
  1047. {
  1048. struct qca_data *qca = hu->priv;
  1049. if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
  1050. return -EUNATCH;
  1051. qca->rx_skb = h4_recv_buf(hu, qca->rx_skb, data, count,
  1052. qca_recv_pkts, ARRAY_SIZE(qca_recv_pkts));
  1053. if (IS_ERR(qca->rx_skb)) {
  1054. int err = PTR_ERR(qca->rx_skb);
  1055. bt_dev_err(hu->hdev, "Frame reassembly failed (%d)", err);
  1056. qca->rx_skb = NULL;
  1057. return err;
  1058. }
  1059. return count;
  1060. }
  1061. static struct sk_buff *qca_dequeue(struct hci_uart *hu)
  1062. {
  1063. struct qca_data *qca = hu->priv;
  1064. return skb_dequeue(&qca->txq);
  1065. }
  1066. static uint8_t qca_get_baudrate_value(int speed)
  1067. {
  1068. switch (speed) {
  1069. case 9600:
  1070. return QCA_BAUDRATE_9600;
  1071. case 19200:
  1072. return QCA_BAUDRATE_19200;
  1073. case 38400:
  1074. return QCA_BAUDRATE_38400;
  1075. case 57600:
  1076. return QCA_BAUDRATE_57600;
  1077. case 115200:
  1078. return QCA_BAUDRATE_115200;
  1079. case 230400:
  1080. return QCA_BAUDRATE_230400;
  1081. case 460800:
  1082. return QCA_BAUDRATE_460800;
  1083. case 500000:
  1084. return QCA_BAUDRATE_500000;
  1085. case 921600:
  1086. return QCA_BAUDRATE_921600;
  1087. case 1000000:
  1088. return QCA_BAUDRATE_1000000;
  1089. case 2000000:
  1090. return QCA_BAUDRATE_2000000;
  1091. case 3000000:
  1092. return QCA_BAUDRATE_3000000;
  1093. case 3200000:
  1094. return QCA_BAUDRATE_3200000;
  1095. case 3500000:
  1096. return QCA_BAUDRATE_3500000;
  1097. default:
  1098. return QCA_BAUDRATE_115200;
  1099. }
  1100. }
  1101. static int qca_set_baudrate(struct hci_dev *hdev, uint8_t baudrate)
  1102. {
  1103. struct hci_uart *hu = hci_get_drvdata(hdev);
  1104. struct qca_data *qca = hu->priv;
  1105. struct sk_buff *skb;
  1106. u8 cmd[] = { 0x01, 0x48, 0xFC, 0x01, 0x00 };
  1107. if (baudrate > QCA_BAUDRATE_3200000)
  1108. return -EINVAL;
  1109. cmd[4] = baudrate;
  1110. skb = bt_skb_alloc(sizeof(cmd), GFP_KERNEL);
  1111. if (!skb) {
  1112. bt_dev_err(hdev, "Failed to allocate baudrate packet");
  1113. return -ENOMEM;
  1114. }
  1115. /* Assign commands to change baudrate and packet type. */
  1116. skb_put_data(skb, cmd, sizeof(cmd));
  1117. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1118. skb_queue_tail(&qca->txq, skb);
  1119. hci_uart_tx_wakeup(hu);
  1120. /* Wait for the baudrate change request to be sent */
  1121. while (!skb_queue_empty(&qca->txq))
  1122. usleep_range(100, 200);
  1123. if (hu->serdev)
  1124. serdev_device_wait_until_sent(hu->serdev,
  1125. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  1126. /* Give the controller time to process the request */
  1127. switch (qca_soc_type(hu)) {
  1128. case QCA_WCN3950:
  1129. case QCA_WCN3988:
  1130. case QCA_WCN3990:
  1131. case QCA_WCN3991:
  1132. case QCA_WCN3998:
  1133. case QCA_WCN6750:
  1134. case QCA_WCN6855:
  1135. case QCA_WCN7850:
  1136. usleep_range(1000, 10000);
  1137. break;
  1138. default:
  1139. msleep(300);
  1140. }
  1141. return 0;
  1142. }
  1143. static inline void host_set_baudrate(struct hci_uart *hu, unsigned int speed)
  1144. {
  1145. if (hu->serdev)
  1146. serdev_device_set_baudrate(hu->serdev, speed);
  1147. else
  1148. hci_uart_set_baudrate(hu, speed);
  1149. }
  1150. static int qca_send_power_pulse(struct hci_uart *hu, bool on)
  1151. {
  1152. int ret;
  1153. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  1154. u8 cmd = on ? QCA_WCN3990_POWERON_PULSE : QCA_WCN3990_POWEROFF_PULSE;
  1155. /* These power pulses are single byte command which are sent
  1156. * at required baudrate to wcn3990. On wcn3990, we have an external
  1157. * circuit at Tx pin which decodes the pulse sent at specific baudrate.
  1158. * For example, wcn3990 supports RF COEX antenna for both Wi-Fi/BT
  1159. * and also we use the same power inputs to turn on and off for
  1160. * Wi-Fi/BT. Powering up the power sources will not enable BT, until
  1161. * we send a power on pulse at 115200 bps. This algorithm will help to
  1162. * save power. Disabling hardware flow control is mandatory while
  1163. * sending power pulses to SoC.
  1164. */
  1165. bt_dev_dbg(hu->hdev, "sending power pulse %02x to controller", cmd);
  1166. serdev_device_write_flush(hu->serdev);
  1167. hci_uart_set_flow_control(hu, true);
  1168. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  1169. if (ret < 0) {
  1170. bt_dev_err(hu->hdev, "failed to send power pulse %02x", cmd);
  1171. return ret;
  1172. }
  1173. serdev_device_wait_until_sent(hu->serdev, timeout);
  1174. hci_uart_set_flow_control(hu, false);
  1175. /* Give to controller time to boot/shutdown */
  1176. if (on)
  1177. msleep(100);
  1178. else
  1179. usleep_range(1000, 10000);
  1180. return 0;
  1181. }
  1182. static unsigned int qca_get_speed(struct hci_uart *hu,
  1183. enum qca_speed_type speed_type)
  1184. {
  1185. unsigned int speed = 0;
  1186. if (speed_type == QCA_INIT_SPEED) {
  1187. if (hu->init_speed)
  1188. speed = hu->init_speed;
  1189. else if (hu->proto->init_speed)
  1190. speed = hu->proto->init_speed;
  1191. } else {
  1192. if (hu->oper_speed)
  1193. speed = hu->oper_speed;
  1194. else if (hu->proto->oper_speed)
  1195. speed = hu->proto->oper_speed;
  1196. }
  1197. return speed;
  1198. }
  1199. static int qca_check_speeds(struct hci_uart *hu)
  1200. {
  1201. switch (qca_soc_type(hu)) {
  1202. case QCA_WCN3950:
  1203. case QCA_WCN3988:
  1204. case QCA_WCN3990:
  1205. case QCA_WCN3991:
  1206. case QCA_WCN3998:
  1207. case QCA_WCN6750:
  1208. case QCA_WCN6855:
  1209. case QCA_WCN7850:
  1210. if (!qca_get_speed(hu, QCA_INIT_SPEED) &&
  1211. !qca_get_speed(hu, QCA_OPER_SPEED))
  1212. return -EINVAL;
  1213. break;
  1214. default:
  1215. if (!qca_get_speed(hu, QCA_INIT_SPEED) ||
  1216. !qca_get_speed(hu, QCA_OPER_SPEED))
  1217. return -EINVAL;
  1218. }
  1219. return 0;
  1220. }
  1221. static int qca_set_speed(struct hci_uart *hu, enum qca_speed_type speed_type)
  1222. {
  1223. unsigned int speed, qca_baudrate;
  1224. struct qca_data *qca = hu->priv;
  1225. int ret = 0;
  1226. if (speed_type == QCA_INIT_SPEED) {
  1227. speed = qca_get_speed(hu, QCA_INIT_SPEED);
  1228. if (speed)
  1229. host_set_baudrate(hu, speed);
  1230. } else {
  1231. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1232. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1233. if (!speed)
  1234. return 0;
  1235. /* Disable flow control for wcn3990 to deassert RTS while
  1236. * changing the baudrate of chip and host.
  1237. */
  1238. switch (soc_type) {
  1239. case QCA_WCN3950:
  1240. case QCA_WCN3988:
  1241. case QCA_WCN3990:
  1242. case QCA_WCN3991:
  1243. case QCA_WCN3998:
  1244. case QCA_WCN6750:
  1245. case QCA_WCN6855:
  1246. case QCA_WCN7850:
  1247. hci_uart_set_flow_control(hu, true);
  1248. break;
  1249. default:
  1250. break;
  1251. }
  1252. switch (soc_type) {
  1253. case QCA_WCN3990:
  1254. reinit_completion(&qca->drop_ev_comp);
  1255. set_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1256. break;
  1257. default:
  1258. break;
  1259. }
  1260. qca_baudrate = qca_get_baudrate_value(speed);
  1261. bt_dev_dbg(hu->hdev, "Set UART speed to %d", speed);
  1262. ret = qca_set_baudrate(hu->hdev, qca_baudrate);
  1263. if (ret)
  1264. goto error;
  1265. host_set_baudrate(hu, speed);
  1266. error:
  1267. switch (soc_type) {
  1268. case QCA_WCN3950:
  1269. case QCA_WCN3988:
  1270. case QCA_WCN3990:
  1271. case QCA_WCN3991:
  1272. case QCA_WCN3998:
  1273. case QCA_WCN6750:
  1274. case QCA_WCN6855:
  1275. case QCA_WCN7850:
  1276. hci_uart_set_flow_control(hu, false);
  1277. break;
  1278. default:
  1279. break;
  1280. }
  1281. switch (soc_type) {
  1282. case QCA_WCN3990:
  1283. /* Wait for the controller to send the vendor event
  1284. * for the baudrate change command.
  1285. */
  1286. if (!wait_for_completion_timeout(&qca->drop_ev_comp,
  1287. msecs_to_jiffies(100))) {
  1288. bt_dev_err(hu->hdev,
  1289. "Failed to change controller baudrate\n");
  1290. ret = -ETIMEDOUT;
  1291. }
  1292. clear_bit(QCA_DROP_VENDOR_EVENT, &qca->flags);
  1293. break;
  1294. default:
  1295. break;
  1296. }
  1297. }
  1298. return ret;
  1299. }
  1300. static int qca_send_crashbuffer(struct hci_uart *hu)
  1301. {
  1302. struct qca_data *qca = hu->priv;
  1303. struct sk_buff *skb;
  1304. skb = bt_skb_alloc(QCA_CRASHBYTE_PACKET_LEN, GFP_KERNEL);
  1305. if (!skb) {
  1306. bt_dev_err(hu->hdev, "Failed to allocate memory for skb packet");
  1307. return -ENOMEM;
  1308. }
  1309. /* We forcefully crash the controller, by sending 0xfb byte for
  1310. * 1024 times. We also might have chance of losing data, To be
  1311. * on safer side we send 1096 bytes to the SoC.
  1312. */
  1313. memset(skb_put(skb, QCA_CRASHBYTE_PACKET_LEN), QCA_MEMDUMP_BYTE,
  1314. QCA_CRASHBYTE_PACKET_LEN);
  1315. hci_skb_pkt_type(skb) = HCI_COMMAND_PKT;
  1316. bt_dev_info(hu->hdev, "crash the soc to collect controller dump");
  1317. skb_queue_tail(&qca->txq, skb);
  1318. hci_uart_tx_wakeup(hu);
  1319. return 0;
  1320. }
  1321. static void qca_wait_for_dump_collection(struct hci_dev *hdev)
  1322. {
  1323. struct hci_uart *hu = hci_get_drvdata(hdev);
  1324. struct qca_data *qca = hu->priv;
  1325. wait_on_bit_timeout(&qca->flags, QCA_MEMDUMP_COLLECTION,
  1326. TASK_UNINTERRUPTIBLE, MEMDUMP_TIMEOUT_MS);
  1327. clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1328. }
  1329. static void qca_hw_error(struct hci_dev *hdev, u8 code)
  1330. {
  1331. struct hci_uart *hu = hci_get_drvdata(hdev);
  1332. struct qca_data *qca = hu->priv;
  1333. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1334. set_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1335. bt_dev_info(hdev, "mem_dump_status: %d", qca->memdump_state);
  1336. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1337. /* If hardware error event received for other than QCA
  1338. * soc memory dump event, then we need to crash the SOC
  1339. * and wait here for 8 seconds to get the dump packets.
  1340. * This will block main thread to be on hold until we
  1341. * collect dump.
  1342. */
  1343. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1344. qca_send_crashbuffer(hu);
  1345. qca_wait_for_dump_collection(hdev);
  1346. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1347. /* Let us wait here until memory dump collected or
  1348. * memory dump timer expired.
  1349. */
  1350. bt_dev_info(hdev, "waiting for dump to complete");
  1351. qca_wait_for_dump_collection(hdev);
  1352. }
  1353. mutex_lock(&qca->hci_memdump_lock);
  1354. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1355. bt_dev_err(hu->hdev, "clearing allocated memory due to memdump timeout");
  1356. hci_devcd_abort(hu->hdev);
  1357. if (qca->qca_memdump) {
  1358. kfree(qca->qca_memdump);
  1359. qca->qca_memdump = NULL;
  1360. }
  1361. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1362. cancel_delayed_work(&qca->ctrl_memdump_timeout);
  1363. }
  1364. mutex_unlock(&qca->hci_memdump_lock);
  1365. if (qca->memdump_state == QCA_MEMDUMP_TIMEOUT ||
  1366. qca->memdump_state == QCA_MEMDUMP_COLLECTED) {
  1367. cancel_work_sync(&qca->ctrl_memdump_evt);
  1368. skb_queue_purge(&qca->rx_memdump_q);
  1369. }
  1370. /*
  1371. * If the BT chip's bt_en pin is connected to a 3.3V power supply via
  1372. * hardware and always stays high, driver cannot control the bt_en pin.
  1373. * As a result, during SSR (SubSystem Restart), QCA_SSR_TRIGGERED and
  1374. * QCA_IBS_DISABLED flags cannot be cleared, which leads to a reset
  1375. * command timeout.
  1376. * Add an msleep delay to ensure controller completes the SSR process.
  1377. *
  1378. * Host will not download the firmware after SSR, controller to remain
  1379. * in the IBS_WAKE state, and the host needs to synchronize with it
  1380. *
  1381. * Since the bluetooth chip has been reset, clear the memdump state.
  1382. */
  1383. if (!hci_test_quirk(hu->hdev, HCI_QUIRK_NON_PERSISTENT_SETUP)) {
  1384. /*
  1385. * When the SSR (SubSystem Restart) duration exceeds 2 seconds,
  1386. * it triggers host tx_idle_delay, which sets host TX state
  1387. * to sleep. Reset tx_idle_timer after SSR to prevent
  1388. * host enter TX IBS_Sleep mode.
  1389. */
  1390. mod_timer(&qca->tx_idle_timer, jiffies +
  1391. msecs_to_jiffies(qca->tx_idle_delay));
  1392. /* Controller reset completion time is 50ms */
  1393. msleep(50);
  1394. clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1395. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  1396. qca->tx_ibs_state = HCI_IBS_TX_AWAKE;
  1397. qca->memdump_state = QCA_MEMDUMP_IDLE;
  1398. }
  1399. clear_bit(QCA_HW_ERROR_EVENT, &qca->flags);
  1400. }
  1401. static void qca_reset(struct hci_dev *hdev)
  1402. {
  1403. struct hci_uart *hu = hci_get_drvdata(hdev);
  1404. struct qca_data *qca = hu->priv;
  1405. set_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1406. if (qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1407. set_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
  1408. qca_send_crashbuffer(hu);
  1409. qca_wait_for_dump_collection(hdev);
  1410. } else if (qca->memdump_state == QCA_MEMDUMP_COLLECTING) {
  1411. /* Let us wait here until memory dump collected or
  1412. * memory dump timer expired.
  1413. */
  1414. bt_dev_info(hdev, "waiting for dump to complete");
  1415. qca_wait_for_dump_collection(hdev);
  1416. }
  1417. mutex_lock(&qca->hci_memdump_lock);
  1418. if (qca->memdump_state != QCA_MEMDUMP_COLLECTED) {
  1419. qca->memdump_state = QCA_MEMDUMP_TIMEOUT;
  1420. if (!test_bit(QCA_HW_ERROR_EVENT, &qca->flags)) {
  1421. /* Inject hw error event to reset the device
  1422. * and driver.
  1423. */
  1424. hci_reset_dev(hu->hdev);
  1425. }
  1426. }
  1427. mutex_unlock(&qca->hci_memdump_lock);
  1428. }
  1429. static bool qca_wakeup(struct hci_dev *hdev)
  1430. {
  1431. struct hci_uart *hu = hci_get_drvdata(hdev);
  1432. bool wakeup;
  1433. if (!hu->serdev)
  1434. return true;
  1435. /* BT SoC attached through the serial bus is handled by the serdev driver.
  1436. * So we need to use the device handle of the serdev driver to get the
  1437. * status of device may wakeup.
  1438. */
  1439. wakeup = device_may_wakeup(&hu->serdev->ctrl->dev);
  1440. bt_dev_dbg(hu->hdev, "wakeup status : %d", wakeup);
  1441. return wakeup;
  1442. }
  1443. static int qca_port_reopen(struct hci_uart *hu)
  1444. {
  1445. int ret;
  1446. /* Now the device is in ready state to communicate with host.
  1447. * To sync host with device we need to reopen port.
  1448. * Without this, we will have RTS and CTS synchronization
  1449. * issues.
  1450. */
  1451. serdev_device_close(hu->serdev);
  1452. ret = serdev_device_open(hu->serdev);
  1453. if (ret) {
  1454. bt_dev_err(hu->hdev, "failed to open port");
  1455. return ret;
  1456. }
  1457. hci_uart_set_flow_control(hu, false);
  1458. return 0;
  1459. }
  1460. static int qca_regulator_init(struct hci_uart *hu)
  1461. {
  1462. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1463. struct qca_serdev *qcadev;
  1464. int ret;
  1465. bool sw_ctrl_state;
  1466. /* Check for vregs status, may be hci down has turned
  1467. * off the voltage regulator.
  1468. */
  1469. qcadev = serdev_device_get_drvdata(hu->serdev);
  1470. if (!qcadev->bt_power->vregs_on) {
  1471. serdev_device_close(hu->serdev);
  1472. ret = qca_regulator_enable(qcadev);
  1473. if (ret)
  1474. return ret;
  1475. ret = serdev_device_open(hu->serdev);
  1476. if (ret) {
  1477. bt_dev_err(hu->hdev, "failed to open port");
  1478. return ret;
  1479. }
  1480. }
  1481. switch (soc_type) {
  1482. case QCA_WCN3950:
  1483. case QCA_WCN3988:
  1484. case QCA_WCN3990:
  1485. case QCA_WCN3991:
  1486. case QCA_WCN3998:
  1487. /* Forcefully enable wcn399x to enter in to boot mode. */
  1488. host_set_baudrate(hu, 2400);
  1489. ret = qca_send_power_pulse(hu, false);
  1490. if (ret)
  1491. return ret;
  1492. break;
  1493. default:
  1494. break;
  1495. }
  1496. /* For wcn6750 need to enable gpio bt_en */
  1497. if (qcadev->bt_en) {
  1498. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1499. msleep(50);
  1500. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1501. msleep(50);
  1502. if (qcadev->sw_ctrl) {
  1503. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1504. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1505. }
  1506. }
  1507. qca_set_speed(hu, QCA_INIT_SPEED);
  1508. switch (soc_type) {
  1509. case QCA_WCN3950:
  1510. case QCA_WCN3988:
  1511. case QCA_WCN3990:
  1512. case QCA_WCN3991:
  1513. case QCA_WCN3998:
  1514. ret = qca_send_power_pulse(hu, true);
  1515. if (ret)
  1516. return ret;
  1517. break;
  1518. default:
  1519. break;
  1520. }
  1521. return qca_port_reopen(hu);
  1522. }
  1523. static int qca_power_on(struct hci_dev *hdev)
  1524. {
  1525. struct hci_uart *hu = hci_get_drvdata(hdev);
  1526. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1527. struct qca_serdev *qcadev;
  1528. struct qca_data *qca = hu->priv;
  1529. int ret = 0;
  1530. /* Non-serdev device usually is powered by external power
  1531. * and don't need additional action in driver for power on
  1532. */
  1533. if (!hu->serdev)
  1534. return 0;
  1535. switch (soc_type) {
  1536. case QCA_WCN3950:
  1537. case QCA_WCN3988:
  1538. case QCA_WCN3990:
  1539. case QCA_WCN3991:
  1540. case QCA_WCN3998:
  1541. case QCA_WCN6750:
  1542. case QCA_WCN6855:
  1543. case QCA_WCN7850:
  1544. case QCA_QCA6390:
  1545. ret = qca_regulator_init(hu);
  1546. break;
  1547. default:
  1548. qcadev = serdev_device_get_drvdata(hu->serdev);
  1549. if (qcadev->bt_en) {
  1550. gpiod_set_value_cansleep(qcadev->bt_en, 1);
  1551. /* Controller needs time to bootup. */
  1552. msleep(150);
  1553. }
  1554. }
  1555. clear_bit(QCA_BT_OFF, &qca->flags);
  1556. return ret;
  1557. }
  1558. static void hci_coredump_qca(struct hci_dev *hdev)
  1559. {
  1560. int err;
  1561. static const u8 param[] = { 0x26 };
  1562. err = __hci_cmd_send(hdev, 0xfc0c, 1, param);
  1563. if (err < 0)
  1564. bt_dev_err(hdev, "%s: trigger crash failed (%d)", __func__, err);
  1565. }
  1566. static int qca_get_data_path_id(struct hci_dev *hdev, __u8 *data_path_id)
  1567. {
  1568. /* QCA uses 1 as non-HCI data path id for HFP */
  1569. *data_path_id = 1;
  1570. return 0;
  1571. }
  1572. static int qca_configure_hfp_offload(struct hci_dev *hdev)
  1573. {
  1574. bt_dev_info(hdev, "HFP non-HCI data transport is supported");
  1575. hdev->get_data_path_id = qca_get_data_path_id;
  1576. /* Do not need to send HCI_Configure_Data_Path to configure non-HCI
  1577. * data transport path for QCA controllers, so set below field as NULL.
  1578. */
  1579. hdev->get_codec_config_data = NULL;
  1580. return 0;
  1581. }
  1582. static int qca_setup(struct hci_uart *hu)
  1583. {
  1584. struct hci_dev *hdev = hu->hdev;
  1585. struct qca_data *qca = hu->priv;
  1586. unsigned int speed, qca_baudrate = QCA_BAUDRATE_115200;
  1587. unsigned int retries = 0;
  1588. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1589. const char *firmware_name = qca_get_firmware_name(hu);
  1590. const char *rampatch_name = qca_get_rampatch_name(hu);
  1591. int ret;
  1592. struct qca_btsoc_version ver;
  1593. struct qca_serdev *qcadev = serdev_device_get_drvdata(hu->serdev);
  1594. const char *soc_name;
  1595. ret = qca_check_speeds(hu);
  1596. if (ret)
  1597. return ret;
  1598. clear_bit(QCA_ROM_FW, &qca->flags);
  1599. /* Patch downloading has to be done without IBS mode */
  1600. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1601. /* Enable controller to do both LE scan and BR/EDR inquiry
  1602. * simultaneously.
  1603. */
  1604. hci_set_quirk(hdev, HCI_QUIRK_SIMULTANEOUS_DISCOVERY);
  1605. switch (soc_type) {
  1606. case QCA_QCA2066:
  1607. soc_name = "qca2066";
  1608. break;
  1609. case QCA_WCN3950:
  1610. case QCA_WCN3988:
  1611. case QCA_WCN3990:
  1612. case QCA_WCN3991:
  1613. case QCA_WCN3998:
  1614. soc_name = "wcn399x";
  1615. break;
  1616. case QCA_WCN6750:
  1617. soc_name = "wcn6750";
  1618. break;
  1619. case QCA_WCN6855:
  1620. soc_name = "wcn6855";
  1621. break;
  1622. case QCA_WCN7850:
  1623. soc_name = "wcn7850";
  1624. break;
  1625. default:
  1626. soc_name = "ROME/QCA6390";
  1627. }
  1628. bt_dev_info(hdev, "setting up %s", soc_name);
  1629. qca->memdump_state = QCA_MEMDUMP_IDLE;
  1630. retry:
  1631. ret = qca_power_on(hdev);
  1632. if (ret)
  1633. goto out;
  1634. clear_bit(QCA_SSR_TRIGGERED, &qca->flags);
  1635. switch (soc_type) {
  1636. case QCA_WCN3950:
  1637. case QCA_WCN3988:
  1638. case QCA_WCN3990:
  1639. case QCA_WCN3991:
  1640. case QCA_WCN3998:
  1641. case QCA_WCN6750:
  1642. case QCA_WCN6855:
  1643. case QCA_WCN7850:
  1644. if (qcadev->bdaddr_property_broken)
  1645. hci_set_quirk(hdev, HCI_QUIRK_BDADDR_PROPERTY_BROKEN);
  1646. hci_set_aosp_capable(hdev);
  1647. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1648. if (ret)
  1649. goto out;
  1650. break;
  1651. default:
  1652. qca_set_speed(hu, QCA_INIT_SPEED);
  1653. }
  1654. /* Setup user speed if needed */
  1655. speed = qca_get_speed(hu, QCA_OPER_SPEED);
  1656. if (speed) {
  1657. ret = qca_set_speed(hu, QCA_OPER_SPEED);
  1658. if (ret)
  1659. goto out;
  1660. qca_baudrate = qca_get_baudrate_value(speed);
  1661. }
  1662. switch (soc_type) {
  1663. case QCA_WCN3950:
  1664. case QCA_WCN3988:
  1665. case QCA_WCN3990:
  1666. case QCA_WCN3991:
  1667. case QCA_WCN3998:
  1668. case QCA_WCN6750:
  1669. case QCA_WCN6855:
  1670. case QCA_WCN7850:
  1671. break;
  1672. default:
  1673. /* Get QCA version information */
  1674. ret = qca_read_soc_version(hdev, &ver, soc_type);
  1675. if (ret)
  1676. goto out;
  1677. }
  1678. /* Setup patch / NVM configurations */
  1679. ret = qca_uart_setup(hdev, qca_baudrate, soc_type, ver,
  1680. firmware_name, rampatch_name);
  1681. if (!ret) {
  1682. clear_bit(QCA_IBS_DISABLED, &qca->flags);
  1683. qca_debugfs_init(hdev);
  1684. hu->hdev->hw_error = qca_hw_error;
  1685. hu->hdev->reset = qca_reset;
  1686. if (hu->serdev) {
  1687. if (device_can_wakeup(hu->serdev->ctrl->dev.parent))
  1688. hu->hdev->wakeup = qca_wakeup;
  1689. }
  1690. } else if (ret == -ENOENT) {
  1691. /* No patch/nvm-config found, run with original fw/config */
  1692. set_bit(QCA_ROM_FW, &qca->flags);
  1693. ret = 0;
  1694. } else if (ret == -EAGAIN) {
  1695. /*
  1696. * Userspace firmware loader will return -EAGAIN in case no
  1697. * patch/nvm-config is found, so run with original fw/config.
  1698. */
  1699. set_bit(QCA_ROM_FW, &qca->flags);
  1700. ret = 0;
  1701. }
  1702. out:
  1703. if (ret) {
  1704. qca_power_shutdown(hu);
  1705. if (retries < MAX_INIT_RETRIES) {
  1706. bt_dev_warn(hdev, "Retry BT power ON:%d", retries);
  1707. if (hu->serdev) {
  1708. serdev_device_close(hu->serdev);
  1709. ret = serdev_device_open(hu->serdev);
  1710. if (ret) {
  1711. bt_dev_err(hdev, "failed to open port");
  1712. return ret;
  1713. }
  1714. }
  1715. retries++;
  1716. goto retry;
  1717. }
  1718. return ret;
  1719. }
  1720. /* Setup bdaddr */
  1721. if (soc_type == QCA_ROME)
  1722. hu->hdev->set_bdaddr = qca_set_bdaddr_rome;
  1723. else
  1724. hu->hdev->set_bdaddr = qca_set_bdaddr;
  1725. if (qcadev->support_hfp_hw_offload)
  1726. qca_configure_hfp_offload(hdev);
  1727. qca->fw_version = le16_to_cpu(ver.patch_ver);
  1728. qca->controller_id = le16_to_cpu(ver.rom_ver);
  1729. hci_devcd_register(hdev, hci_coredump_qca, qca_dmp_hdr, NULL);
  1730. return ret;
  1731. }
  1732. static const struct hci_uart_proto qca_proto = {
  1733. .id = HCI_UART_QCA,
  1734. .name = "QCA",
  1735. .manufacturer = 29,
  1736. .init_speed = 115200,
  1737. .oper_speed = 3000000,
  1738. .open = qca_open,
  1739. .close = qca_close,
  1740. .flush = qca_flush,
  1741. .setup = qca_setup,
  1742. .recv = qca_recv,
  1743. .enqueue = qca_enqueue,
  1744. .dequeue = qca_dequeue,
  1745. };
  1746. static const struct qca_device_data qca_soc_data_wcn3950 __maybe_unused = {
  1747. .soc_type = QCA_WCN3950,
  1748. .vregs = (struct qca_vreg []) {
  1749. { "vddio", 15000 },
  1750. { "vddxo", 60000 },
  1751. { "vddrf", 155000 },
  1752. { "vddch0", 585000 },
  1753. },
  1754. .num_vregs = 4,
  1755. };
  1756. static const struct qca_device_data qca_soc_data_wcn3988 __maybe_unused = {
  1757. .soc_type = QCA_WCN3988,
  1758. .vregs = (struct qca_vreg []) {
  1759. { "vddio", 15000 },
  1760. { "vddxo", 80000 },
  1761. { "vddrf", 300000 },
  1762. { "vddch0", 450000 },
  1763. },
  1764. .num_vregs = 4,
  1765. };
  1766. static const struct qca_device_data qca_soc_data_wcn3990 __maybe_unused = {
  1767. .soc_type = QCA_WCN3990,
  1768. .vregs = (struct qca_vreg []) {
  1769. { "vddio", 15000 },
  1770. { "vddxo", 80000 },
  1771. { "vddrf", 300000 },
  1772. { "vddch0", 450000 },
  1773. },
  1774. .num_vregs = 4,
  1775. };
  1776. static const struct qca_device_data qca_soc_data_wcn3991 __maybe_unused = {
  1777. .soc_type = QCA_WCN3991,
  1778. .vregs = (struct qca_vreg []) {
  1779. { "vddio", 15000 },
  1780. { "vddxo", 80000 },
  1781. { "vddrf", 300000 },
  1782. { "vddch0", 450000 },
  1783. },
  1784. .num_vregs = 4,
  1785. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1786. };
  1787. static const struct qca_device_data qca_soc_data_wcn3998 __maybe_unused = {
  1788. .soc_type = QCA_WCN3998,
  1789. .vregs = (struct qca_vreg []) {
  1790. { "vddio", 10000 },
  1791. { "vddxo", 80000 },
  1792. { "vddrf", 300000 },
  1793. { "vddch0", 450000 },
  1794. },
  1795. .num_vregs = 4,
  1796. };
  1797. static const struct qca_device_data qca_soc_data_qca2066 __maybe_unused = {
  1798. .soc_type = QCA_QCA2066,
  1799. .num_vregs = 0,
  1800. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES |
  1801. QCA_CAP_HFP_HW_OFFLOAD,
  1802. };
  1803. static const struct qca_device_data qca_soc_data_qca6390 __maybe_unused = {
  1804. .soc_type = QCA_QCA6390,
  1805. .num_vregs = 0,
  1806. };
  1807. static const struct qca_device_data qca_soc_data_wcn6750 __maybe_unused = {
  1808. .soc_type = QCA_WCN6750,
  1809. .vregs = (struct qca_vreg []) {
  1810. { "vddio", 5000 },
  1811. { "vddaon", 26000 },
  1812. { "vddbtcxmx", 126000 },
  1813. { "vddrfacmn", 12500 },
  1814. { "vddrfa0p8", 102000 },
  1815. { "vddrfa1p7", 302000 },
  1816. { "vddrfa1p2", 257000 },
  1817. { "vddrfa2p2", 1700000 },
  1818. { "vddasd", 200 },
  1819. },
  1820. .num_vregs = 9,
  1821. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES,
  1822. };
  1823. static const struct qca_device_data qca_soc_data_wcn6855 __maybe_unused = {
  1824. .soc_type = QCA_WCN6855,
  1825. .vregs = (struct qca_vreg []) {
  1826. { "vddio", 5000 },
  1827. { "vddbtcxmx", 126000 },
  1828. { "vddrfacmn", 12500 },
  1829. { "vddrfa0p8", 102000 },
  1830. { "vddrfa1p7", 302000 },
  1831. { "vddrfa1p2", 257000 },
  1832. },
  1833. .num_vregs = 6,
  1834. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES |
  1835. QCA_CAP_HFP_HW_OFFLOAD,
  1836. };
  1837. static const struct qca_device_data qca_soc_data_wcn7850 __maybe_unused = {
  1838. .soc_type = QCA_WCN7850,
  1839. .vregs = (struct qca_vreg []) {
  1840. { "vddio", 5000 },
  1841. { "vddaon", 26000 },
  1842. { "vdddig", 126000 },
  1843. { "vddrfa0p8", 102000 },
  1844. { "vddrfa1p2", 257000 },
  1845. { "vddrfa1p9", 302000 },
  1846. },
  1847. .num_vregs = 6,
  1848. .capabilities = QCA_CAP_WIDEBAND_SPEECH | QCA_CAP_VALID_LE_STATES |
  1849. QCA_CAP_HFP_HW_OFFLOAD,
  1850. };
  1851. static void qca_power_shutdown(struct hci_uart *hu)
  1852. {
  1853. struct qca_serdev *qcadev;
  1854. struct qca_data *qca = hu->priv;
  1855. unsigned long flags;
  1856. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1857. bool sw_ctrl_state;
  1858. struct qca_power *power;
  1859. /* From this point we go into power off state. But serial port is
  1860. * still open, stop queueing the IBS data and flush all the buffered
  1861. * data in skb's.
  1862. */
  1863. spin_lock_irqsave(&qca->hci_ibs_lock, flags);
  1864. set_bit(QCA_IBS_DISABLED, &qca->flags);
  1865. qca_flush(hu);
  1866. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  1867. /* Non-serdev device usually is powered by external power
  1868. * and don't need additional action in driver for power down
  1869. */
  1870. if (!hu->serdev)
  1871. return;
  1872. qcadev = serdev_device_get_drvdata(hu->serdev);
  1873. power = qcadev->bt_power;
  1874. if (power && power->pwrseq) {
  1875. pwrseq_power_off(power->pwrseq);
  1876. set_bit(QCA_BT_OFF, &qca->flags);
  1877. return;
  1878. }
  1879. switch (soc_type) {
  1880. case QCA_WCN3988:
  1881. case QCA_WCN3990:
  1882. case QCA_WCN3991:
  1883. case QCA_WCN3998:
  1884. host_set_baudrate(hu, 2400);
  1885. qca_send_power_pulse(hu, false);
  1886. qca_regulator_disable(qcadev);
  1887. break;
  1888. case QCA_WCN6750:
  1889. case QCA_WCN6855:
  1890. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1891. msleep(100);
  1892. qca_regulator_disable(qcadev);
  1893. if (qcadev->sw_ctrl) {
  1894. sw_ctrl_state = gpiod_get_value_cansleep(qcadev->sw_ctrl);
  1895. bt_dev_dbg(hu->hdev, "SW_CTRL is %d", sw_ctrl_state);
  1896. }
  1897. break;
  1898. default:
  1899. gpiod_set_value_cansleep(qcadev->bt_en, 0);
  1900. }
  1901. set_bit(QCA_BT_OFF, &qca->flags);
  1902. }
  1903. static int qca_power_off(struct hci_dev *hdev)
  1904. {
  1905. struct hci_uart *hu = hci_get_drvdata(hdev);
  1906. struct qca_data *qca = hu->priv;
  1907. enum qca_btsoc_type soc_type = qca_soc_type(hu);
  1908. hu->hdev->hw_error = NULL;
  1909. hu->hdev->reset = NULL;
  1910. timer_delete_sync(&qca->wake_retrans_timer);
  1911. timer_delete_sync(&qca->tx_idle_timer);
  1912. /* Stop sending shutdown command if soc crashes. */
  1913. if (soc_type != QCA_ROME
  1914. && qca->memdump_state == QCA_MEMDUMP_IDLE) {
  1915. qca_send_pre_shutdown_cmd(hdev);
  1916. usleep_range(8000, 10000);
  1917. }
  1918. qca_power_shutdown(hu);
  1919. return 0;
  1920. }
  1921. static int qca_regulator_enable(struct qca_serdev *qcadev)
  1922. {
  1923. struct qca_power *power = qcadev->bt_power;
  1924. int ret;
  1925. if (power->pwrseq)
  1926. return pwrseq_power_on(power->pwrseq);
  1927. /* Already enabled */
  1928. if (power->vregs_on)
  1929. return 0;
  1930. BT_DBG("enabling %d regulators)", power->num_vregs);
  1931. ret = regulator_bulk_enable(power->num_vregs, power->vreg_bulk);
  1932. if (ret)
  1933. return ret;
  1934. power->vregs_on = true;
  1935. ret = clk_prepare_enable(qcadev->susclk);
  1936. if (ret)
  1937. qca_regulator_disable(qcadev);
  1938. return ret;
  1939. }
  1940. static void qca_regulator_disable(struct qca_serdev *qcadev)
  1941. {
  1942. struct qca_power *power;
  1943. if (!qcadev)
  1944. return;
  1945. power = qcadev->bt_power;
  1946. /* Already disabled? */
  1947. if (!power->vregs_on)
  1948. return;
  1949. regulator_bulk_disable(power->num_vregs, power->vreg_bulk);
  1950. power->vregs_on = false;
  1951. clk_disable_unprepare(qcadev->susclk);
  1952. }
  1953. static int qca_init_regulators(struct qca_power *qca,
  1954. const struct qca_vreg *vregs, size_t num_vregs)
  1955. {
  1956. struct regulator_bulk_data *bulk;
  1957. int ret;
  1958. int i;
  1959. bulk = devm_kcalloc(qca->dev, num_vregs, sizeof(*bulk), GFP_KERNEL);
  1960. if (!bulk)
  1961. return -ENOMEM;
  1962. for (i = 0; i < num_vregs; i++)
  1963. bulk[i].supply = vregs[i].name;
  1964. ret = devm_regulator_bulk_get(qca->dev, num_vregs, bulk);
  1965. if (ret < 0)
  1966. return ret;
  1967. for (i = 0; i < num_vregs; i++) {
  1968. ret = regulator_set_load(bulk[i].consumer, vregs[i].load_uA);
  1969. if (ret)
  1970. return ret;
  1971. }
  1972. qca->vreg_bulk = bulk;
  1973. qca->num_vregs = num_vregs;
  1974. return 0;
  1975. }
  1976. static int qca_serdev_probe(struct serdev_device *serdev)
  1977. {
  1978. struct qca_serdev *qcadev;
  1979. struct hci_dev *hdev;
  1980. const struct qca_device_data *data;
  1981. int err;
  1982. bool power_ctrl_enabled = true;
  1983. qcadev = devm_kzalloc(&serdev->dev, sizeof(*qcadev), GFP_KERNEL);
  1984. if (!qcadev)
  1985. return -ENOMEM;
  1986. qcadev->serdev_hu.serdev = serdev;
  1987. data = device_get_match_data(&serdev->dev);
  1988. serdev_device_set_drvdata(serdev, qcadev);
  1989. device_property_read_string_array(&serdev->dev, "firmware-name",
  1990. qcadev->firmware_name, ARRAY_SIZE(qcadev->firmware_name));
  1991. device_property_read_u32(&serdev->dev, "max-speed",
  1992. &qcadev->oper_speed);
  1993. if (!qcadev->oper_speed)
  1994. BT_DBG("UART will pick default operating speed");
  1995. qcadev->bdaddr_property_broken = device_property_read_bool(&serdev->dev,
  1996. "qcom,local-bd-address-broken");
  1997. if (data)
  1998. qcadev->btsoc_type = data->soc_type;
  1999. else
  2000. qcadev->btsoc_type = QCA_ROME;
  2001. switch (qcadev->btsoc_type) {
  2002. case QCA_WCN3950:
  2003. case QCA_WCN3988:
  2004. case QCA_WCN3990:
  2005. case QCA_WCN3991:
  2006. case QCA_WCN3998:
  2007. case QCA_WCN6750:
  2008. case QCA_WCN6855:
  2009. case QCA_WCN7850:
  2010. case QCA_QCA6390:
  2011. qcadev->bt_power = devm_kzalloc(&serdev->dev,
  2012. sizeof(struct qca_power),
  2013. GFP_KERNEL);
  2014. if (!qcadev->bt_power)
  2015. return -ENOMEM;
  2016. break;
  2017. default:
  2018. break;
  2019. }
  2020. switch (qcadev->btsoc_type) {
  2021. case QCA_WCN6855:
  2022. case QCA_WCN7850:
  2023. case QCA_WCN6750:
  2024. if (!device_property_present(&serdev->dev, "enable-gpios")) {
  2025. /*
  2026. * Backward compatibility with old DT sources. If the
  2027. * node doesn't have the 'enable-gpios' property then
  2028. * let's use the power sequencer. Otherwise, let's
  2029. * drive everything ourselves.
  2030. */
  2031. qcadev->bt_power->pwrseq = devm_pwrseq_get(&serdev->dev,
  2032. "bluetooth");
  2033. /*
  2034. * Some modules have BT_EN enabled via a hardware pull-up,
  2035. * meaning it is not defined in the DTS and is not controlled
  2036. * through the power sequence. In such cases, fall through
  2037. * to follow the legacy flow.
  2038. */
  2039. if (IS_ERR(qcadev->bt_power->pwrseq))
  2040. qcadev->bt_power->pwrseq = NULL;
  2041. else
  2042. break;
  2043. }
  2044. fallthrough;
  2045. case QCA_WCN3950:
  2046. case QCA_WCN3988:
  2047. case QCA_WCN3990:
  2048. case QCA_WCN3991:
  2049. case QCA_WCN3998:
  2050. qcadev->bt_power->dev = &serdev->dev;
  2051. err = qca_init_regulators(qcadev->bt_power, data->vregs,
  2052. data->num_vregs);
  2053. if (err) {
  2054. BT_ERR("Failed to init regulators:%d", err);
  2055. return err;
  2056. }
  2057. qcadev->bt_power->vregs_on = false;
  2058. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  2059. GPIOD_OUT_LOW);
  2060. if (IS_ERR(qcadev->bt_en))
  2061. return dev_err_probe(&serdev->dev,
  2062. PTR_ERR(qcadev->bt_en),
  2063. "failed to acquire BT_EN gpio\n");
  2064. if (!qcadev->bt_en &&
  2065. (data->soc_type == QCA_WCN6750 ||
  2066. data->soc_type == QCA_WCN6855))
  2067. power_ctrl_enabled = false;
  2068. qcadev->sw_ctrl = devm_gpiod_get_optional(&serdev->dev, "swctrl",
  2069. GPIOD_IN);
  2070. if (IS_ERR(qcadev->sw_ctrl) &&
  2071. (data->soc_type == QCA_WCN6750 ||
  2072. data->soc_type == QCA_WCN6855 ||
  2073. data->soc_type == QCA_WCN7850)) {
  2074. dev_err(&serdev->dev, "failed to acquire SW_CTRL gpio\n");
  2075. return PTR_ERR(qcadev->sw_ctrl);
  2076. }
  2077. qcadev->susclk = devm_clk_get_optional(&serdev->dev, NULL);
  2078. if (IS_ERR(qcadev->susclk)) {
  2079. dev_err(&serdev->dev, "failed to acquire clk\n");
  2080. return PTR_ERR(qcadev->susclk);
  2081. }
  2082. break;
  2083. case QCA_QCA6390:
  2084. if (dev_of_node(&serdev->dev)) {
  2085. qcadev->bt_power->pwrseq = devm_pwrseq_get(&serdev->dev,
  2086. "bluetooth");
  2087. if (IS_ERR(qcadev->bt_power->pwrseq))
  2088. return PTR_ERR(qcadev->bt_power->pwrseq);
  2089. break;
  2090. }
  2091. fallthrough;
  2092. default:
  2093. qcadev->bt_en = devm_gpiod_get_optional(&serdev->dev, "enable",
  2094. GPIOD_OUT_LOW);
  2095. if (IS_ERR(qcadev->bt_en)) {
  2096. dev_err(&serdev->dev, "failed to acquire enable gpio\n");
  2097. return PTR_ERR(qcadev->bt_en);
  2098. }
  2099. if (!qcadev->bt_en)
  2100. power_ctrl_enabled = false;
  2101. qcadev->susclk = devm_clk_get_optional_enabled_with_rate(
  2102. &serdev->dev, NULL, SUSCLK_RATE_32KHZ);
  2103. if (IS_ERR(qcadev->susclk)) {
  2104. dev_warn(&serdev->dev, "failed to acquire clk\n");
  2105. return PTR_ERR(qcadev->susclk);
  2106. }
  2107. }
  2108. err = hci_uart_register_device(&qcadev->serdev_hu, &qca_proto);
  2109. if (err) {
  2110. BT_ERR("serdev registration failed");
  2111. return err;
  2112. }
  2113. hdev = qcadev->serdev_hu.hdev;
  2114. if (power_ctrl_enabled) {
  2115. hci_set_quirk(hdev, HCI_QUIRK_NON_PERSISTENT_SETUP);
  2116. hdev->shutdown = qca_power_off;
  2117. }
  2118. if (data) {
  2119. /* Wideband speech support must be set per driver since it can't
  2120. * be queried via hci. Same with the valid le states quirk.
  2121. */
  2122. if (data->capabilities & QCA_CAP_WIDEBAND_SPEECH)
  2123. hci_set_quirk(hdev,
  2124. HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED);
  2125. if (!(data->capabilities & QCA_CAP_VALID_LE_STATES))
  2126. hci_set_quirk(hdev, HCI_QUIRK_BROKEN_LE_STATES);
  2127. if (data->capabilities & QCA_CAP_HFP_HW_OFFLOAD)
  2128. qcadev->support_hfp_hw_offload = true;
  2129. }
  2130. return 0;
  2131. }
  2132. static void qca_serdev_remove(struct serdev_device *serdev)
  2133. {
  2134. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2135. struct qca_power *power = qcadev->bt_power;
  2136. switch (qcadev->btsoc_type) {
  2137. case QCA_WCN3988:
  2138. case QCA_WCN3990:
  2139. case QCA_WCN3991:
  2140. case QCA_WCN3998:
  2141. case QCA_WCN6750:
  2142. case QCA_WCN6855:
  2143. case QCA_WCN7850:
  2144. if (power->vregs_on)
  2145. qca_power_shutdown(&qcadev->serdev_hu);
  2146. break;
  2147. default:
  2148. break;
  2149. }
  2150. hci_uart_unregister_device(&qcadev->serdev_hu);
  2151. }
  2152. static void qca_serdev_shutdown(struct serdev_device *serdev)
  2153. {
  2154. int ret;
  2155. int timeout = msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS);
  2156. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2157. struct hci_uart *hu = &qcadev->serdev_hu;
  2158. struct hci_dev *hdev = hu->hdev;
  2159. const u8 ibs_wake_cmd[] = { 0xFD };
  2160. const u8 edl_reset_soc_cmd[] = { 0x01, 0x00, 0xFC, 0x01, 0x05 };
  2161. if (qcadev->btsoc_type == QCA_QCA6390) {
  2162. /* The purpose of sending the VSC is to reset SOC into a initial
  2163. * state and the state will ensure next hdev->setup() success.
  2164. * if HCI_QUIRK_NON_PERSISTENT_SETUP is set, it means that
  2165. * hdev->setup() can do its job regardless of SoC state, so
  2166. * don't need to send the VSC.
  2167. * if HCI_SETUP is set, it means that hdev->setup() was never
  2168. * invoked and the SOC is already in the initial state, so
  2169. * don't also need to send the VSC.
  2170. */
  2171. if (hci_test_quirk(hdev, HCI_QUIRK_NON_PERSISTENT_SETUP) ||
  2172. hci_dev_test_flag(hdev, HCI_SETUP))
  2173. return;
  2174. /* The serdev must be in open state when control logic arrives
  2175. * here, so also fix the use-after-free issue caused by that
  2176. * the serdev is flushed or wrote after it is closed.
  2177. */
  2178. serdev_device_write_flush(serdev);
  2179. ret = serdev_device_write_buf(serdev, ibs_wake_cmd,
  2180. sizeof(ibs_wake_cmd));
  2181. if (ret < 0) {
  2182. BT_ERR("QCA send IBS_WAKE_IND error: %d", ret);
  2183. return;
  2184. }
  2185. serdev_device_wait_until_sent(serdev, timeout);
  2186. usleep_range(8000, 10000);
  2187. serdev_device_write_flush(serdev);
  2188. ret = serdev_device_write_buf(serdev, edl_reset_soc_cmd,
  2189. sizeof(edl_reset_soc_cmd));
  2190. if (ret < 0) {
  2191. BT_ERR("QCA send EDL_RESET_REQ error: %d", ret);
  2192. return;
  2193. }
  2194. serdev_device_wait_until_sent(serdev, timeout);
  2195. usleep_range(8000, 10000);
  2196. }
  2197. }
  2198. static int __maybe_unused qca_suspend(struct device *dev)
  2199. {
  2200. struct serdev_device *serdev = to_serdev_device(dev);
  2201. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2202. struct hci_uart *hu = &qcadev->serdev_hu;
  2203. struct qca_data *qca = hu->priv;
  2204. unsigned long flags;
  2205. bool tx_pending = false;
  2206. int ret = 0;
  2207. u8 cmd;
  2208. u32 wait_timeout = 0;
  2209. set_bit(QCA_SUSPENDING, &qca->flags);
  2210. /* if BT SoC is running with default firmware then it does not
  2211. * support in-band sleep
  2212. */
  2213. if (test_bit(QCA_ROM_FW, &qca->flags))
  2214. return 0;
  2215. /* During SSR after memory dump collection, controller will be
  2216. * powered off and then powered on.If controller is powered off
  2217. * during SSR then we should wait until SSR is completed.
  2218. */
  2219. if (test_bit(QCA_BT_OFF, &qca->flags) &&
  2220. !test_bit(QCA_SSR_TRIGGERED, &qca->flags))
  2221. return 0;
  2222. if (test_bit(QCA_IBS_DISABLED, &qca->flags) ||
  2223. test_bit(QCA_SSR_TRIGGERED, &qca->flags)) {
  2224. wait_timeout = test_bit(QCA_SSR_TRIGGERED, &qca->flags) ?
  2225. IBS_DISABLE_SSR_TIMEOUT_MS :
  2226. FW_DOWNLOAD_TIMEOUT_MS;
  2227. /* QCA_IBS_DISABLED flag is set to true, During FW download
  2228. * and during memory dump collection. It is reset to false,
  2229. * After FW download complete.
  2230. */
  2231. wait_on_bit_timeout(&qca->flags, QCA_IBS_DISABLED,
  2232. TASK_UNINTERRUPTIBLE, msecs_to_jiffies(wait_timeout));
  2233. if (test_bit(QCA_IBS_DISABLED, &qca->flags)) {
  2234. bt_dev_err(hu->hdev, "SSR or FW download time out");
  2235. ret = -ETIMEDOUT;
  2236. goto error;
  2237. }
  2238. }
  2239. cancel_work_sync(&qca->ws_awake_device);
  2240. cancel_work_sync(&qca->ws_awake_rx);
  2241. spin_lock_irqsave_nested(&qca->hci_ibs_lock,
  2242. flags, SINGLE_DEPTH_NESTING);
  2243. switch (qca->tx_ibs_state) {
  2244. case HCI_IBS_TX_WAKING:
  2245. timer_delete(&qca->wake_retrans_timer);
  2246. fallthrough;
  2247. case HCI_IBS_TX_AWAKE:
  2248. timer_delete(&qca->tx_idle_timer);
  2249. serdev_device_write_flush(hu->serdev);
  2250. cmd = HCI_IBS_SLEEP_IND;
  2251. ret = serdev_device_write_buf(hu->serdev, &cmd, sizeof(cmd));
  2252. if (ret < 0) {
  2253. BT_ERR("Failed to send SLEEP to device");
  2254. break;
  2255. }
  2256. qca->tx_ibs_state = HCI_IBS_TX_ASLEEP;
  2257. qca->ibs_sent_slps++;
  2258. tx_pending = true;
  2259. break;
  2260. case HCI_IBS_TX_ASLEEP:
  2261. break;
  2262. default:
  2263. BT_ERR("Spurious tx state %d", qca->tx_ibs_state);
  2264. ret = -EINVAL;
  2265. break;
  2266. }
  2267. spin_unlock_irqrestore(&qca->hci_ibs_lock, flags);
  2268. if (ret < 0)
  2269. goto error;
  2270. if (tx_pending) {
  2271. serdev_device_wait_until_sent(hu->serdev,
  2272. msecs_to_jiffies(CMD_TRANS_TIMEOUT_MS));
  2273. serial_clock_vote(HCI_IBS_TX_VOTE_CLOCK_OFF, hu);
  2274. }
  2275. /* Wait for HCI_IBS_SLEEP_IND sent by device to indicate its Tx is going
  2276. * to sleep, so that the packet does not wake the system later.
  2277. */
  2278. ret = wait_event_interruptible_timeout(qca->suspend_wait_q,
  2279. qca->rx_ibs_state == HCI_IBS_RX_ASLEEP,
  2280. msecs_to_jiffies(IBS_BTSOC_TX_IDLE_TIMEOUT_MS));
  2281. if (ret == 0) {
  2282. ret = -ETIMEDOUT;
  2283. goto error;
  2284. }
  2285. return 0;
  2286. error:
  2287. clear_bit(QCA_SUSPENDING, &qca->flags);
  2288. return ret;
  2289. }
  2290. static int __maybe_unused qca_resume(struct device *dev)
  2291. {
  2292. struct serdev_device *serdev = to_serdev_device(dev);
  2293. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2294. struct hci_uart *hu = &qcadev->serdev_hu;
  2295. struct qca_data *qca = hu->priv;
  2296. clear_bit(QCA_SUSPENDING, &qca->flags);
  2297. return 0;
  2298. }
  2299. static SIMPLE_DEV_PM_OPS(qca_pm_ops, qca_suspend, qca_resume);
  2300. #ifdef CONFIG_OF
  2301. static const struct of_device_id qca_bluetooth_of_match[] = {
  2302. { .compatible = "qcom,qca2066-bt", .data = &qca_soc_data_qca2066},
  2303. { .compatible = "qcom,qca6174-bt" },
  2304. { .compatible = "qcom,qca6390-bt", .data = &qca_soc_data_qca6390},
  2305. { .compatible = "qcom,qca9377-bt" },
  2306. { .compatible = "qcom,wcn3950-bt", .data = &qca_soc_data_wcn3950},
  2307. { .compatible = "qcom,wcn3988-bt", .data = &qca_soc_data_wcn3988},
  2308. { .compatible = "qcom,wcn3990-bt", .data = &qca_soc_data_wcn3990},
  2309. { .compatible = "qcom,wcn3991-bt", .data = &qca_soc_data_wcn3991},
  2310. { .compatible = "qcom,wcn3998-bt", .data = &qca_soc_data_wcn3998},
  2311. { .compatible = "qcom,wcn6750-bt", .data = &qca_soc_data_wcn6750},
  2312. { .compatible = "qcom,wcn6855-bt", .data = &qca_soc_data_wcn6855},
  2313. { .compatible = "qcom,wcn7850-bt", .data = &qca_soc_data_wcn7850},
  2314. { /* sentinel */ }
  2315. };
  2316. MODULE_DEVICE_TABLE(of, qca_bluetooth_of_match);
  2317. #endif
  2318. #ifdef CONFIG_ACPI
  2319. static const struct acpi_device_id qca_bluetooth_acpi_match[] = {
  2320. { "QCOM2066", (kernel_ulong_t)&qca_soc_data_qca2066 },
  2321. { "QCOM6390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2322. { "DLA16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2323. { "DLB16390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2324. { "DLB26390", (kernel_ulong_t)&qca_soc_data_qca6390 },
  2325. { },
  2326. };
  2327. MODULE_DEVICE_TABLE(acpi, qca_bluetooth_acpi_match);
  2328. #endif
  2329. #ifdef CONFIG_DEV_COREDUMP
  2330. static void hciqca_coredump(struct device *dev)
  2331. {
  2332. struct serdev_device *serdev = to_serdev_device(dev);
  2333. struct qca_serdev *qcadev = serdev_device_get_drvdata(serdev);
  2334. struct hci_uart *hu = &qcadev->serdev_hu;
  2335. struct hci_dev *hdev = hu->hdev;
  2336. if (hdev->dump.coredump)
  2337. hdev->dump.coredump(hdev);
  2338. }
  2339. #endif
  2340. static struct serdev_device_driver qca_serdev_driver = {
  2341. .probe = qca_serdev_probe,
  2342. .remove = qca_serdev_remove,
  2343. .shutdown = qca_serdev_shutdown,
  2344. .driver = {
  2345. .name = "hci_uart_qca",
  2346. .of_match_table = of_match_ptr(qca_bluetooth_of_match),
  2347. .acpi_match_table = ACPI_PTR(qca_bluetooth_acpi_match),
  2348. .pm = &qca_pm_ops,
  2349. #ifdef CONFIG_DEV_COREDUMP
  2350. .coredump = hciqca_coredump,
  2351. #endif
  2352. },
  2353. };
  2354. int __init qca_init(void)
  2355. {
  2356. serdev_device_driver_register(&qca_serdev_driver);
  2357. return hci_uart_register_proto(&qca_proto);
  2358. }
  2359. int __exit qca_deinit(void)
  2360. {
  2361. serdev_device_driver_unregister(&qca_serdev_driver);
  2362. return hci_uart_unregister_proto(&qca_proto);
  2363. }