cpuidle.c 1.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2024, Ventana Micro Systems Inc
  4. * Author: Sunil V L <sunilvl@ventanamicro.com>
  5. *
  6. */
  7. #include <linux/acpi.h>
  8. #include <acpi/processor.h>
  9. #include <linux/cpu_pm.h>
  10. #include <linux/cpuidle.h>
  11. #include <linux/suspend.h>
  12. #include <asm/cpuidle.h>
  13. #include <asm/sbi.h>
  14. #include <asm/suspend.h>
  15. #define RISCV_FFH_LPI_TYPE_MASK GENMASK_ULL(63, 60)
  16. #define RISCV_FFH_LPI_RSVD_MASK GENMASK_ULL(59, 32)
  17. #define RISCV_FFH_LPI_TYPE_SBI BIT_ULL(60)
  18. static int acpi_cpu_init_idle(unsigned int cpu)
  19. {
  20. int i;
  21. struct acpi_lpi_state *lpi;
  22. struct acpi_processor *pr = per_cpu(processors, cpu);
  23. if (unlikely(!pr || !pr->flags.has_lpi))
  24. return -EINVAL;
  25. if (!riscv_sbi_hsm_is_supported())
  26. return -ENODEV;
  27. if (pr->power.count <= 1)
  28. return -ENODEV;
  29. for (i = 1; i < pr->power.count; i++) {
  30. u32 state;
  31. lpi = &pr->power.lpi_states[i];
  32. /*
  33. * Validate Entry Method as per FFH spec.
  34. * bits[63:60] should be 0x1
  35. * bits[59:32] should be 0x0
  36. * bits[31:0] represent a SBI power_state
  37. */
  38. if (((lpi->address & RISCV_FFH_LPI_TYPE_MASK) != RISCV_FFH_LPI_TYPE_SBI) ||
  39. (lpi->address & RISCV_FFH_LPI_RSVD_MASK)) {
  40. pr_warn("Invalid LPI entry method %#llx\n", lpi->address);
  41. return -EINVAL;
  42. }
  43. state = lpi->address;
  44. if (!riscv_sbi_suspend_state_is_valid(state)) {
  45. pr_warn("Invalid SBI power state %#x\n", state);
  46. return -EINVAL;
  47. }
  48. }
  49. return 0;
  50. }
  51. int acpi_processor_ffh_lpi_probe(unsigned int cpu)
  52. {
  53. return acpi_cpu_init_idle(cpu);
  54. }
  55. int acpi_processor_ffh_lpi_enter(struct acpi_lpi_state *lpi)
  56. {
  57. u32 state = lpi->address;
  58. if (state & SBI_HSM_SUSP_NON_RET_BIT)
  59. return CPU_PM_CPU_IDLE_ENTER_PARAM(riscv_sbi_hart_suspend,
  60. lpi->index,
  61. state);
  62. else
  63. return CPU_PM_CPU_IDLE_ENTER_RETENTION_PARAM(riscv_sbi_hart_suspend,
  64. lpi->index,
  65. state);
  66. }