qaic_ssr.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */
  3. /* Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. */
  4. #include <asm/byteorder.h>
  5. #include <drm/drm_file.h>
  6. #include <drm/drm_managed.h>
  7. #include <linux/devcoredump.h>
  8. #include <linux/device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mhi.h>
  11. #include <linux/workqueue.h>
  12. #include "qaic.h"
  13. #include "qaic_ssr.h"
  14. #define SSR_RESP_MSG_SZ 32
  15. #define SSR_MHI_BUF_SIZE SZ_64K
  16. #define SSR_MEM_READ_DATA_SIZE ((u64)SSR_MHI_BUF_SIZE - sizeof(struct ssr_crashdump))
  17. #define SSR_MEM_READ_CHUNK_SIZE ((u64)SSR_MEM_READ_DATA_SIZE - sizeof(struct ssr_memory_read_rsp))
  18. #define DEBUG_TRANSFER_INFO BIT(0)
  19. #define DEBUG_TRANSFER_INFO_RSP BIT(1)
  20. #define MEMORY_READ BIT(2)
  21. #define MEMORY_READ_RSP BIT(3)
  22. #define DEBUG_TRANSFER_DONE BIT(4)
  23. #define DEBUG_TRANSFER_DONE_RSP BIT(5)
  24. #define SSR_EVENT BIT(8)
  25. #define SSR_EVENT_RSP BIT(9)
  26. #define SSR_EVENT_NACK BIT(0)
  27. #define BEFORE_SHUTDOWN BIT(1)
  28. #define AFTER_SHUTDOWN BIT(2)
  29. #define BEFORE_POWER_UP BIT(3)
  30. #define AFTER_POWER_UP BIT(4)
  31. struct debug_info_table {
  32. /* Save preferences. Default is mandatory */
  33. u64 save_perf;
  34. /* Base address of the debug region */
  35. u64 mem_base;
  36. /* Size of debug region in bytes */
  37. u64 len;
  38. /* Description */
  39. char desc[20];
  40. /* Filename of debug region */
  41. char filename[20];
  42. };
  43. struct _ssr_hdr {
  44. __le32 cmd;
  45. __le32 len;
  46. __le32 dbc_id;
  47. };
  48. struct ssr_hdr {
  49. u32 cmd;
  50. u32 len;
  51. u32 dbc_id;
  52. };
  53. struct ssr_debug_transfer_info {
  54. struct ssr_hdr hdr;
  55. u32 resv;
  56. u64 tbl_addr;
  57. u64 tbl_len;
  58. } __packed;
  59. struct ssr_debug_transfer_info_rsp {
  60. struct _ssr_hdr hdr;
  61. __le32 ret;
  62. } __packed;
  63. struct ssr_memory_read {
  64. struct _ssr_hdr hdr;
  65. __le32 resv;
  66. __le64 addr;
  67. __le64 len;
  68. } __packed;
  69. struct ssr_memory_read_rsp {
  70. struct _ssr_hdr hdr;
  71. __le32 resv;
  72. u8 data[];
  73. } __packed;
  74. struct ssr_debug_transfer_done {
  75. struct _ssr_hdr hdr;
  76. __le32 resv;
  77. } __packed;
  78. struct ssr_debug_transfer_done_rsp {
  79. struct _ssr_hdr hdr;
  80. __le32 ret;
  81. } __packed;
  82. struct ssr_event {
  83. struct ssr_hdr hdr;
  84. u32 event;
  85. } __packed;
  86. struct ssr_event_rsp {
  87. struct _ssr_hdr hdr;
  88. __le32 event;
  89. } __packed;
  90. struct ssr_resp {
  91. /* Work struct to schedule work coming on QAIC_SSR channel */
  92. struct work_struct work;
  93. /* Root struct of device, used to access device resources */
  94. struct qaic_device *qdev;
  95. /* Buffer used by MHI for transfer requests */
  96. u8 data[] __aligned(8);
  97. };
  98. /* SSR crashdump book keeping structure */
  99. struct ssr_dump_info {
  100. /* DBC associated with this SSR crashdump */
  101. struct dma_bridge_chan *dbc;
  102. /*
  103. * It will be used when we complete the crashdump download and switch
  104. * to waiting on SSR events
  105. */
  106. struct ssr_resp *resp;
  107. /* MEMORY READ request MHI buffer.*/
  108. struct ssr_memory_read *read_buf_req;
  109. /* TRUE: ->read_buf_req is queued for MHI transaction. FALSE: Otherwise */
  110. bool read_buf_req_queued;
  111. /* Address of table in host */
  112. void *tbl_addr;
  113. /* Total size of table */
  114. u64 tbl_len;
  115. /* Offset of table(->tbl_addr) where the new chunk will be dumped */
  116. u64 tbl_off;
  117. /* Address of table in device/target */
  118. u64 tbl_addr_dev;
  119. /* Ptr to the entire dump */
  120. void *dump_addr;
  121. /* Entire crashdump size */
  122. u64 dump_sz;
  123. /* Offset of crashdump(->dump_addr) where the new chunk will be dumped */
  124. u64 dump_off;
  125. /* Points to the table entry we are currently downloading */
  126. struct debug_info_table *tbl_ent;
  127. /* Offset in the current table entry(->tbl_ent) for next chuck */
  128. u64 tbl_ent_off;
  129. };
  130. struct ssr_crashdump {
  131. /*
  132. * Points to a book keeping struct maintained by MHI SSR device while
  133. * downloading a SSR crashdump. It is NULL when crashdump downloading
  134. * not in progress.
  135. */
  136. struct ssr_dump_info *dump_info;
  137. /* Work struct to schedule work coming on QAIC_SSR channel */
  138. struct work_struct work;
  139. /* Root struct of device, used to access device resources */
  140. struct qaic_device *qdev;
  141. /* Buffer used by MHI for transfer requests */
  142. u8 data[];
  143. };
  144. #define QAIC_SSR_DUMP_V1_MAGIC 0x1234567890abcdef
  145. #define QAIC_SSR_DUMP_V1_VER 1
  146. struct dump_file_meta {
  147. u64 magic;
  148. u64 version;
  149. u64 size; /* Total size of the entire dump */
  150. u64 tbl_len; /* Length of the table in byte */
  151. };
  152. /*
  153. * Layout of crashdump
  154. * +------------------------------------------+
  155. * | Crashdump Meta structure |
  156. * | type: struct dump_file_meta |
  157. * +------------------------------------------+
  158. * | Crashdump Table |
  159. * | type: array of struct debug_info_table |
  160. * | |
  161. * | |
  162. * | |
  163. * +------------------------------------------+
  164. * | Crashdump |
  165. * | |
  166. * | |
  167. * | |
  168. * | |
  169. * | |
  170. * +------------------------------------------+
  171. */
  172. static void free_ssr_dump_info(struct ssr_crashdump *ssr_crash)
  173. {
  174. struct ssr_dump_info *dump_info = ssr_crash->dump_info;
  175. ssr_crash->dump_info = NULL;
  176. if (!dump_info)
  177. return;
  178. if (!dump_info->read_buf_req_queued)
  179. kfree(dump_info->read_buf_req);
  180. vfree(dump_info->tbl_addr);
  181. vfree(dump_info->dump_addr);
  182. kfree(dump_info);
  183. }
  184. void qaic_clean_up_ssr(struct qaic_device *qdev)
  185. {
  186. struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
  187. if (!ssr_crash)
  188. return;
  189. qaic_dbc_exit_ssr(qdev);
  190. free_ssr_dump_info(ssr_crash);
  191. }
  192. static int alloc_dump(struct ssr_dump_info *dump_info)
  193. {
  194. struct debug_info_table *tbl_ent = dump_info->tbl_addr;
  195. struct dump_file_meta *dump_meta;
  196. u64 tbl_sz_lp = 0;
  197. u64 dump_size = 0;
  198. while (tbl_sz_lp < dump_info->tbl_len) {
  199. le64_to_cpus(&tbl_ent->save_perf);
  200. le64_to_cpus(&tbl_ent->mem_base);
  201. le64_to_cpus(&tbl_ent->len);
  202. if (tbl_ent->len == 0)
  203. return -EINVAL;
  204. dump_size += tbl_ent->len;
  205. tbl_ent++;
  206. tbl_sz_lp += sizeof(*tbl_ent);
  207. }
  208. dump_info->dump_sz = dump_size + dump_info->tbl_len + sizeof(*dump_meta);
  209. dump_info->dump_addr = vzalloc(dump_info->dump_sz);
  210. if (!dump_info->dump_addr)
  211. return -ENOMEM;
  212. /* Copy crashdump meta and table */
  213. dump_meta = dump_info->dump_addr;
  214. dump_meta->magic = QAIC_SSR_DUMP_V1_MAGIC;
  215. dump_meta->version = QAIC_SSR_DUMP_V1_VER;
  216. dump_meta->size = dump_info->dump_sz;
  217. dump_meta->tbl_len = dump_info->tbl_len;
  218. memcpy(dump_info->dump_addr + sizeof(*dump_meta), dump_info->tbl_addr, dump_info->tbl_len);
  219. /* Offset by crashdump meta and table (copied above) */
  220. dump_info->dump_off = dump_info->tbl_len + sizeof(*dump_meta);
  221. return 0;
  222. }
  223. static int send_xfer_done(struct qaic_device *qdev, void *resp, u32 dbc_id)
  224. {
  225. struct ssr_debug_transfer_done *xfer_done;
  226. int ret;
  227. xfer_done = kmalloc_obj(*xfer_done);
  228. if (!xfer_done) {
  229. ret = -ENOMEM;
  230. goto out;
  231. }
  232. ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, resp, SSR_RESP_MSG_SZ, MHI_EOT);
  233. if (ret)
  234. goto free_xfer_done;
  235. xfer_done->hdr.cmd = cpu_to_le32(DEBUG_TRANSFER_DONE);
  236. xfer_done->hdr.len = cpu_to_le32(sizeof(*xfer_done));
  237. xfer_done->hdr.dbc_id = cpu_to_le32(dbc_id);
  238. ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, xfer_done, sizeof(*xfer_done), MHI_EOT);
  239. if (ret)
  240. goto free_xfer_done;
  241. return 0;
  242. free_xfer_done:
  243. kfree(xfer_done);
  244. out:
  245. return ret;
  246. }
  247. static int mem_read_req(struct qaic_device *qdev, u64 dest_addr, u64 dest_len)
  248. {
  249. struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
  250. struct ssr_memory_read *read_buf_req;
  251. struct ssr_dump_info *dump_info;
  252. int ret;
  253. dump_info = ssr_crash->dump_info;
  254. ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, ssr_crash->data, SSR_MEM_READ_DATA_SIZE,
  255. MHI_EOT);
  256. if (ret)
  257. goto out;
  258. read_buf_req = dump_info->read_buf_req;
  259. read_buf_req->hdr.cmd = cpu_to_le32(MEMORY_READ);
  260. read_buf_req->hdr.len = cpu_to_le32(sizeof(*read_buf_req));
  261. read_buf_req->hdr.dbc_id = cpu_to_le32(qdev->ssr_dbc);
  262. read_buf_req->addr = cpu_to_le64(dest_addr);
  263. read_buf_req->len = cpu_to_le64(dest_len);
  264. ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, read_buf_req, sizeof(*read_buf_req),
  265. MHI_EOT);
  266. if (!ret)
  267. dump_info->read_buf_req_queued = true;
  268. out:
  269. return ret;
  270. }
  271. static int ssr_copy_table(struct ssr_dump_info *dump_info, void *data, u64 len)
  272. {
  273. if (len > dump_info->tbl_len - dump_info->tbl_off)
  274. return -EINVAL;
  275. memcpy(dump_info->tbl_addr + dump_info->tbl_off, data, len);
  276. dump_info->tbl_off += len;
  277. /* Entire table has been downloaded, alloc dump memory */
  278. if (dump_info->tbl_off == dump_info->tbl_len) {
  279. dump_info->tbl_ent = dump_info->tbl_addr;
  280. return alloc_dump(dump_info);
  281. }
  282. return 0;
  283. }
  284. static int ssr_copy_dump(struct ssr_dump_info *dump_info, void *data, u64 len)
  285. {
  286. struct debug_info_table *tbl_ent;
  287. tbl_ent = dump_info->tbl_ent;
  288. if (len > tbl_ent->len - dump_info->tbl_ent_off)
  289. return -EINVAL;
  290. memcpy(dump_info->dump_addr + dump_info->dump_off, data, len);
  291. dump_info->dump_off += len;
  292. dump_info->tbl_ent_off += len;
  293. /*
  294. * Current segment (a entry in table) of the crashdump is complete,
  295. * move to next one
  296. */
  297. if (tbl_ent->len == dump_info->tbl_ent_off) {
  298. dump_info->tbl_ent++;
  299. dump_info->tbl_ent_off = 0;
  300. }
  301. return 0;
  302. }
  303. static void ssr_dump_worker(struct work_struct *work)
  304. {
  305. struct ssr_crashdump *ssr_crash = container_of(work, struct ssr_crashdump, work);
  306. struct qaic_device *qdev = ssr_crash->qdev;
  307. struct ssr_memory_read_rsp *mem_rd_resp;
  308. struct debug_info_table *tbl_ent;
  309. struct ssr_dump_info *dump_info;
  310. u64 dest_addr, dest_len;
  311. struct _ssr_hdr *_hdr;
  312. struct ssr_hdr hdr;
  313. u64 data_len;
  314. int ret;
  315. mem_rd_resp = (struct ssr_memory_read_rsp *)ssr_crash->data;
  316. _hdr = &mem_rd_resp->hdr;
  317. hdr.cmd = le32_to_cpu(_hdr->cmd);
  318. hdr.len = le32_to_cpu(_hdr->len);
  319. hdr.dbc_id = le32_to_cpu(_hdr->dbc_id);
  320. if (hdr.dbc_id != qdev->ssr_dbc)
  321. goto reset_device;
  322. dump_info = ssr_crash->dump_info;
  323. if (!dump_info)
  324. goto reset_device;
  325. if (hdr.cmd != MEMORY_READ_RSP)
  326. goto free_dump_info;
  327. if (hdr.len > SSR_MEM_READ_DATA_SIZE)
  328. goto free_dump_info;
  329. data_len = hdr.len - sizeof(*mem_rd_resp);
  330. if (dump_info->tbl_off < dump_info->tbl_len) /* Chunk belongs to table */
  331. ret = ssr_copy_table(dump_info, mem_rd_resp->data, data_len);
  332. else /* Chunk belongs to crashdump */
  333. ret = ssr_copy_dump(dump_info, mem_rd_resp->data, data_len);
  334. if (ret)
  335. goto free_dump_info;
  336. if (dump_info->tbl_off < dump_info->tbl_len) {
  337. /* Continue downloading table */
  338. dest_addr = dump_info->tbl_addr_dev + dump_info->tbl_off;
  339. dest_len = min(SSR_MEM_READ_CHUNK_SIZE, dump_info->tbl_len - dump_info->tbl_off);
  340. ret = mem_read_req(qdev, dest_addr, dest_len);
  341. } else if (dump_info->dump_off < dump_info->dump_sz) {
  342. /* Continue downloading crashdump */
  343. tbl_ent = dump_info->tbl_ent;
  344. dest_addr = tbl_ent->mem_base + dump_info->tbl_ent_off;
  345. dest_len = min(SSR_MEM_READ_CHUNK_SIZE, tbl_ent->len - dump_info->tbl_ent_off);
  346. ret = mem_read_req(qdev, dest_addr, dest_len);
  347. } else {
  348. /* Crashdump download complete */
  349. ret = send_xfer_done(qdev, dump_info->resp->data, hdr.dbc_id);
  350. }
  351. /* Most likely a MHI xfer has failed */
  352. if (ret)
  353. goto free_dump_info;
  354. return;
  355. free_dump_info:
  356. /* Free the allocated memory */
  357. free_ssr_dump_info(ssr_crash);
  358. reset_device:
  359. /*
  360. * After subsystem crashes in device crashdump collection begins but
  361. * something went wrong while collecting crashdump, now instead of
  362. * handling this error we just reset the device as the best effort has
  363. * been made
  364. */
  365. mhi_soc_reset(qdev->mhi_cntrl);
  366. }
  367. static struct ssr_dump_info *alloc_dump_info(struct qaic_device *qdev,
  368. struct ssr_debug_transfer_info *debug_info)
  369. {
  370. struct ssr_dump_info *dump_info;
  371. int ret;
  372. le64_to_cpus(&debug_info->tbl_len);
  373. le64_to_cpus(&debug_info->tbl_addr);
  374. if (debug_info->tbl_len == 0 ||
  375. debug_info->tbl_len % sizeof(struct debug_info_table) != 0) {
  376. ret = -EINVAL;
  377. goto out;
  378. }
  379. /* Allocate SSR crashdump book keeping structure */
  380. dump_info = kzalloc_obj(*dump_info);
  381. if (!dump_info) {
  382. ret = -ENOMEM;
  383. goto out;
  384. }
  385. /* Buffer used to send MEMORY READ request to device via MHI */
  386. dump_info->read_buf_req = kzalloc_obj(*dump_info->read_buf_req);
  387. if (!dump_info->read_buf_req) {
  388. ret = -ENOMEM;
  389. goto free_dump_info;
  390. }
  391. /* Crashdump meta table buffer */
  392. dump_info->tbl_addr = vzalloc(debug_info->tbl_len);
  393. if (!dump_info->tbl_addr) {
  394. ret = -ENOMEM;
  395. goto free_read_buf_req;
  396. }
  397. dump_info->tbl_addr_dev = debug_info->tbl_addr;
  398. dump_info->tbl_len = debug_info->tbl_len;
  399. return dump_info;
  400. free_read_buf_req:
  401. kfree(dump_info->read_buf_req);
  402. free_dump_info:
  403. kfree(dump_info);
  404. out:
  405. return ERR_PTR(ret);
  406. }
  407. static int dbg_xfer_info_rsp(struct qaic_device *qdev, struct dma_bridge_chan *dbc,
  408. struct ssr_debug_transfer_info *debug_info)
  409. {
  410. struct ssr_debug_transfer_info_rsp *debug_rsp;
  411. struct ssr_crashdump *ssr_crash = NULL;
  412. int ret = 0, ret2;
  413. debug_rsp = kmalloc_obj(*debug_rsp);
  414. if (!debug_rsp)
  415. return -ENOMEM;
  416. if (!qdev->ssr_mhi_buf) {
  417. ret = -ENOMEM;
  418. goto send_rsp;
  419. }
  420. if (dbc->state != DBC_STATE_BEFORE_POWER_UP) {
  421. ret = -EINVAL;
  422. goto send_rsp;
  423. }
  424. ssr_crash = qdev->ssr_mhi_buf;
  425. ssr_crash->dump_info = alloc_dump_info(qdev, debug_info);
  426. if (IS_ERR(ssr_crash->dump_info)) {
  427. ret = PTR_ERR(ssr_crash->dump_info);
  428. ssr_crash->dump_info = NULL;
  429. }
  430. send_rsp:
  431. debug_rsp->hdr.cmd = cpu_to_le32(DEBUG_TRANSFER_INFO_RSP);
  432. debug_rsp->hdr.len = cpu_to_le32(sizeof(*debug_rsp));
  433. debug_rsp->hdr.dbc_id = cpu_to_le32(dbc->id);
  434. /*
  435. * 0 = Return an ACK confirming the host is ready to download crashdump
  436. * 1 = Return an NACK confirming the host is not ready to download crashdump
  437. */
  438. debug_rsp->ret = cpu_to_le32(ret ? 1 : 0);
  439. ret2 = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, debug_rsp, sizeof(*debug_rsp), MHI_EOT);
  440. if (ret2) {
  441. free_ssr_dump_info(ssr_crash);
  442. kfree(debug_rsp);
  443. return ret2;
  444. }
  445. return ret;
  446. }
  447. static void dbg_xfer_done_rsp(struct qaic_device *qdev, struct dma_bridge_chan *dbc,
  448. struct ssr_debug_transfer_done_rsp *xfer_rsp)
  449. {
  450. struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
  451. u32 status = le32_to_cpu(xfer_rsp->ret);
  452. struct device *dev = &qdev->pdev->dev;
  453. struct ssr_dump_info *dump_info;
  454. dump_info = ssr_crash->dump_info;
  455. if (!dump_info)
  456. return;
  457. if (status) {
  458. free_ssr_dump_info(ssr_crash);
  459. return;
  460. }
  461. dev_coredumpv(dev, dump_info->dump_addr, dump_info->dump_sz, GFP_KERNEL);
  462. /* dev_coredumpv will free dump_info->dump_addr */
  463. dump_info->dump_addr = NULL;
  464. free_ssr_dump_info(ssr_crash);
  465. }
  466. static void ssr_worker(struct work_struct *work)
  467. {
  468. struct ssr_resp *resp = container_of(work, struct ssr_resp, work);
  469. struct ssr_hdr *hdr = (struct ssr_hdr *)resp->data;
  470. struct ssr_dump_info *dump_info = NULL;
  471. struct qaic_device *qdev = resp->qdev;
  472. struct ssr_crashdump *ssr_crash;
  473. struct ssr_event_rsp *event_rsp;
  474. struct dma_bridge_chan *dbc;
  475. struct ssr_event *event;
  476. u32 ssr_event_ack;
  477. int ret;
  478. le32_to_cpus(&hdr->cmd);
  479. le32_to_cpus(&hdr->len);
  480. le32_to_cpus(&hdr->dbc_id);
  481. if (hdr->len > SSR_RESP_MSG_SZ)
  482. goto out;
  483. if (hdr->dbc_id >= qdev->num_dbc)
  484. goto out;
  485. dbc = &qdev->dbc[hdr->dbc_id];
  486. switch (hdr->cmd) {
  487. case DEBUG_TRANSFER_INFO:
  488. ret = dbg_xfer_info_rsp(qdev, dbc, (struct ssr_debug_transfer_info *)resp->data);
  489. if (ret)
  490. break;
  491. ssr_crash = qdev->ssr_mhi_buf;
  492. dump_info = ssr_crash->dump_info;
  493. dump_info->dbc = dbc;
  494. dump_info->resp = resp;
  495. /* Start by downloading debug table */
  496. ret = mem_read_req(qdev, dump_info->tbl_addr_dev,
  497. min(dump_info->tbl_len, SSR_MEM_READ_CHUNK_SIZE));
  498. if (ret) {
  499. free_ssr_dump_info(ssr_crash);
  500. break;
  501. }
  502. /*
  503. * Till now everything went fine, which means that we will be
  504. * collecting crashdump chunk by chunk. Do not queue a response
  505. * buffer for SSR cmds till the crashdump is complete.
  506. */
  507. return;
  508. case SSR_EVENT:
  509. event = (struct ssr_event *)hdr;
  510. le32_to_cpus(&event->event);
  511. ssr_event_ack = event->event;
  512. ssr_crash = qdev->ssr_mhi_buf;
  513. switch (event->event) {
  514. case BEFORE_SHUTDOWN:
  515. set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_BEFORE_SHUTDOWN);
  516. qaic_dbc_enter_ssr(qdev, hdr->dbc_id);
  517. break;
  518. case AFTER_SHUTDOWN:
  519. set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_AFTER_SHUTDOWN);
  520. break;
  521. case BEFORE_POWER_UP:
  522. set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_BEFORE_POWER_UP);
  523. break;
  524. case AFTER_POWER_UP:
  525. /*
  526. * If dump info is a non NULL value it means that we
  527. * have received this SSR event while downloading a
  528. * crashdump for this DBC is still in progress. NACK
  529. * the SSR event
  530. */
  531. if (ssr_crash && ssr_crash->dump_info) {
  532. free_ssr_dump_info(ssr_crash);
  533. ssr_event_ack = SSR_EVENT_NACK;
  534. break;
  535. }
  536. set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_AFTER_POWER_UP);
  537. break;
  538. default:
  539. break;
  540. }
  541. event_rsp = kmalloc_obj(*event_rsp);
  542. if (!event_rsp)
  543. break;
  544. event_rsp->hdr.cmd = cpu_to_le32(SSR_EVENT_RSP);
  545. event_rsp->hdr.len = cpu_to_le32(sizeof(*event_rsp));
  546. event_rsp->hdr.dbc_id = cpu_to_le32(hdr->dbc_id);
  547. event_rsp->event = cpu_to_le32(ssr_event_ack);
  548. ret = mhi_queue_buf(qdev->ssr_ch, DMA_TO_DEVICE, event_rsp, sizeof(*event_rsp),
  549. MHI_EOT);
  550. if (ret)
  551. kfree(event_rsp);
  552. if (event->event == AFTER_POWER_UP && ssr_event_ack != SSR_EVENT_NACK) {
  553. qaic_dbc_exit_ssr(qdev);
  554. set_dbc_state(qdev, hdr->dbc_id, DBC_STATE_IDLE);
  555. }
  556. break;
  557. case DEBUG_TRANSFER_DONE_RSP:
  558. dbg_xfer_done_rsp(qdev, dbc, (struct ssr_debug_transfer_done_rsp *)hdr);
  559. break;
  560. default:
  561. break;
  562. }
  563. out:
  564. ret = mhi_queue_buf(qdev->ssr_ch, DMA_FROM_DEVICE, resp->data, SSR_RESP_MSG_SZ, MHI_EOT);
  565. if (ret)
  566. kfree(resp);
  567. }
  568. static int qaic_ssr_mhi_probe(struct mhi_device *mhi_dev, const struct mhi_device_id *id)
  569. {
  570. struct qaic_device *qdev = pci_get_drvdata(to_pci_dev(mhi_dev->mhi_cntrl->cntrl_dev));
  571. struct ssr_resp *resp;
  572. int ret;
  573. ret = mhi_prepare_for_transfer(mhi_dev);
  574. if (ret)
  575. return ret;
  576. resp = kzalloc(sizeof(*resp) + SSR_RESP_MSG_SZ, GFP_KERNEL);
  577. if (!resp) {
  578. mhi_unprepare_from_transfer(mhi_dev);
  579. return -ENOMEM;
  580. }
  581. resp->qdev = qdev;
  582. INIT_WORK(&resp->work, ssr_worker);
  583. ret = mhi_queue_buf(mhi_dev, DMA_FROM_DEVICE, resp->data, SSR_RESP_MSG_SZ, MHI_EOT);
  584. if (ret) {
  585. kfree(resp);
  586. mhi_unprepare_from_transfer(mhi_dev);
  587. return ret;
  588. }
  589. dev_set_drvdata(&mhi_dev->dev, qdev);
  590. qdev->ssr_ch = mhi_dev;
  591. return 0;
  592. }
  593. static void qaic_ssr_mhi_remove(struct mhi_device *mhi_dev)
  594. {
  595. struct qaic_device *qdev;
  596. qdev = dev_get_drvdata(&mhi_dev->dev);
  597. mhi_unprepare_from_transfer(qdev->ssr_ch);
  598. qdev->ssr_ch = NULL;
  599. }
  600. static void qaic_ssr_mhi_ul_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
  601. {
  602. struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
  603. struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
  604. struct _ssr_hdr *hdr = mhi_result->buf_addr;
  605. struct ssr_dump_info *dump_info;
  606. if (mhi_result->transaction_status) {
  607. kfree(mhi_result->buf_addr);
  608. return;
  609. }
  610. /*
  611. * MEMORY READ is used to download crashdump. And crashdump is
  612. * downloaded chunk by chunk in a series of MEMORY READ SSR commands.
  613. * Hence to avoid too many kmalloc() and kfree() of the same MEMORY READ
  614. * request buffer, we allocate only one such buffer and free it only
  615. * once.
  616. */
  617. if (le32_to_cpu(hdr->cmd) == MEMORY_READ) {
  618. dump_info = ssr_crash->dump_info;
  619. if (dump_info) {
  620. dump_info->read_buf_req_queued = false;
  621. return;
  622. }
  623. }
  624. kfree(mhi_result->buf_addr);
  625. }
  626. static void qaic_ssr_mhi_dl_xfer_cb(struct mhi_device *mhi_dev, struct mhi_result *mhi_result)
  627. {
  628. struct ssr_resp *resp = container_of(mhi_result->buf_addr, struct ssr_resp, data);
  629. struct qaic_device *qdev = dev_get_drvdata(&mhi_dev->dev);
  630. struct ssr_crashdump *ssr_crash = qdev->ssr_mhi_buf;
  631. bool memory_read_rsp = false;
  632. if (ssr_crash && ssr_crash->data == mhi_result->buf_addr)
  633. memory_read_rsp = true;
  634. if (mhi_result->transaction_status) {
  635. /* Do not free SSR crashdump buffer as it allocated via managed APIs */
  636. if (!memory_read_rsp)
  637. kfree(resp);
  638. return;
  639. }
  640. if (memory_read_rsp)
  641. queue_work(qdev->ssr_wq, &ssr_crash->work);
  642. else
  643. queue_work(qdev->ssr_wq, &resp->work);
  644. }
  645. static const struct mhi_device_id qaic_ssr_mhi_match_table[] = {
  646. { .chan = "QAIC_SSR", },
  647. {},
  648. };
  649. static struct mhi_driver qaic_ssr_mhi_driver = {
  650. .id_table = qaic_ssr_mhi_match_table,
  651. .remove = qaic_ssr_mhi_remove,
  652. .probe = qaic_ssr_mhi_probe,
  653. .ul_xfer_cb = qaic_ssr_mhi_ul_xfer_cb,
  654. .dl_xfer_cb = qaic_ssr_mhi_dl_xfer_cb,
  655. .driver = {
  656. .name = "qaic_ssr",
  657. },
  658. };
  659. int qaic_ssr_init(struct qaic_device *qdev, struct drm_device *drm)
  660. {
  661. struct ssr_crashdump *ssr_crash;
  662. qdev->ssr_dbc = QAIC_SSR_DBC_SENTINEL;
  663. /*
  664. * Device requests only one SSR at a time. So allocating only one
  665. * buffer to download crashdump is good enough.
  666. */
  667. ssr_crash = drmm_kzalloc(drm, SSR_MHI_BUF_SIZE, GFP_KERNEL);
  668. if (!ssr_crash)
  669. return -ENOMEM;
  670. ssr_crash->qdev = qdev;
  671. INIT_WORK(&ssr_crash->work, ssr_dump_worker);
  672. qdev->ssr_mhi_buf = ssr_crash;
  673. return 0;
  674. }
  675. int qaic_ssr_register(void)
  676. {
  677. return mhi_driver_register(&qaic_ssr_mhi_driver);
  678. }
  679. void qaic_ssr_unregister(void)
  680. {
  681. mhi_driver_unregister(&qaic_ssr_mhi_driver);
  682. }