ethosu_drv.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only or MIT
  2. // Copyright (C) 2025 Arm, Ltd.
  3. #include <linux/bitfield.h>
  4. #include <linux/clk.h>
  5. #include <linux/genalloc.h>
  6. #include <linux/io.h>
  7. #include <linux/iopoll.h>
  8. #include <linux/module.h>
  9. #include <linux/mod_devicetable.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm_runtime.h>
  12. #include <drm/drm_drv.h>
  13. #include <drm/drm_ioctl.h>
  14. #include <drm/drm_utils.h>
  15. #include <drm/drm_gem.h>
  16. #include <drm/drm_accel.h>
  17. #include <drm/ethosu_accel.h>
  18. #include "ethosu_drv.h"
  19. #include "ethosu_device.h"
  20. #include "ethosu_gem.h"
  21. #include "ethosu_job.h"
  22. static int ethosu_ioctl_dev_query(struct drm_device *ddev, void *data,
  23. struct drm_file *file)
  24. {
  25. struct ethosu_device *ethosudev = to_ethosu_device(ddev);
  26. struct drm_ethosu_dev_query *args = data;
  27. if (!args->pointer) {
  28. switch (args->type) {
  29. case DRM_ETHOSU_DEV_QUERY_NPU_INFO:
  30. args->size = sizeof(ethosudev->npu_info);
  31. return 0;
  32. default:
  33. return -EINVAL;
  34. }
  35. }
  36. switch (args->type) {
  37. case DRM_ETHOSU_DEV_QUERY_NPU_INFO:
  38. if (args->size < offsetofend(struct drm_ethosu_npu_info, sram_size))
  39. return -EINVAL;
  40. return copy_struct_to_user(u64_to_user_ptr(args->pointer),
  41. args->size,
  42. &ethosudev->npu_info,
  43. sizeof(ethosudev->npu_info), NULL);
  44. default:
  45. return -EINVAL;
  46. }
  47. }
  48. #define ETHOSU_BO_FLAGS DRM_ETHOSU_BO_NO_MMAP
  49. static int ethosu_ioctl_bo_create(struct drm_device *ddev, void *data,
  50. struct drm_file *file)
  51. {
  52. struct drm_ethosu_bo_create *args = data;
  53. int cookie, ret;
  54. if (!drm_dev_enter(ddev, &cookie))
  55. return -ENODEV;
  56. if (!args->size || (args->flags & ~ETHOSU_BO_FLAGS)) {
  57. ret = -EINVAL;
  58. goto out_dev_exit;
  59. }
  60. ret = ethosu_gem_create_with_handle(file, ddev, &args->size,
  61. args->flags, &args->handle);
  62. out_dev_exit:
  63. drm_dev_exit(cookie);
  64. return ret;
  65. }
  66. static int ethosu_ioctl_bo_wait(struct drm_device *ddev, void *data,
  67. struct drm_file *file)
  68. {
  69. struct drm_ethosu_bo_wait *args = data;
  70. int cookie, ret;
  71. unsigned long timeout = drm_timeout_abs_to_jiffies(args->timeout_ns);
  72. if (args->pad)
  73. return -EINVAL;
  74. if (!drm_dev_enter(ddev, &cookie))
  75. return -ENODEV;
  76. ret = drm_gem_dma_resv_wait(file, args->handle, true, timeout);
  77. drm_dev_exit(cookie);
  78. return ret;
  79. }
  80. static int ethosu_ioctl_bo_mmap_offset(struct drm_device *ddev, void *data,
  81. struct drm_file *file)
  82. {
  83. struct drm_ethosu_bo_mmap_offset *args = data;
  84. struct drm_gem_object *obj;
  85. if (args->pad)
  86. return -EINVAL;
  87. obj = drm_gem_object_lookup(file, args->handle);
  88. if (!obj)
  89. return -ENOENT;
  90. args->offset = drm_vma_node_offset_addr(&obj->vma_node);
  91. drm_gem_object_put(obj);
  92. return 0;
  93. }
  94. static int ethosu_ioctl_cmdstream_bo_create(struct drm_device *ddev, void *data,
  95. struct drm_file *file)
  96. {
  97. struct drm_ethosu_cmdstream_bo_create *args = data;
  98. int cookie, ret;
  99. if (!drm_dev_enter(ddev, &cookie))
  100. return -ENODEV;
  101. if (!args->size || !args->data || args->pad || args->flags) {
  102. ret = -EINVAL;
  103. goto out_dev_exit;
  104. }
  105. args->flags |= DRM_ETHOSU_BO_NO_MMAP;
  106. ret = ethosu_gem_cmdstream_create(file, ddev, args->size, args->data,
  107. args->flags, &args->handle);
  108. out_dev_exit:
  109. drm_dev_exit(cookie);
  110. return ret;
  111. }
  112. static int ethosu_open(struct drm_device *ddev, struct drm_file *file)
  113. {
  114. int ret = 0;
  115. if (!try_module_get(THIS_MODULE))
  116. return -EINVAL;
  117. struct ethosu_file_priv __free(kfree) *priv = kzalloc_obj(*priv);
  118. if (!priv) {
  119. ret = -ENOMEM;
  120. goto err_put_mod;
  121. }
  122. priv->edev = to_ethosu_device(ddev);
  123. ret = ethosu_job_open(priv);
  124. if (ret)
  125. goto err_put_mod;
  126. file->driver_priv = no_free_ptr(priv);
  127. return 0;
  128. err_put_mod:
  129. module_put(THIS_MODULE);
  130. return ret;
  131. }
  132. static void ethosu_postclose(struct drm_device *ddev, struct drm_file *file)
  133. {
  134. ethosu_job_close(file->driver_priv);
  135. kfree(file->driver_priv);
  136. module_put(THIS_MODULE);
  137. }
  138. static const struct drm_ioctl_desc ethosu_drm_driver_ioctls[] = {
  139. #define ETHOSU_IOCTL(n, func, flags) \
  140. DRM_IOCTL_DEF_DRV(ETHOSU_##n, ethosu_ioctl_##func, flags)
  141. ETHOSU_IOCTL(DEV_QUERY, dev_query, 0),
  142. ETHOSU_IOCTL(BO_CREATE, bo_create, 0),
  143. ETHOSU_IOCTL(BO_WAIT, bo_wait, 0),
  144. ETHOSU_IOCTL(BO_MMAP_OFFSET, bo_mmap_offset, 0),
  145. ETHOSU_IOCTL(CMDSTREAM_BO_CREATE, cmdstream_bo_create, 0),
  146. ETHOSU_IOCTL(SUBMIT, submit, 0),
  147. };
  148. DEFINE_DRM_ACCEL_FOPS(ethosu_drm_driver_fops);
  149. /*
  150. * Ethosu driver version:
  151. * - 1.0 - initial interface
  152. */
  153. static const struct drm_driver ethosu_drm_driver = {
  154. .driver_features = DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
  155. .open = ethosu_open,
  156. .postclose = ethosu_postclose,
  157. .ioctls = ethosu_drm_driver_ioctls,
  158. .num_ioctls = ARRAY_SIZE(ethosu_drm_driver_ioctls),
  159. .fops = &ethosu_drm_driver_fops,
  160. .name = "ethosu",
  161. .desc = "Arm Ethos-U Accel driver",
  162. .major = 1,
  163. .minor = 0,
  164. .gem_create_object = ethosu_gem_create_object,
  165. };
  166. #define U65_DRAM_AXI_LIMIT_CFG 0x1f3f0002
  167. #define U65_SRAM_AXI_LIMIT_CFG 0x1f3f00b0
  168. #define U85_AXI_EXT_CFG 0x00021f3f
  169. #define U85_AXI_SRAM_CFG 0x00021f3f
  170. #define U85_MEM_ATTR0_CFG 0x00000000
  171. #define U85_MEM_ATTR2_CFG 0x000000b7
  172. static int ethosu_reset(struct ethosu_device *ethosudev)
  173. {
  174. int ret;
  175. u32 reg;
  176. writel_relaxed(RESET_PENDING_CSL, ethosudev->regs + NPU_REG_RESET);
  177. ret = readl_poll_timeout(ethosudev->regs + NPU_REG_STATUS, reg,
  178. !FIELD_GET(STATUS_RESET_STATUS, reg),
  179. USEC_PER_MSEC, USEC_PER_SEC);
  180. if (ret)
  181. return ret;
  182. if (!FIELD_GET(PROT_ACTIVE_CSL, readl_relaxed(ethosudev->regs + NPU_REG_PROT))) {
  183. dev_warn(ethosudev->base.dev, "Could not reset to non-secure mode (PROT = %x)\n",
  184. readl_relaxed(ethosudev->regs + NPU_REG_PROT));
  185. }
  186. /*
  187. * Assign region 2 (SRAM) to AXI M0 (AXILIMIT0),
  188. * everything else to AXI M1 (AXILIMIT2)
  189. */
  190. writel_relaxed(0x0000aa8a, ethosudev->regs + NPU_REG_REGIONCFG);
  191. if (ethosu_is_u65(ethosudev)) {
  192. writel_relaxed(U65_SRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT0);
  193. writel_relaxed(U65_DRAM_AXI_LIMIT_CFG, ethosudev->regs + NPU_REG_AXILIMIT2);
  194. } else {
  195. writel_relaxed(U85_AXI_SRAM_CFG, ethosudev->regs + NPU_REG_AXI_SRAM);
  196. writel_relaxed(U85_AXI_EXT_CFG, ethosudev->regs + NPU_REG_AXI_EXT);
  197. writel_relaxed(U85_MEM_ATTR0_CFG, ethosudev->regs + NPU_REG_MEM_ATTR0); // SRAM
  198. writel_relaxed(U85_MEM_ATTR2_CFG, ethosudev->regs + NPU_REG_MEM_ATTR2); // DRAM
  199. }
  200. if (ethosudev->sram)
  201. memset_io(ethosudev->sram, 0, ethosudev->npu_info.sram_size);
  202. return 0;
  203. }
  204. static int ethosu_device_resume(struct device *dev)
  205. {
  206. struct ethosu_device *ethosudev = dev_get_drvdata(dev);
  207. int ret;
  208. ret = clk_bulk_prepare_enable(ethosudev->num_clks, ethosudev->clks);
  209. if (ret)
  210. return ret;
  211. ret = ethosu_reset(ethosudev);
  212. if (!ret)
  213. return 0;
  214. clk_bulk_disable_unprepare(ethosudev->num_clks, ethosudev->clks);
  215. return ret;
  216. }
  217. static int ethosu_device_suspend(struct device *dev)
  218. {
  219. struct ethosu_device *ethosudev = dev_get_drvdata(dev);
  220. clk_bulk_disable_unprepare(ethosudev->num_clks, ethosudev->clks);
  221. return 0;
  222. }
  223. static int ethosu_sram_init(struct ethosu_device *ethosudev)
  224. {
  225. ethosudev->npu_info.sram_size = 0;
  226. ethosudev->srampool = of_gen_pool_get(ethosudev->base.dev->of_node, "sram", 0);
  227. if (!ethosudev->srampool)
  228. return 0;
  229. ethosudev->npu_info.sram_size = gen_pool_size(ethosudev->srampool);
  230. ethosudev->sram = (void __iomem *)gen_pool_dma_alloc(ethosudev->srampool,
  231. ethosudev->npu_info.sram_size,
  232. &ethosudev->sramphys);
  233. if (!ethosudev->sram) {
  234. dev_err(ethosudev->base.dev, "failed to allocate from SRAM pool\n");
  235. return -ENOMEM;
  236. }
  237. return 0;
  238. }
  239. static int ethosu_init(struct ethosu_device *ethosudev)
  240. {
  241. int ret;
  242. u32 id, config;
  243. ret = ethosu_device_resume(ethosudev->base.dev);
  244. if (ret)
  245. return ret;
  246. pm_runtime_set_autosuspend_delay(ethosudev->base.dev, 50);
  247. pm_runtime_use_autosuspend(ethosudev->base.dev);
  248. ret = devm_pm_runtime_set_active_enabled(ethosudev->base.dev);
  249. if (ret)
  250. return ret;
  251. pm_runtime_get_noresume(ethosudev->base.dev);
  252. ethosudev->npu_info.id = id = readl_relaxed(ethosudev->regs + NPU_REG_ID);
  253. ethosudev->npu_info.config = config = readl_relaxed(ethosudev->regs + NPU_REG_CONFIG);
  254. ethosu_sram_init(ethosudev);
  255. dev_info(ethosudev->base.dev,
  256. "Ethos-U NPU, arch v%ld.%ld.%ld, rev r%ldp%ld, cmd stream ver%ld, %d MACs, %dKB SRAM\n",
  257. FIELD_GET(ID_ARCH_MAJOR_MASK, id),
  258. FIELD_GET(ID_ARCH_MINOR_MASK, id),
  259. FIELD_GET(ID_ARCH_PATCH_MASK, id),
  260. FIELD_GET(ID_VER_MAJOR_MASK, id),
  261. FIELD_GET(ID_VER_MINOR_MASK, id),
  262. FIELD_GET(CONFIG_CMD_STREAM_VER_MASK, config),
  263. 1 << FIELD_GET(CONFIG_MACS_PER_CC_MASK, config),
  264. ethosudev->npu_info.sram_size / 1024);
  265. return 0;
  266. }
  267. static int ethosu_probe(struct platform_device *pdev)
  268. {
  269. int ret;
  270. struct ethosu_device *ethosudev;
  271. ethosudev = devm_drm_dev_alloc(&pdev->dev, &ethosu_drm_driver,
  272. struct ethosu_device, base);
  273. if (IS_ERR(ethosudev))
  274. return -ENOMEM;
  275. platform_set_drvdata(pdev, ethosudev);
  276. dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40));
  277. ethosudev->regs = devm_platform_ioremap_resource(pdev, 0);
  278. ethosudev->num_clks = devm_clk_bulk_get_all(&pdev->dev, &ethosudev->clks);
  279. if (ethosudev->num_clks < 0)
  280. return ethosudev->num_clks;
  281. ret = ethosu_job_init(ethosudev);
  282. if (ret)
  283. return ret;
  284. ret = ethosu_init(ethosudev);
  285. if (ret)
  286. return ret;
  287. ret = drm_dev_register(&ethosudev->base, 0);
  288. if (ret)
  289. pm_runtime_dont_use_autosuspend(ethosudev->base.dev);
  290. pm_runtime_put_autosuspend(ethosudev->base.dev);
  291. return ret;
  292. }
  293. static void ethosu_remove(struct platform_device *pdev)
  294. {
  295. struct ethosu_device *ethosudev = dev_get_drvdata(&pdev->dev);
  296. drm_dev_unregister(&ethosudev->base);
  297. ethosu_job_fini(ethosudev);
  298. if (ethosudev->sram)
  299. gen_pool_free(ethosudev->srampool, (unsigned long)ethosudev->sram,
  300. ethosudev->npu_info.sram_size);
  301. }
  302. static const struct of_device_id dt_match[] = {
  303. { .compatible = "arm,ethos-u65" },
  304. { .compatible = "arm,ethos-u85" },
  305. {}
  306. };
  307. MODULE_DEVICE_TABLE(of, dt_match);
  308. static DEFINE_RUNTIME_DEV_PM_OPS(ethosu_pm_ops,
  309. ethosu_device_suspend,
  310. ethosu_device_resume,
  311. NULL);
  312. static struct platform_driver ethosu_driver = {
  313. .probe = ethosu_probe,
  314. .remove = ethosu_remove,
  315. .driver = {
  316. .name = "ethosu",
  317. .pm = pm_ptr(&ethosu_pm_ops),
  318. .of_match_table = dt_match,
  319. },
  320. };
  321. module_platform_driver(ethosu_driver);
  322. MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
  323. MODULE_DESCRIPTION("Arm Ethos-U Accel Driver");
  324. MODULE_LICENSE("Dual MIT/GPL");