amdxdna_ctx.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
  4. */
  5. #include <drm/amdxdna_accel.h>
  6. #include <drm/drm_device.h>
  7. #include <drm/drm_drv.h>
  8. #include <drm/drm_file.h>
  9. #include <drm/drm_gem.h>
  10. #include <drm/drm_gem_shmem_helper.h>
  11. #include <drm/drm_print.h>
  12. #include <drm/gpu_scheduler.h>
  13. #include <linux/xarray.h>
  14. #include <trace/events/amdxdna.h>
  15. #include "amdxdna_ctx.h"
  16. #include "amdxdna_gem.h"
  17. #include "amdxdna_pci_drv.h"
  18. #include "amdxdna_pm.h"
  19. #define MAX_HWCTX_ID 255
  20. #define MAX_ARG_COUNT 4095
  21. struct amdxdna_fence {
  22. struct dma_fence base;
  23. spinlock_t lock; /* for base */
  24. struct amdxdna_hwctx *hwctx;
  25. };
  26. static const char *amdxdna_fence_get_driver_name(struct dma_fence *fence)
  27. {
  28. return KBUILD_MODNAME;
  29. }
  30. static const char *amdxdna_fence_get_timeline_name(struct dma_fence *fence)
  31. {
  32. struct amdxdna_fence *xdna_fence;
  33. xdna_fence = container_of(fence, struct amdxdna_fence, base);
  34. return xdna_fence->hwctx->name;
  35. }
  36. static const struct dma_fence_ops fence_ops = {
  37. .get_driver_name = amdxdna_fence_get_driver_name,
  38. .get_timeline_name = amdxdna_fence_get_timeline_name,
  39. };
  40. static struct dma_fence *amdxdna_fence_create(struct amdxdna_hwctx *hwctx)
  41. {
  42. struct amdxdna_fence *fence;
  43. fence = kzalloc_obj(*fence);
  44. if (!fence)
  45. return NULL;
  46. fence->hwctx = hwctx;
  47. spin_lock_init(&fence->lock);
  48. dma_fence_init(&fence->base, &fence_ops, &fence->lock, hwctx->id, 0);
  49. return &fence->base;
  50. }
  51. static void amdxdna_hwctx_destroy_rcu(struct amdxdna_hwctx *hwctx,
  52. struct srcu_struct *ss)
  53. {
  54. struct amdxdna_dev *xdna = hwctx->client->xdna;
  55. synchronize_srcu(ss);
  56. /* At this point, user is not able to submit new commands */
  57. xdna->dev_info->ops->hwctx_fini(hwctx);
  58. kfree(hwctx->name);
  59. kfree(hwctx);
  60. }
  61. int amdxdna_hwctx_walk(struct amdxdna_client *client, void *arg,
  62. int (*walk)(struct amdxdna_hwctx *hwctx, void *arg))
  63. {
  64. struct amdxdna_hwctx *hwctx;
  65. unsigned long hwctx_id;
  66. int ret = 0, idx;
  67. idx = srcu_read_lock(&client->hwctx_srcu);
  68. amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
  69. ret = walk(hwctx, arg);
  70. if (ret)
  71. break;
  72. }
  73. srcu_read_unlock(&client->hwctx_srcu, idx);
  74. return ret;
  75. }
  76. void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size)
  77. {
  78. struct amdxdna_cmd *cmd = abo->mem.kva;
  79. u32 num_masks, count;
  80. if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
  81. num_masks = 0;
  82. else
  83. num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
  84. if (size) {
  85. count = FIELD_GET(AMDXDNA_CMD_COUNT, cmd->header);
  86. if (unlikely(count <= num_masks ||
  87. count * sizeof(u32) +
  88. offsetof(struct amdxdna_cmd, data[0]) >
  89. abo->mem.size)) {
  90. *size = 0;
  91. return NULL;
  92. }
  93. *size = (count - num_masks) * sizeof(u32);
  94. }
  95. return &cmd->data[num_masks];
  96. }
  97. u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
  98. {
  99. struct amdxdna_cmd *cmd = abo->mem.kva;
  100. u32 num_masks, i;
  101. u32 *cu_mask;
  102. if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
  103. return INVALID_CU_IDX;
  104. num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
  105. cu_mask = cmd->data;
  106. for (i = 0; i < num_masks; i++) {
  107. if (cu_mask[i])
  108. return ffs(cu_mask[i]) - 1;
  109. }
  110. return INVALID_CU_IDX;
  111. }
  112. int amdxdna_cmd_set_error(struct amdxdna_gem_obj *abo,
  113. struct amdxdna_sched_job *job, u32 cmd_idx,
  114. enum ert_cmd_state error_state)
  115. {
  116. struct amdxdna_client *client = job->hwctx->client;
  117. struct amdxdna_cmd *cmd = abo->mem.kva;
  118. struct amdxdna_cmd_chain *cc = NULL;
  119. cmd->header &= ~AMDXDNA_CMD_STATE;
  120. cmd->header |= FIELD_PREP(AMDXDNA_CMD_STATE, error_state);
  121. if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN) {
  122. cc = amdxdna_cmd_get_payload(abo, NULL);
  123. cc->error_index = (cmd_idx < cc->command_count) ? cmd_idx : 0;
  124. abo = amdxdna_gem_get_obj(client, cc->data[0], AMDXDNA_BO_CMD);
  125. if (!abo)
  126. return -EINVAL;
  127. cmd = abo->mem.kva;
  128. }
  129. memset(cmd->data, 0xff, abo->mem.size - sizeof(*cmd));
  130. if (cc)
  131. amdxdna_gem_put_obj(abo);
  132. return 0;
  133. }
  134. /*
  135. * This should be called in close() and remove(). DO NOT call in other syscalls.
  136. * This guarantee that when hwctx and resources will be released, if user
  137. * doesn't call amdxdna_drm_destroy_hwctx_ioctl.
  138. */
  139. void amdxdna_hwctx_remove_all(struct amdxdna_client *client)
  140. {
  141. struct amdxdna_hwctx *hwctx;
  142. unsigned long hwctx_id;
  143. amdxdna_for_each_hwctx(client, hwctx_id, hwctx) {
  144. XDNA_DBG(client->xdna, "PID %d close HW context %d",
  145. client->pid, hwctx->id);
  146. xa_erase(&client->hwctx_xa, hwctx->id);
  147. amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu);
  148. }
  149. }
  150. int amdxdna_drm_create_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  151. {
  152. struct amdxdna_client *client = filp->driver_priv;
  153. struct amdxdna_drm_create_hwctx *args = data;
  154. struct amdxdna_dev *xdna = to_xdna_dev(dev);
  155. struct amdxdna_hwctx *hwctx;
  156. int ret, idx;
  157. if (args->ext || args->ext_flags)
  158. return -EINVAL;
  159. hwctx = kzalloc_obj(*hwctx);
  160. if (!hwctx)
  161. return -ENOMEM;
  162. if (copy_from_user(&hwctx->qos, u64_to_user_ptr(args->qos_p), sizeof(hwctx->qos))) {
  163. XDNA_ERR(xdna, "Access QoS info failed");
  164. kfree(hwctx);
  165. return -EFAULT;
  166. }
  167. hwctx->client = client;
  168. hwctx->fw_ctx_id = -1;
  169. hwctx->num_tiles = args->num_tiles;
  170. hwctx->mem_size = args->mem_size;
  171. hwctx->max_opc = args->max_opc;
  172. guard(mutex)(&xdna->dev_lock);
  173. if (!drm_dev_enter(dev, &idx)) {
  174. ret = -ENODEV;
  175. goto free_hwctx;
  176. }
  177. ret = xdna->dev_info->ops->hwctx_init(hwctx);
  178. if (ret) {
  179. XDNA_ERR(xdna, "Init hwctx failed, ret %d", ret);
  180. goto dev_exit;
  181. }
  182. hwctx->name = kasprintf(GFP_KERNEL, "hwctx.%d.%d", client->pid, hwctx->fw_ctx_id);
  183. if (!hwctx->name) {
  184. ret = -ENOMEM;
  185. goto fini_hwctx;
  186. }
  187. ret = xa_alloc_cyclic(&client->hwctx_xa, &hwctx->id, hwctx,
  188. XA_LIMIT(AMDXDNA_INVALID_CTX_HANDLE + 1, MAX_HWCTX_ID),
  189. &client->next_hwctxid, GFP_KERNEL);
  190. if (ret < 0) {
  191. XDNA_ERR(xdna, "Allocate hwctx ID failed, ret %d", ret);
  192. goto free_name;
  193. }
  194. args->handle = hwctx->id;
  195. args->syncobj_handle = hwctx->syncobj_hdl;
  196. atomic64_set(&hwctx->job_submit_cnt, 0);
  197. atomic64_set(&hwctx->job_free_cnt, 0);
  198. XDNA_DBG(xdna, "PID %d create HW context %d, ret %d", client->pid, args->handle, ret);
  199. drm_dev_exit(idx);
  200. return 0;
  201. free_name:
  202. kfree(hwctx->name);
  203. fini_hwctx:
  204. xdna->dev_info->ops->hwctx_fini(hwctx);
  205. dev_exit:
  206. drm_dev_exit(idx);
  207. free_hwctx:
  208. kfree(hwctx);
  209. return ret;
  210. }
  211. int amdxdna_drm_destroy_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  212. {
  213. struct amdxdna_client *client = filp->driver_priv;
  214. struct amdxdna_drm_destroy_hwctx *args = data;
  215. struct amdxdna_dev *xdna = to_xdna_dev(dev);
  216. struct amdxdna_hwctx *hwctx;
  217. int ret = 0, idx;
  218. if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad)))
  219. return -EINVAL;
  220. if (!drm_dev_enter(dev, &idx))
  221. return -ENODEV;
  222. mutex_lock(&xdna->dev_lock);
  223. hwctx = xa_erase(&client->hwctx_xa, args->handle);
  224. if (!hwctx) {
  225. ret = -EINVAL;
  226. XDNA_DBG(xdna, "PID %d HW context %d not exist",
  227. client->pid, args->handle);
  228. goto out;
  229. }
  230. /*
  231. * The pushed jobs are handled by DRM scheduler during destroy.
  232. * SRCU to synchronize with exec command ioctls.
  233. */
  234. amdxdna_hwctx_destroy_rcu(hwctx, &client->hwctx_srcu);
  235. XDNA_DBG(xdna, "PID %d destroyed HW context %d", client->pid, args->handle);
  236. out:
  237. mutex_unlock(&xdna->dev_lock);
  238. drm_dev_exit(idx);
  239. return ret;
  240. }
  241. int amdxdna_drm_config_hwctx_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  242. {
  243. struct amdxdna_client *client = filp->driver_priv;
  244. struct amdxdna_drm_config_hwctx *args = data;
  245. struct amdxdna_dev *xdna = to_xdna_dev(dev);
  246. struct amdxdna_hwctx *hwctx;
  247. u32 buf_size;
  248. void *buf;
  249. int ret;
  250. u64 val;
  251. if (XDNA_MBZ_DBG(xdna, &args->pad, sizeof(args->pad)))
  252. return -EINVAL;
  253. if (!xdna->dev_info->ops->hwctx_config)
  254. return -EOPNOTSUPP;
  255. val = args->param_val;
  256. buf_size = args->param_val_size;
  257. switch (args->param_type) {
  258. case DRM_AMDXDNA_HWCTX_CONFIG_CU:
  259. /* For those types that param_val is pointer */
  260. if (buf_size > PAGE_SIZE) {
  261. XDNA_ERR(xdna, "Config CU param buffer too large");
  262. return -E2BIG;
  263. }
  264. /* Hwctx needs to keep buf */
  265. buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
  266. if (!buf)
  267. return -ENOMEM;
  268. if (copy_from_user(buf, u64_to_user_ptr(val), buf_size)) {
  269. kfree(buf);
  270. return -EFAULT;
  271. }
  272. break;
  273. case DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF:
  274. case DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF:
  275. /* For those types that param_val is a value */
  276. buf = NULL;
  277. buf_size = 0;
  278. break;
  279. default:
  280. XDNA_DBG(xdna, "Unknown HW context config type %d", args->param_type);
  281. return -EINVAL;
  282. }
  283. guard(mutex)(&xdna->dev_lock);
  284. hwctx = xa_load(&client->hwctx_xa, args->handle);
  285. if (!hwctx) {
  286. XDNA_DBG(xdna, "PID %d failed to get hwctx %d", client->pid, args->handle);
  287. ret = -EINVAL;
  288. goto free_buf;
  289. }
  290. ret = xdna->dev_info->ops->hwctx_config(hwctx, args->param_type, val, buf, buf_size);
  291. free_buf:
  292. kfree(buf);
  293. return ret;
  294. }
  295. int amdxdna_hwctx_sync_debug_bo(struct amdxdna_client *client, u32 debug_bo_hdl)
  296. {
  297. struct amdxdna_dev *xdna = client->xdna;
  298. struct amdxdna_hwctx *hwctx;
  299. struct amdxdna_gem_obj *abo;
  300. struct drm_gem_object *gobj;
  301. int ret;
  302. if (!xdna->dev_info->ops->hwctx_sync_debug_bo)
  303. return -EOPNOTSUPP;
  304. gobj = drm_gem_object_lookup(client->filp, debug_bo_hdl);
  305. if (!gobj)
  306. return -EINVAL;
  307. abo = to_xdna_obj(gobj);
  308. guard(mutex)(&xdna->dev_lock);
  309. hwctx = xa_load(&client->hwctx_xa, abo->assigned_hwctx);
  310. if (!hwctx) {
  311. ret = -EINVAL;
  312. goto put_obj;
  313. }
  314. ret = xdna->dev_info->ops->hwctx_sync_debug_bo(hwctx, debug_bo_hdl);
  315. put_obj:
  316. drm_gem_object_put(gobj);
  317. return ret;
  318. }
  319. static void
  320. amdxdna_arg_bos_put(struct amdxdna_sched_job *job)
  321. {
  322. int i;
  323. for (i = 0; i < job->bo_cnt; i++) {
  324. if (!job->bos[i])
  325. break;
  326. drm_gem_object_put(job->bos[i]);
  327. }
  328. }
  329. static int
  330. amdxdna_arg_bos_lookup(struct amdxdna_client *client,
  331. struct amdxdna_sched_job *job,
  332. u32 *bo_hdls, u32 bo_cnt)
  333. {
  334. struct drm_gem_object *gobj;
  335. int i, ret;
  336. job->bo_cnt = bo_cnt;
  337. for (i = 0; i < job->bo_cnt; i++) {
  338. struct amdxdna_gem_obj *abo;
  339. gobj = drm_gem_object_lookup(client->filp, bo_hdls[i]);
  340. if (!gobj) {
  341. ret = -ENOENT;
  342. goto put_shmem_bo;
  343. }
  344. abo = to_xdna_obj(gobj);
  345. mutex_lock(&abo->lock);
  346. if (abo->pinned) {
  347. mutex_unlock(&abo->lock);
  348. job->bos[i] = gobj;
  349. continue;
  350. }
  351. ret = amdxdna_gem_pin_nolock(abo);
  352. if (ret) {
  353. mutex_unlock(&abo->lock);
  354. drm_gem_object_put(gobj);
  355. goto put_shmem_bo;
  356. }
  357. abo->pinned = true;
  358. mutex_unlock(&abo->lock);
  359. job->bos[i] = gobj;
  360. }
  361. return 0;
  362. put_shmem_bo:
  363. amdxdna_arg_bos_put(job);
  364. return ret;
  365. }
  366. void amdxdna_sched_job_cleanup(struct amdxdna_sched_job *job)
  367. {
  368. trace_amdxdna_debug_point(job->hwctx->name, job->seq, "job release");
  369. amdxdna_pm_suspend_put(job->hwctx->client->xdna);
  370. amdxdna_arg_bos_put(job);
  371. amdxdna_gem_put_obj(job->cmd_bo);
  372. dma_fence_put(job->fence);
  373. }
  374. int amdxdna_cmd_submit(struct amdxdna_client *client,
  375. struct amdxdna_drv_cmd *drv_cmd,
  376. u32 cmd_bo_hdl, u32 *arg_bo_hdls, u32 arg_bo_cnt,
  377. u32 hwctx_hdl, u64 *seq)
  378. {
  379. struct amdxdna_dev *xdna = client->xdna;
  380. struct amdxdna_sched_job *job;
  381. struct amdxdna_hwctx *hwctx;
  382. int ret, idx;
  383. XDNA_DBG(xdna, "Command BO hdl %d, Arg BO count %d", cmd_bo_hdl, arg_bo_cnt);
  384. job = kzalloc_flex(*job, bos, arg_bo_cnt);
  385. if (!job)
  386. return -ENOMEM;
  387. job->drv_cmd = drv_cmd;
  388. if (cmd_bo_hdl != AMDXDNA_INVALID_BO_HANDLE) {
  389. job->cmd_bo = amdxdna_gem_get_obj(client, cmd_bo_hdl, AMDXDNA_BO_CMD);
  390. if (!job->cmd_bo) {
  391. XDNA_ERR(xdna, "Failed to get cmd bo from %d", cmd_bo_hdl);
  392. ret = -EINVAL;
  393. goto free_job;
  394. }
  395. }
  396. ret = amdxdna_arg_bos_lookup(client, job, arg_bo_hdls, arg_bo_cnt);
  397. if (ret) {
  398. XDNA_ERR(xdna, "Argument BOs lookup failed, ret %d", ret);
  399. goto cmd_put;
  400. }
  401. ret = amdxdna_pm_resume_get(xdna);
  402. if (ret) {
  403. XDNA_ERR(xdna, "Resume failed, ret %d", ret);
  404. goto put_bos;
  405. }
  406. idx = srcu_read_lock(&client->hwctx_srcu);
  407. hwctx = xa_load(&client->hwctx_xa, hwctx_hdl);
  408. if (!hwctx) {
  409. XDNA_DBG(xdna, "PID %d failed to get hwctx %d",
  410. client->pid, hwctx_hdl);
  411. ret = -EINVAL;
  412. goto unlock_srcu;
  413. }
  414. job->hwctx = hwctx;
  415. job->mm = current->mm;
  416. job->fence = amdxdna_fence_create(hwctx);
  417. if (!job->fence) {
  418. XDNA_ERR(xdna, "Failed to create fence");
  419. ret = -ENOMEM;
  420. goto unlock_srcu;
  421. }
  422. kref_init(&job->refcnt);
  423. ret = xdna->dev_info->ops->cmd_submit(hwctx, job, seq);
  424. if (ret)
  425. goto put_fence;
  426. /*
  427. * The amdxdna_hwctx_destroy_rcu() will release hwctx and associated
  428. * resource after synchronize_srcu(). The submitted jobs should be
  429. * handled by the queue, for example DRM scheduler, in device layer.
  430. * For here we can unlock SRCU.
  431. */
  432. srcu_read_unlock(&client->hwctx_srcu, idx);
  433. trace_amdxdna_debug_point(hwctx->name, *seq, "job pushed");
  434. return 0;
  435. put_fence:
  436. dma_fence_put(job->fence);
  437. unlock_srcu:
  438. srcu_read_unlock(&client->hwctx_srcu, idx);
  439. amdxdna_pm_suspend_put(xdna);
  440. put_bos:
  441. amdxdna_arg_bos_put(job);
  442. cmd_put:
  443. amdxdna_gem_put_obj(job->cmd_bo);
  444. free_job:
  445. kfree(job);
  446. return ret;
  447. }
  448. /*
  449. * The submit command ioctl submits a command to firmware. One firmware command
  450. * may contain multiple command BOs for processing as a whole.
  451. * The command sequence number is returned which can be used for wait command ioctl.
  452. */
  453. static int amdxdna_drm_submit_execbuf(struct amdxdna_client *client,
  454. struct amdxdna_drm_exec_cmd *args)
  455. {
  456. struct amdxdna_dev *xdna = client->xdna;
  457. u32 *arg_bo_hdls = NULL;
  458. u32 cmd_bo_hdl;
  459. int ret;
  460. if (args->arg_count > MAX_ARG_COUNT) {
  461. XDNA_ERR(xdna, "Invalid arg bo count %d", args->arg_count);
  462. return -EINVAL;
  463. }
  464. /* Only support single command for now. */
  465. if (args->cmd_count != 1) {
  466. XDNA_ERR(xdna, "Invalid cmd bo count %d", args->cmd_count);
  467. return -EINVAL;
  468. }
  469. cmd_bo_hdl = (u32)args->cmd_handles;
  470. if (args->arg_count) {
  471. arg_bo_hdls = kcalloc(args->arg_count, sizeof(u32), GFP_KERNEL);
  472. if (!arg_bo_hdls)
  473. return -ENOMEM;
  474. ret = copy_from_user(arg_bo_hdls, u64_to_user_ptr(args->args),
  475. args->arg_count * sizeof(u32));
  476. if (ret) {
  477. ret = -EFAULT;
  478. goto free_cmd_bo_hdls;
  479. }
  480. }
  481. ret = amdxdna_cmd_submit(client, NULL, cmd_bo_hdl, arg_bo_hdls,
  482. args->arg_count, args->hwctx, &args->seq);
  483. if (ret)
  484. XDNA_DBG(xdna, "Submit cmds failed, ret %d", ret);
  485. free_cmd_bo_hdls:
  486. kfree(arg_bo_hdls);
  487. if (!ret)
  488. XDNA_DBG(xdna, "Pushed cmd %lld to scheduler", args->seq);
  489. return ret;
  490. }
  491. int amdxdna_drm_submit_cmd_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  492. {
  493. struct amdxdna_client *client = filp->driver_priv;
  494. struct amdxdna_drm_exec_cmd *args = data;
  495. if (args->ext || args->ext_flags)
  496. return -EINVAL;
  497. switch (args->type) {
  498. case AMDXDNA_CMD_SUBMIT_EXEC_BUF:
  499. return amdxdna_drm_submit_execbuf(client, args);
  500. }
  501. XDNA_ERR(client->xdna, "Invalid command type %d", args->type);
  502. return -EINVAL;
  503. }