platform.c 12 KB

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  1. /*
  2. * Platform device support for Au1x00 SoCs.
  3. *
  4. * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  5. *
  6. * (C) Copyright Embedded Alley Solutions, Inc 2005
  7. * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/serial_8250.h>
  19. #include <linux/slab.h>
  20. #include <linux/usb/ehci_pdriver.h>
  21. #include <linux/usb/ohci_pdriver.h>
  22. #include <asm/mach-au1x00/au1000.h>
  23. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  24. #include <asm/mach-au1x00/au1100_mmc.h>
  25. #include <asm/mach-au1x00/au1xxx_eth.h>
  26. #include <prom.h>
  27. static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
  28. unsigned int old_state)
  29. {
  30. #ifdef CONFIG_SERIAL_8250
  31. switch (state) {
  32. case 0:
  33. alchemy_uart_enable(CPHYSADDR(port->membase));
  34. serial8250_do_pm(port, state, old_state);
  35. break;
  36. case 3: /* power off */
  37. serial8250_do_pm(port, state, old_state);
  38. alchemy_uart_disable(CPHYSADDR(port->membase));
  39. break;
  40. default:
  41. serial8250_do_pm(port, state, old_state);
  42. break;
  43. }
  44. #endif
  45. }
  46. #define PORT(_base, _irq) \
  47. { \
  48. .mapbase = _base, \
  49. .mapsize = 0x1000, \
  50. .irq = _irq, \
  51. .regshift = 2, \
  52. .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
  53. UPF_FIXED_TYPE, \
  54. .type = PORT_16550A, \
  55. .pm = alchemy_8250_pm, \
  56. }
  57. static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
  58. [ALCHEMY_CPU_AU1000] = {
  59. PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
  60. PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
  61. PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
  62. PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
  63. },
  64. [ALCHEMY_CPU_AU1500] = {
  65. PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
  66. PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
  67. },
  68. [ALCHEMY_CPU_AU1100] = {
  69. PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
  70. PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
  71. PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
  72. },
  73. [ALCHEMY_CPU_AU1550] = {
  74. PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
  75. PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
  76. PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
  77. },
  78. [ALCHEMY_CPU_AU1200] = {
  79. PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
  80. PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
  81. },
  82. [ALCHEMY_CPU_AU1300] = {
  83. PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
  84. PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
  85. PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
  86. PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
  87. },
  88. };
  89. static struct platform_device au1xx0_uart_device = {
  90. .name = "serial8250",
  91. .id = PLAT8250_DEV_AU1X00,
  92. };
  93. static void __init alchemy_setup_uarts(int ctype)
  94. {
  95. long uartclk;
  96. int s = sizeof(struct plat_serial8250_port);
  97. int c = alchemy_get_uarts(ctype);
  98. struct plat_serial8250_port *ports;
  99. struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
  100. if (IS_ERR(clk))
  101. return;
  102. if (clk_prepare_enable(clk)) {
  103. clk_put(clk);
  104. return;
  105. }
  106. uartclk = clk_get_rate(clk);
  107. clk_put(clk);
  108. ports = kcalloc(s, (c + 1), GFP_KERNEL);
  109. if (!ports) {
  110. printk(KERN_INFO "Alchemy: no memory for UART data\n");
  111. return;
  112. }
  113. memcpy(ports, au1x00_uart_data[ctype], s * c);
  114. au1xx0_uart_device.dev.platform_data = ports;
  115. /* Fill up uartclk. */
  116. for (s = 0; s < c; s++) {
  117. ports[s].uartclk = uartclk;
  118. if (au_platform_setup(&ports[s]) < 0) {
  119. kfree(ports);
  120. printk(KERN_INFO "Alchemy: missing support for UARTs\n");
  121. return;
  122. }
  123. }
  124. if (platform_device_register(&au1xx0_uart_device))
  125. printk(KERN_INFO "Alchemy: failed to register UARTs\n");
  126. }
  127. static u64 alchemy_all_dmamask = DMA_BIT_MASK(32);
  128. /* Power on callback for the ehci platform driver */
  129. static int alchemy_ehci_power_on(struct platform_device *pdev)
  130. {
  131. return alchemy_usb_control(ALCHEMY_USB_EHCI0, 1);
  132. }
  133. /* Power off/suspend callback for the ehci platform driver */
  134. static void alchemy_ehci_power_off(struct platform_device *pdev)
  135. {
  136. alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
  137. }
  138. static struct usb_ehci_pdata alchemy_ehci_pdata = {
  139. .no_io_watchdog = 1,
  140. .power_on = alchemy_ehci_power_on,
  141. .power_off = alchemy_ehci_power_off,
  142. .power_suspend = alchemy_ehci_power_off,
  143. };
  144. /* Power on callback for the ohci platform driver */
  145. static int alchemy_ohci_power_on(struct platform_device *pdev)
  146. {
  147. int unit;
  148. unit = (pdev->id == 1) ?
  149. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  150. return alchemy_usb_control(unit, 1);
  151. }
  152. /* Power off/suspend callback for the ohci platform driver */
  153. static void alchemy_ohci_power_off(struct platform_device *pdev)
  154. {
  155. int unit;
  156. unit = (pdev->id == 1) ?
  157. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  158. alchemy_usb_control(unit, 0);
  159. }
  160. static struct usb_ohci_pdata alchemy_ohci_pdata = {
  161. .power_on = alchemy_ohci_power_on,
  162. .power_off = alchemy_ohci_power_off,
  163. .power_suspend = alchemy_ohci_power_off,
  164. };
  165. static unsigned long alchemy_ohci_data[][2] __initdata = {
  166. [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
  167. [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
  168. [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
  169. [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
  170. [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
  171. [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
  172. };
  173. static unsigned long alchemy_ehci_data[][2] __initdata = {
  174. [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
  175. [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
  176. };
  177. static int __init _new_usbres(struct resource **r, struct platform_device **d)
  178. {
  179. *r = kzalloc_objs(struct resource, 2);
  180. if (!*r)
  181. return -ENOMEM;
  182. *d = kzalloc_obj(struct platform_device);
  183. if (!*d) {
  184. kfree(*r);
  185. return -ENOMEM;
  186. }
  187. (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  188. (*d)->num_resources = 2;
  189. (*d)->resource = *r;
  190. return 0;
  191. }
  192. static void __init alchemy_setup_usb(int ctype)
  193. {
  194. struct resource *res;
  195. struct platform_device *pdev;
  196. /* setup OHCI0. Every variant has one */
  197. if (_new_usbres(&res, &pdev))
  198. return;
  199. res[0].start = alchemy_ohci_data[ctype][0];
  200. res[0].end = res[0].start + 0x100 - 1;
  201. res[0].flags = IORESOURCE_MEM;
  202. res[1].start = alchemy_ohci_data[ctype][1];
  203. res[1].end = res[1].start;
  204. res[1].flags = IORESOURCE_IRQ;
  205. pdev->name = "ohci-platform";
  206. pdev->id = 0;
  207. pdev->dev.dma_mask = &alchemy_all_dmamask;
  208. pdev->dev.platform_data = &alchemy_ohci_pdata;
  209. if (platform_device_register(pdev))
  210. printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
  211. /* setup EHCI0: Au1200/Au1300 */
  212. if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
  213. if (_new_usbres(&res, &pdev))
  214. return;
  215. res[0].start = alchemy_ehci_data[ctype][0];
  216. res[0].end = res[0].start + 0x100 - 1;
  217. res[0].flags = IORESOURCE_MEM;
  218. res[1].start = alchemy_ehci_data[ctype][1];
  219. res[1].end = res[1].start;
  220. res[1].flags = IORESOURCE_IRQ;
  221. pdev->name = "ehci-platform";
  222. pdev->id = 0;
  223. pdev->dev.dma_mask = &alchemy_all_dmamask;
  224. pdev->dev.platform_data = &alchemy_ehci_pdata;
  225. if (platform_device_register(pdev))
  226. printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
  227. }
  228. /* Au1300: OHCI1 */
  229. if (ctype == ALCHEMY_CPU_AU1300) {
  230. if (_new_usbres(&res, &pdev))
  231. return;
  232. res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
  233. res[0].end = res[0].start + 0x100 - 1;
  234. res[0].flags = IORESOURCE_MEM;
  235. res[1].start = AU1300_USB_INT;
  236. res[1].end = res[1].start;
  237. res[1].flags = IORESOURCE_IRQ;
  238. pdev->name = "ohci-platform";
  239. pdev->id = 1;
  240. pdev->dev.dma_mask = &alchemy_all_dmamask;
  241. pdev->dev.platform_data = &alchemy_ohci_pdata;
  242. if (platform_device_register(pdev))
  243. printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
  244. }
  245. }
  246. /* Macro to help defining the Ethernet MAC resources */
  247. #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
  248. #define MAC_RES(_base, _enable, _irq, _macdma) \
  249. { \
  250. .start = _base, \
  251. .end = _base + 0xffff, \
  252. .flags = IORESOURCE_MEM, \
  253. }, \
  254. { \
  255. .start = _enable, \
  256. .end = _enable + 0x3, \
  257. .flags = IORESOURCE_MEM, \
  258. }, \
  259. { \
  260. .start = _irq, \
  261. .end = _irq, \
  262. .flags = IORESOURCE_IRQ \
  263. }, \
  264. { \
  265. .start = _macdma, \
  266. .end = _macdma + 0x1ff, \
  267. .flags = IORESOURCE_MEM, \
  268. }
  269. static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
  270. [ALCHEMY_CPU_AU1000] = {
  271. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  272. AU1000_MACEN_PHYS_ADDR,
  273. AU1000_MAC0_DMA_INT,
  274. AU1000_MACDMA0_PHYS_ADDR)
  275. },
  276. [ALCHEMY_CPU_AU1500] = {
  277. MAC_RES(AU1500_MAC0_PHYS_ADDR,
  278. AU1500_MACEN_PHYS_ADDR,
  279. AU1500_MAC0_DMA_INT,
  280. AU1000_MACDMA0_PHYS_ADDR)
  281. },
  282. [ALCHEMY_CPU_AU1100] = {
  283. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  284. AU1000_MACEN_PHYS_ADDR,
  285. AU1100_MAC0_DMA_INT,
  286. AU1000_MACDMA0_PHYS_ADDR)
  287. },
  288. [ALCHEMY_CPU_AU1550] = {
  289. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  290. AU1000_MACEN_PHYS_ADDR,
  291. AU1550_MAC0_DMA_INT,
  292. AU1000_MACDMA0_PHYS_ADDR)
  293. },
  294. };
  295. static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
  296. .phy1_search_mac0 = 1,
  297. };
  298. static struct platform_device au1xxx_eth0_device = {
  299. .name = "au1000-eth",
  300. .id = 0,
  301. .num_resources = MAC_RES_COUNT,
  302. .dev = {
  303. .dma_mask = &alchemy_all_dmamask,
  304. .coherent_dma_mask = DMA_BIT_MASK(32),
  305. .platform_data = &au1xxx_eth0_platform_data,
  306. },
  307. };
  308. static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
  309. [ALCHEMY_CPU_AU1000] = {
  310. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  311. AU1000_MACEN_PHYS_ADDR + 4,
  312. AU1000_MAC1_DMA_INT,
  313. AU1000_MACDMA1_PHYS_ADDR)
  314. },
  315. [ALCHEMY_CPU_AU1500] = {
  316. MAC_RES(AU1500_MAC1_PHYS_ADDR,
  317. AU1500_MACEN_PHYS_ADDR + 4,
  318. AU1500_MAC1_DMA_INT,
  319. AU1000_MACDMA1_PHYS_ADDR)
  320. },
  321. [ALCHEMY_CPU_AU1550] = {
  322. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  323. AU1000_MACEN_PHYS_ADDR + 4,
  324. AU1550_MAC1_DMA_INT,
  325. AU1000_MACDMA1_PHYS_ADDR)
  326. },
  327. };
  328. static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
  329. .phy1_search_mac0 = 1,
  330. };
  331. static struct platform_device au1xxx_eth1_device = {
  332. .name = "au1000-eth",
  333. .id = 1,
  334. .num_resources = MAC_RES_COUNT,
  335. .dev = {
  336. .dma_mask = &alchemy_all_dmamask,
  337. .coherent_dma_mask = DMA_BIT_MASK(32),
  338. .platform_data = &au1xxx_eth1_platform_data,
  339. },
  340. };
  341. void __init au1xxx_override_eth_cfg(unsigned int port,
  342. struct au1000_eth_platform_data *eth_data)
  343. {
  344. if (!eth_data || port > 1)
  345. return;
  346. if (port == 0)
  347. memcpy(&au1xxx_eth0_platform_data, eth_data,
  348. sizeof(struct au1000_eth_platform_data));
  349. else
  350. memcpy(&au1xxx_eth1_platform_data, eth_data,
  351. sizeof(struct au1000_eth_platform_data));
  352. }
  353. static void __init alchemy_setup_macs(int ctype)
  354. {
  355. int ret, i;
  356. unsigned char ethaddr[6];
  357. struct resource *macres;
  358. /* Handle 1st MAC */
  359. if (alchemy_get_macs(ctype) < 1)
  360. return;
  361. macres = kmemdup_array(au1xxx_eth0_resources[ctype], MAC_RES_COUNT,
  362. sizeof(*macres), GFP_KERNEL);
  363. if (!macres) {
  364. printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
  365. return;
  366. }
  367. au1xxx_eth0_device.resource = macres;
  368. i = prom_get_ethernet_addr(ethaddr);
  369. if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
  370. memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
  371. ret = platform_device_register(&au1xxx_eth0_device);
  372. if (ret)
  373. printk(KERN_INFO "Alchemy: failed to register MAC0\n");
  374. /* Handle 2nd MAC */
  375. if (alchemy_get_macs(ctype) < 2)
  376. return;
  377. macres = kmemdup_array(au1xxx_eth1_resources[ctype], MAC_RES_COUNT,
  378. sizeof(*macres), GFP_KERNEL);
  379. if (!macres) {
  380. printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
  381. return;
  382. }
  383. au1xxx_eth1_device.resource = macres;
  384. ethaddr[5] += 1; /* next addr for 2nd MAC */
  385. if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
  386. memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
  387. /* Register second MAC if enabled in pinfunc */
  388. if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) {
  389. ret = platform_device_register(&au1xxx_eth1_device);
  390. if (ret)
  391. printk(KERN_INFO "Alchemy: failed to register MAC1\n");
  392. }
  393. }
  394. static int __init au1xxx_platform_init(void)
  395. {
  396. int ctype = alchemy_get_cputype();
  397. alchemy_setup_uarts(ctype);
  398. alchemy_setup_macs(ctype);
  399. alchemy_setup_usb(ctype);
  400. return 0;
  401. }
  402. arch_initcall(au1xxx_platform_init);