addrspace.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4. *
  5. * Derived from MIPS:
  6. * Copyright (C) 1996, 99 Ralf Baechle
  7. * Copyright (C) 2000, 2002 Maciej W. Rozycki
  8. * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  9. */
  10. #ifndef _ASM_ADDRSPACE_H
  11. #define _ASM_ADDRSPACE_H
  12. #include <linux/const.h>
  13. #include <linux/sizes.h>
  14. #include <asm/loongarch.h>
  15. /*
  16. * This gives the physical RAM offset.
  17. */
  18. #ifndef __ASSEMBLER__
  19. #ifndef PHYS_OFFSET
  20. #define PHYS_OFFSET _UL(0)
  21. #endif
  22. extern unsigned long vm_map_base;
  23. #endif /* __ASSEMBLER__ */
  24. #ifndef IO_BASE
  25. #define IO_BASE CSR_DMW0_BASE
  26. #endif
  27. #ifndef CACHE_BASE
  28. #define CACHE_BASE CSR_DMW1_BASE
  29. #endif
  30. #ifndef UNCACHE_BASE
  31. #define UNCACHE_BASE CSR_DMW0_BASE
  32. #endif
  33. #ifndef WRITECOMBINE_BASE
  34. #ifdef CONFIG_32BIT
  35. #define WRITECOMBINE_BASE CSR_DMW0_BASE
  36. #else
  37. #define WRITECOMBINE_BASE CSR_DMW2_BASE
  38. #endif
  39. #endif
  40. #ifdef CONFIG_32BIT
  41. #define DMW_PABITS 29
  42. #define TO_PHYS_MASK ((_UL(1) << _UL(DMW_PABITS)) - 1)
  43. #else
  44. #define DMW_PABITS 48
  45. #define TO_PHYS_MASK ((_ULL(1) << _ULL(DMW_PABITS)) - 1)
  46. #endif
  47. /*
  48. * Memory above this physical address will be considered highmem.
  49. */
  50. #ifndef HIGHMEM_START
  51. #define HIGHMEM_START (_UL(1) << _UL(DMW_PABITS))
  52. #endif
  53. #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
  54. #define TO_CACHE(x) (CACHE_BASE | ((x) & TO_PHYS_MASK))
  55. #define TO_UNCACHE(x) (UNCACHE_BASE | ((x) & TO_PHYS_MASK))
  56. /*
  57. * This handles the memory map.
  58. */
  59. #ifndef PAGE_OFFSET
  60. #define PAGE_OFFSET (CACHE_BASE + PHYS_OFFSET)
  61. #endif
  62. #ifndef FIXADDR_TOP
  63. #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000)
  64. #endif
  65. #ifdef __ASSEMBLER__
  66. #define _ATYPE_
  67. #define _ATYPE32_
  68. #define _ATYPE64_
  69. #else
  70. #define _ATYPE_ __PTRDIFF_TYPE__
  71. #define _ATYPE32_ int
  72. #define _ATYPE64_ __s64
  73. #endif
  74. #ifdef CONFIG_64BIT
  75. #define _CONST64_(x) _UL(x)
  76. #else
  77. #define _CONST64_(x) _ULL(x)
  78. #endif
  79. /*
  80. * 32/64-bit LoongArch address spaces
  81. */
  82. #ifdef __ASSEMBLER__
  83. #define _ACAST32_
  84. #define _ACAST64_
  85. #else
  86. #define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
  87. #define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
  88. #endif
  89. #ifdef CONFIG_32BIT
  90. #define UVRANGE 0x00000000
  91. #define KPRANGE0 0x80000000
  92. #define KPRANGE1 0xa0000000
  93. #define KVRANGE 0xc0000000
  94. #else
  95. #define XUVRANGE _CONST64_(0x0000000000000000)
  96. #define XSPRANGE _CONST64_(0x4000000000000000)
  97. #define XKPRANGE _CONST64_(0x8000000000000000)
  98. #define XKVRANGE _CONST64_(0xc000000000000000)
  99. #endif
  100. /*
  101. * Returns the physical address of a KPRANGEx / XKPRANGE address
  102. */
  103. #ifdef CONFIG_32BIT
  104. #define PHYSADDR(a) ((_ACAST32_(a)) & TO_PHYS_MASK)
  105. #else
  106. #define PHYSADDR(a) ((_ACAST64_(a)) & TO_PHYS_MASK)
  107. #endif
  108. /*
  109. * On LoongArch, I/O ports mappring is following:
  110. *
  111. * | .... |
  112. * |-----------------------|
  113. * | pci io ports(16K~32M) |
  114. * |-----------------------|
  115. * | isa io ports(0 ~16K) |
  116. * PCI_IOBASE ->|-----------------------|
  117. * | .... |
  118. */
  119. #define PCI_IOBASE ((void __iomem *)(vm_map_base + (2 * PAGE_SIZE)))
  120. #define PCI_IOSIZE SZ_32M
  121. #define ISA_IOSIZE SZ_16K
  122. #define IO_SPACE_LIMIT (PCI_IOSIZE - 1)
  123. #define PHYS_LINK_KADDR PHYSADDR(VMLINUX_LOAD_ADDRESS)
  124. #endif /* _ASM_ADDRSPACE_H */