fpsimd.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (C) 2012 ARM Ltd.
  4. */
  5. #ifndef __ASM_FP_H
  6. #define __ASM_FP_H
  7. #include <asm/errno.h>
  8. #include <asm/percpu.h>
  9. #include <asm/ptrace.h>
  10. #include <asm/processor.h>
  11. #include <asm/sigcontext.h>
  12. #include <asm/sysreg.h>
  13. #ifndef __ASSEMBLER__
  14. #include <linux/bitmap.h>
  15. #include <linux/build_bug.h>
  16. #include <linux/bug.h>
  17. #include <linux/cache.h>
  18. #include <linux/init.h>
  19. #include <linux/stddef.h>
  20. #include <linux/types.h>
  21. /* Masks for extracting the FPSR and FPCR from the FPSCR */
  22. #define VFP_FPSCR_STAT_MASK 0xf800009f
  23. #define VFP_FPSCR_CTRL_MASK 0x07f79f00
  24. /*
  25. * The VFP state has 32x64-bit registers and a single 32-bit
  26. * control/status register.
  27. */
  28. #define VFP_STATE_SIZE ((32 * 8) + 4)
  29. static inline unsigned long cpacr_save_enable_kernel_sve(void)
  30. {
  31. unsigned long old = read_sysreg(cpacr_el1);
  32. unsigned long set = CPACR_EL1_FPEN_EL1EN | CPACR_EL1_ZEN_EL1EN;
  33. write_sysreg(old | set, cpacr_el1);
  34. isb();
  35. return old;
  36. }
  37. static inline unsigned long cpacr_save_enable_kernel_sme(void)
  38. {
  39. unsigned long old = read_sysreg(cpacr_el1);
  40. unsigned long set = CPACR_EL1_FPEN_EL1EN | CPACR_EL1_SMEN_EL1EN;
  41. write_sysreg(old | set, cpacr_el1);
  42. isb();
  43. return old;
  44. }
  45. static inline void cpacr_restore(unsigned long cpacr)
  46. {
  47. write_sysreg(cpacr, cpacr_el1);
  48. isb();
  49. }
  50. /*
  51. * When we defined the maximum SVE vector length we defined the ABI so
  52. * that the maximum vector length included all the reserved for future
  53. * expansion bits in ZCR rather than those just currently defined by
  54. * the architecture. Using this length to allocate worst size buffers
  55. * results in excessively large allocations, and this effect is even
  56. * more pronounced for SME due to ZA. Define more suitable VLs for
  57. * these situations.
  58. */
  59. #define ARCH_SVE_VQ_MAX ((ZCR_ELx_LEN_MASK >> ZCR_ELx_LEN_SHIFT) + 1)
  60. #define SME_VQ_MAX ((SMCR_ELx_LEN_MASK >> SMCR_ELx_LEN_SHIFT) + 1)
  61. struct task_struct;
  62. extern void fpsimd_save_state(struct user_fpsimd_state *state);
  63. extern void fpsimd_load_state(struct user_fpsimd_state *state);
  64. extern void fpsimd_thread_switch(struct task_struct *next);
  65. extern void fpsimd_flush_thread(void);
  66. extern void fpsimd_preserve_current_state(void);
  67. extern void fpsimd_restore_current_state(void);
  68. extern void fpsimd_update_current_state(struct user_fpsimd_state const *state);
  69. struct cpu_fp_state {
  70. struct user_fpsimd_state *st;
  71. void *sve_state;
  72. void *sme_state;
  73. u64 *svcr;
  74. u64 *fpmr;
  75. unsigned int sve_vl;
  76. unsigned int sme_vl;
  77. enum fp_type *fp_type;
  78. enum fp_type to_save;
  79. };
  80. DECLARE_PER_CPU(struct cpu_fp_state, fpsimd_last_state);
  81. extern void fpsimd_bind_state_to_cpu(struct cpu_fp_state *fp_state);
  82. extern void fpsimd_flush_task_state(struct task_struct *target);
  83. extern void fpsimd_save_and_flush_current_state(void);
  84. extern void fpsimd_save_and_flush_cpu_state(void);
  85. static inline bool thread_sm_enabled(struct thread_struct *thread)
  86. {
  87. return system_supports_sme() && (thread->svcr & SVCR_SM_MASK);
  88. }
  89. static inline bool thread_za_enabled(struct thread_struct *thread)
  90. {
  91. return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK);
  92. }
  93. extern void task_smstop_sm(struct task_struct *task);
  94. /* Maximum VL that SVE/SME VL-agnostic software can transparently support */
  95. #define VL_ARCH_MAX 0x100
  96. /* Offset of FFR in the SVE register dump */
  97. static inline size_t sve_ffr_offset(int vl)
  98. {
  99. return SVE_SIG_FFR_OFFSET(sve_vq_from_vl(vl)) - SVE_SIG_REGS_OFFSET;
  100. }
  101. static inline void *sve_pffr(struct thread_struct *thread)
  102. {
  103. unsigned int vl;
  104. if (system_supports_sme() && thread_sm_enabled(thread))
  105. vl = thread_get_sme_vl(thread);
  106. else
  107. vl = thread_get_sve_vl(thread);
  108. return (char *)thread->sve_state + sve_ffr_offset(vl);
  109. }
  110. static inline void *thread_zt_state(struct thread_struct *thread)
  111. {
  112. /* The ZT register state is stored immediately after the ZA state */
  113. unsigned int sme_vq = sve_vq_from_vl(thread_get_sme_vl(thread));
  114. return thread->sme_state + ZA_SIG_REGS_SIZE(sme_vq);
  115. }
  116. extern void sve_save_state(void *state, u32 *pfpsr, int save_ffr);
  117. extern void sve_load_state(void const *state, u32 const *pfpsr,
  118. int restore_ffr);
  119. extern void sve_flush_live(bool flush_ffr, unsigned long vq_minus_1);
  120. extern unsigned int sve_get_vl(void);
  121. extern void sve_set_vq(unsigned long vq_minus_1);
  122. extern void sme_set_vq(unsigned long vq_minus_1);
  123. extern void sme_save_state(void *state, int zt);
  124. extern void sme_load_state(void const *state, int zt);
  125. struct arm64_cpu_capabilities;
  126. extern void cpu_enable_fpsimd(const struct arm64_cpu_capabilities *__unused);
  127. extern void cpu_enable_sve(const struct arm64_cpu_capabilities *__unused);
  128. extern void cpu_enable_sme(const struct arm64_cpu_capabilities *__unused);
  129. extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused);
  130. extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused);
  131. extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused);
  132. /*
  133. * Helpers to translate bit indices in sve_vq_map to VQ values (and
  134. * vice versa). This allows find_next_bit() to be used to find the
  135. * _maximum_ VQ not exceeding a certain value.
  136. */
  137. static inline unsigned int __vq_to_bit(unsigned int vq)
  138. {
  139. return SVE_VQ_MAX - vq;
  140. }
  141. static inline unsigned int __bit_to_vq(unsigned int bit)
  142. {
  143. return SVE_VQ_MAX - bit;
  144. }
  145. struct vl_info {
  146. enum vec_type type;
  147. const char *name; /* For display purposes */
  148. /* Minimum supported vector length across all CPUs */
  149. int min_vl;
  150. /* Maximum supported vector length across all CPUs */
  151. int max_vl;
  152. int max_virtualisable_vl;
  153. /*
  154. * Set of available vector lengths,
  155. * where length vq encoded as bit __vq_to_bit(vq):
  156. */
  157. DECLARE_BITMAP(vq_map, SVE_VQ_MAX);
  158. /* Set of vector lengths present on at least one cpu: */
  159. DECLARE_BITMAP(vq_partial_map, SVE_VQ_MAX);
  160. };
  161. #ifdef CONFIG_ARM64_SVE
  162. extern void sve_alloc(struct task_struct *task, bool flush);
  163. extern void fpsimd_release_task(struct task_struct *task);
  164. extern void fpsimd_sync_from_effective_state(struct task_struct *task);
  165. extern void fpsimd_sync_to_effective_state_zeropad(struct task_struct *task);
  166. extern int vec_set_vector_length(struct task_struct *task, enum vec_type type,
  167. unsigned long vl, unsigned long flags);
  168. extern int sve_set_current_vl(unsigned long arg);
  169. extern int sve_get_current_vl(void);
  170. static inline void sve_user_disable(void)
  171. {
  172. sysreg_clear_set(cpacr_el1, CPACR_EL1_ZEN_EL0EN, 0);
  173. }
  174. static inline void sve_user_enable(void)
  175. {
  176. sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_ZEN_EL0EN);
  177. }
  178. #define sve_cond_update_zcr_vq(val, reg) \
  179. do { \
  180. u64 __zcr = read_sysreg_s((reg)); \
  181. u64 __new = __zcr & ~ZCR_ELx_LEN_MASK; \
  182. __new |= (val) & ZCR_ELx_LEN_MASK; \
  183. if (__zcr != __new) \
  184. write_sysreg_s(__new, (reg)); \
  185. } while (0)
  186. /*
  187. * Probing and setup functions.
  188. * Calls to these functions must be serialised with one another.
  189. */
  190. enum vec_type;
  191. extern void __init vec_init_vq_map(enum vec_type type);
  192. extern void vec_update_vq_map(enum vec_type type);
  193. extern int vec_verify_vq_map(enum vec_type type);
  194. extern void __init sve_setup(void);
  195. extern __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX];
  196. static inline void write_vl(enum vec_type type, u64 val)
  197. {
  198. u64 tmp;
  199. switch (type) {
  200. #ifdef CONFIG_ARM64_SVE
  201. case ARM64_VEC_SVE:
  202. tmp = read_sysreg_s(SYS_ZCR_EL1) & ~ZCR_ELx_LEN_MASK;
  203. write_sysreg_s(tmp | val, SYS_ZCR_EL1);
  204. break;
  205. #endif
  206. #ifdef CONFIG_ARM64_SME
  207. case ARM64_VEC_SME:
  208. tmp = read_sysreg_s(SYS_SMCR_EL1) & ~SMCR_ELx_LEN_MASK;
  209. write_sysreg_s(tmp | val, SYS_SMCR_EL1);
  210. break;
  211. #endif
  212. default:
  213. WARN_ON_ONCE(1);
  214. break;
  215. }
  216. }
  217. static inline int vec_max_vl(enum vec_type type)
  218. {
  219. return vl_info[type].max_vl;
  220. }
  221. static inline int vec_max_virtualisable_vl(enum vec_type type)
  222. {
  223. return vl_info[type].max_virtualisable_vl;
  224. }
  225. static inline int sve_max_vl(void)
  226. {
  227. return vec_max_vl(ARM64_VEC_SVE);
  228. }
  229. static inline int sve_max_virtualisable_vl(void)
  230. {
  231. return vec_max_virtualisable_vl(ARM64_VEC_SVE);
  232. }
  233. /* Ensure vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX before calling this function */
  234. static inline bool vq_available(enum vec_type type, unsigned int vq)
  235. {
  236. return test_bit(__vq_to_bit(vq), vl_info[type].vq_map);
  237. }
  238. static inline bool sve_vq_available(unsigned int vq)
  239. {
  240. return vq_available(ARM64_VEC_SVE, vq);
  241. }
  242. static inline size_t __sve_state_size(unsigned int sve_vl, unsigned int sme_vl)
  243. {
  244. unsigned int vl = max(sve_vl, sme_vl);
  245. return SVE_SIG_REGS_SIZE(sve_vq_from_vl(vl));
  246. }
  247. /*
  248. * Return how many bytes of memory are required to store the full SVE
  249. * state for task, given task's currently configured vector length.
  250. */
  251. static inline size_t sve_state_size(struct task_struct const *task)
  252. {
  253. unsigned int sve_vl = task_get_sve_vl(task);
  254. unsigned int sme_vl = task_get_sme_vl(task);
  255. return __sve_state_size(sve_vl, sme_vl);
  256. }
  257. #else /* ! CONFIG_ARM64_SVE */
  258. static inline void sve_alloc(struct task_struct *task, bool flush) { }
  259. static inline void fpsimd_release_task(struct task_struct *task) { }
  260. static inline void fpsimd_sync_from_effective_state(struct task_struct *task) { }
  261. static inline void fpsimd_sync_to_effective_state_zeropad(struct task_struct *task) { }
  262. static inline int sve_max_virtualisable_vl(void)
  263. {
  264. return 0;
  265. }
  266. static inline int sve_set_current_vl(unsigned long arg)
  267. {
  268. return -EINVAL;
  269. }
  270. static inline int sve_get_current_vl(void)
  271. {
  272. return -EINVAL;
  273. }
  274. static inline int sve_max_vl(void)
  275. {
  276. return -EINVAL;
  277. }
  278. static inline bool sve_vq_available(unsigned int vq) { return false; }
  279. static inline void sve_user_disable(void) { BUILD_BUG(); }
  280. static inline void sve_user_enable(void) { BUILD_BUG(); }
  281. #define sve_cond_update_zcr_vq(val, reg) do { } while (0)
  282. static inline void vec_init_vq_map(enum vec_type t) { }
  283. static inline void vec_update_vq_map(enum vec_type t) { }
  284. static inline int vec_verify_vq_map(enum vec_type t) { return 0; }
  285. static inline void sve_setup(void) { }
  286. static inline size_t __sve_state_size(unsigned int sve_vl, unsigned int sme_vl)
  287. {
  288. return 0;
  289. }
  290. static inline size_t sve_state_size(struct task_struct const *task)
  291. {
  292. return 0;
  293. }
  294. #endif /* ! CONFIG_ARM64_SVE */
  295. #ifdef CONFIG_ARM64_SME
  296. static inline void sme_user_disable(void)
  297. {
  298. sysreg_clear_set(cpacr_el1, CPACR_EL1_SMEN_EL0EN, 0);
  299. }
  300. static inline void sme_user_enable(void)
  301. {
  302. sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_SMEN_EL0EN);
  303. }
  304. static inline void sme_smstart_sm(void)
  305. {
  306. asm volatile(__msr_s(SYS_SVCR_SMSTART_SM_EL0, "xzr"));
  307. }
  308. static inline void sme_smstop_sm(void)
  309. {
  310. asm volatile(__msr_s(SYS_SVCR_SMSTOP_SM_EL0, "xzr"));
  311. }
  312. static inline void sme_smstop(void)
  313. {
  314. asm volatile(__msr_s(SYS_SVCR_SMSTOP_SMZA_EL0, "xzr"));
  315. }
  316. extern void __init sme_setup(void);
  317. static inline int sme_max_vl(void)
  318. {
  319. return vec_max_vl(ARM64_VEC_SME);
  320. }
  321. static inline int sme_max_virtualisable_vl(void)
  322. {
  323. return vec_max_virtualisable_vl(ARM64_VEC_SME);
  324. }
  325. extern void sme_alloc(struct task_struct *task, bool flush);
  326. extern unsigned int sme_get_vl(void);
  327. extern int sme_set_current_vl(unsigned long arg);
  328. extern int sme_get_current_vl(void);
  329. extern void sme_suspend_exit(void);
  330. static inline size_t __sme_state_size(unsigned int sme_vl)
  331. {
  332. size_t size = ZA_SIG_REGS_SIZE(sve_vq_from_vl(sme_vl));
  333. if (system_supports_sme2())
  334. size += ZT_SIG_REG_SIZE;
  335. return size;
  336. }
  337. /*
  338. * Return how many bytes of memory are required to store the full SME
  339. * specific state for task, given task's currently configured vector
  340. * length.
  341. */
  342. static inline size_t sme_state_size(struct task_struct const *task)
  343. {
  344. return __sme_state_size(task_get_sme_vl(task));
  345. }
  346. #else
  347. static inline void sme_user_disable(void) { BUILD_BUG(); }
  348. static inline void sme_user_enable(void) { BUILD_BUG(); }
  349. static inline void sme_smstart_sm(void) { }
  350. static inline void sme_smstop_sm(void) { }
  351. static inline void sme_smstop(void) { }
  352. static inline void sme_alloc(struct task_struct *task, bool flush) { }
  353. static inline void sme_setup(void) { }
  354. static inline unsigned int sme_get_vl(void) { return 0; }
  355. static inline int sme_max_vl(void) { return 0; }
  356. static inline int sme_max_virtualisable_vl(void) { return 0; }
  357. static inline int sme_set_current_vl(unsigned long arg) { return -EINVAL; }
  358. static inline int sme_get_current_vl(void) { return -EINVAL; }
  359. static inline void sme_suspend_exit(void) { }
  360. static inline size_t __sme_state_size(unsigned int sme_vl)
  361. {
  362. return 0;
  363. }
  364. static inline size_t sme_state_size(struct task_struct const *task)
  365. {
  366. return 0;
  367. }
  368. #endif /* ! CONFIG_ARM64_SME */
  369. /* For use by EFI runtime services calls only */
  370. extern void __efi_fpsimd_begin(void);
  371. extern void __efi_fpsimd_end(void);
  372. #endif
  373. #endif