ARK-OS/arkos/kernel/arch/arm64/boot/dts/mediatek/mt8183.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (c) 2018 MediaTek Inc.
 * Author: Ben Ho <ben.ho@mediatek.com>
 *	   Erin Lo <erin.lo@mediatek.com>
 */

#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8183-larb-port.h>
#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset/mt8183-resets.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/pinctrl/mt8183-pinfunc.h>

/ {
	compatible = "mediatek,mt8183";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c7;
		i2c8 = &i2c8;
		i2c9 = &i2c9;
		i2c10 = &i2c10;
		i2c11 = &i2c11;
		ovl0 = &ovl0;
		ovl-2l0 = &ovl_2l0;
		ovl-2l1 = &ovl_2l1;
		rdma0 = &rdma0;
		rdma1 = &rdma1;
	};

	cluster0_opp: opp-table-cluster0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp0-793000000 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <650000>;
			required-opps = <&opp2_00>;
		};
		opp0-910000000 {
			opp-hz = /bits/ 64 <910000000>;
			opp-microvolt = <687500>;
			required-opps = <&opp2_01>;
		};
		opp0-1014000000 {
			opp-hz = /bits/ 64 <1014000000>;
			opp-microvolt = <718750>;
			required-opps = <&opp2_02>;
		};
		opp0-1131000000 {
			opp-hz = /bits/ 64 <1131000000>;
			opp-microvolt = <756250>;
			required-opps = <&opp2_03>;
		};
		opp0-1248000000 {
			opp-hz = /bits/ 64 <1248000000>;
			opp-microvolt = <800000>;
			required-opps = <&opp2_04>;
		};
		opp0-1326000000 {
			opp-hz = /bits/ 64 <1326000000>;
			opp-microvolt = <818750>;
			required-opps = <&opp2_05>;
		};
		opp0-1417000000 {
			opp-hz = /bits/ 64 <1417000000>;
			opp-microvolt = <850000>;
			required-opps = <&opp2_06>;
		};
		opp0-1508000000 {
			opp-hz = /bits/ 64 <1508000000>;
			opp-microvolt = <868750>;
			required-opps = <&opp2_07>;
		};
		opp0-1586000000 {
			opp-hz = /bits/ 64 <1586000000>;
			opp-microvolt = <893750>;
			required-opps = <&opp2_08>;
		};
		opp0-1625000000 {
			opp-hz = /bits/ 64 <1625000000>;
			opp-microvolt = <906250>;
			required-opps = <&opp2_09>;
		};
		opp0-1677000000 {
			opp-hz = /bits/ 64 <1677000000>;
			opp-microvolt = <931250>;
			required-opps = <&opp2_10>;
		};
		opp0-1716000000 {
			opp-hz = /bits/ 64 <1716000000>;
			opp-microvolt = <943750>;
			required-opps = <&opp2_11>;
		};
		opp0-1781000000 {
			opp-hz = /bits/ 64 <1781000000>;
			opp-microvolt = <975000>;
			required-opps = <&opp2_12>;
		};
		opp0-1846000000 {
			opp-hz = /bits/ 64 <1846000000>;
			opp-microvolt = <1000000>;
			required-opps = <&opp2_13>;
		};
		opp0-1924000000 {
			opp-hz = /bits/ 64 <1924000000>;
			opp-microvolt = <1025000>;
			required-opps = <&opp2_14>;
		};
		opp0-1989000000 {
			opp-hz = /bits/ 64 <1989000000>;
			opp-microvolt = <1050000>;
			required-opps = <&opp2_15>;
		};	};

	cluster1_opp: opp-table-cluster1 {
		compatible = "operating-points-v2";
		opp-shared;
		opp1-793000000 {
			opp-hz = /bits/ 64 <793000000>;
			opp-microvolt = <700000>;
			required-opps = <&opp2_00>;
		};
		opp1-910000000 {
			opp-hz = /bits/ 64 <910000000>;
			opp-microvolt = <725000>;
			required-opps = <&opp2_01>;
		};
		opp1-1014000000 {
			opp-hz = /bits/ 64 <1014000000>;
			opp-microvolt = <750000>;
			required-opps = <&opp2_02>;
		};
		opp1-1131000000 {
			opp-hz = /bits/ 64 <1131000000>;
			opp-microvolt = <775000>;
			required-opps = <&opp2_03>;
		};
		opp1-1248000000 {
			opp-hz = /bits/ 64 <1248000000>;
			opp-microvolt = <800000>;
			required-opps = <&opp2_04>;
		};
		opp1-1326000000 {
			opp-hz = /bits/ 64 <1326000000>;
			opp-microvolt = <825000>;
			required-opps = <&opp2_05>;
		};
		opp1-1417000000 {
			opp-hz = /bits/ 64 <1417000000>;
			opp-microvolt = <850000>;
			required-opps = <&opp2_06>;
		};
		opp1-1508000000 {
			opp-hz = /bits/ 64 <1508000000>;
			opp-microvolt = <875000>;
			required-opps = <&opp2_07>;
		};
		opp1-1586000000 {
			opp-hz = /bits/ 64 <1586000000>;
			opp-microvolt = <900000>;
			required-opps = <&opp2_08>;
		};
		opp1-1625000000 {
			opp-hz = /bits/ 64 <1625000000>;
			opp-microvolt = <912500>;
			required-opps = <&opp2_09>;
		};
		opp1-1677000000 {
			opp-hz = /bits/ 64 <1677000000>;
			opp-microvolt = <931250>;
			required-opps = <&opp2_10>;
		};
		opp1-1716000000 {
			opp-hz = /bits/ 64 <1716000000>;
			opp-microvolt = <950000>;
			required-opps = <&opp2_11>;
		};
		opp1-1781000000 {
			opp-hz = /bits/ 64 <1781000000>;
			opp-microvolt = <975000>;
			required-opps = <&opp2_12>;
		};
		opp1-1846000000 {
			opp-hz = /bits/ 64 <1846000000>;
			opp-microvolt = <1000000>;
			required-opps = <&opp2_13>;
		};
		opp1-1924000000 {
			opp-hz = /bits/ 64 <1924000000>;
			opp-microvolt = <1025000>;
			required-opps = <&opp2_14>;
		};
		opp1-1989000000 {
			opp-hz = /bits/ 64 <1989000000>;
			opp-microvolt = <1050000>;
			required-opps = <&opp2_15>;
		};
	};

	cci_opp: opp-table-cci {
		compatible = "operating-points-v2";
		opp-shared;
		opp2_00: opp-273000000 {
			opp-hz = /bits/ 64 <273000000>;
			opp-microvolt = <650000>;
		};
		opp2_01: opp-338000000 {
			opp-hz = /bits/ 64 <338000000>;
			opp-microvolt = <687500>;
		};
		opp2_02: opp-403000000 {
			opp-hz = /bits/ 64 <403000000>;
			opp-microvolt = <718750>;
		};
		opp2_03: opp-463000000 {
			opp-hz = /bits/ 64 <463000000>;
			opp-microvolt = <756250>;
		};
		opp2_04: opp-546000000 {
			opp-hz = /bits/ 64 <546000000>;
			opp-microvolt = <800000>;
		};
		opp2_05: opp-624000000 {
			opp-hz = /bits/ 64 <624000000>;
			opp-microvolt = <818750>;
		};
		opp2_06: opp-689000000 {
			opp-hz = /bits/ 64 <689000000>;
			opp-microvolt = <850000>;
		};
		opp2_07: opp-767000000 {
			opp-hz = /bits/ 64 <767000000>;
			opp-microvolt = <868750>;
		};
		opp2_08: opp-845000000 {
			opp-hz = /bits/ 64 <845000000>;
			opp-microvolt = <893750>;
		};
		opp2_09: opp-871000000 {
			opp-hz = /bits/ 64 <871000000>;
			opp-microvolt = <906250>;
		};
		opp2_10: opp-923000000 {
			opp-hz = /bits/ 64 <923000000>;
			opp-microvolt = <931250>;
		};
		opp2_11: opp-962000000 {
			opp-hz = /bits/ 64 <962000000>;
			opp-microvolt = <943750>;
		};
		opp2_12: opp-1027000000 {
			opp-hz = /bits/ 64 <1027000000>;
			opp-microvolt = <975000>;
		};
		opp2_13: opp-1092000000 {
			opp-hz = /bits/ 64 <1092000000>;
			opp-microvolt = <1000000>;
		};
		opp2_14: opp-1144000000 {
			opp-hz = /bits/ 64 <1144000000>;
			opp-microvolt = <1025000>;
		};
		opp2_15: opp-1196000000 {
			opp-hz = /bits/ 64 <1196000000>;
			opp-microvolt = <1050000>;
		};
	};

	cci: cci {
		compatible = "mediatek,mt8183-cci";
		clocks = <&mcucfg CLK_MCU_BUS_SEL>,
			 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
		clock-names = "cci", "intermediate";
		operating-points-v2 = <&cci_opp>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <84>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <84>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <84>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			enable-method = "psci";
			capacity-dmips-mhz = <741>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>;
			clocks = <&mcucfg CLK_MCU_MP0_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <84>;
			i-cache-size = <32768>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <32768>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&l2_0>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			dynamic-power-coefficient = <211>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x101>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			dynamic-power-coefficient = <211>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x102>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			dynamic-power-coefficient = <211>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		cpu7: cpu@103 {
			device_type = "cpu";
			compatible = "arm,cortex-a73";
			reg = <0x103>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>;
			clocks = <&mcucfg CLK_MCU_MP2_SEL>,
				 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
			clock-names = "cpu", "intermediate";
			operating-points-v2 = <&cluster1_opp>;
			dynamic-power-coefficient = <211>;
			i-cache-size = <65536>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <65536>;
			d-cache-line-size = <64>;
			d-cache-sets = <256>;
			next-level-cache = <&l2_1>;
			#cooling-cells = <2>;
			mediatek,cci = <&cci>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP: cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x00010001>;
				entry-latency-us = <200>;
				exit-latency-us = <200>;
				min-residency-us = <800>;
			};

			CLUSTER_SLEEP0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <250>;
				exit-latency-us = <400>;
				min-residency-us = <1000>;
			};
			CLUSTER_SLEEP1: cluster-sleep-1 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <250>;
				exit-latency-us = <400>;
				min-residency-us = <1300>;
			};
		};

		l2_0: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-unified;
		};

		l2_1: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-size = <1048576>;
			cache-line-size = <64>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	gpu_opp_table: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-microvolt = <625000>;
		};

		opp-320000000 {
			opp-hz = /bits/ 64 <320000000>;
			opp-microvolt = <631250>;
		};

		opp-340000000 {
			opp-hz = /bits/ 64 <340000000>;
			opp-microvolt = <637500>;
		};

		opp-360000000 {
			opp-hz = /bits/ 64 <360000000>;
			opp-microvolt = <643750>;
		};

		opp-380000000 {
			opp-hz = /bits/ 64 <380000000>;
			opp-microvolt = <650000>;
		};

		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			opp-microvolt = <656250>;
		};

		opp-420000000 {
			opp-hz = /bits/ 64 <420000000>;
			opp-microvolt = <662500>;
		};

		opp-460000000 {
			opp-hz = /bits/ 64 <460000000>;
			opp-microvolt = <675000>;
		};

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <687500>;
		};

		opp-540000000 {
			opp-hz = /bits/ 64 <540000000>;
			opp-microvolt = <700000>;
		};

		opp-580000000 {
			opp-hz = /bits/ 64 <580000000>;
			opp-microvolt = <712500>;
		};

		opp-620000000 {
			opp-hz = /bits/ 64 <620000000>;
			opp-microvolt = <725000>;
		};

		opp-653000000 {
			opp-hz = /bits/ 64 <653000000>;
			opp-microvolt = <743750>;
		};

		opp-698000000 {
			opp-hz = /bits/ 64 <698000000>;
			opp-microvolt = <768750>;
		};

		opp-743000000 {
			opp-hz = /bits/ 64 <743000000>;
			opp-microvolt = <793750>;
		};

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <825000>;
		};
	};

	pmu-a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
	};

	pmu-a73 {
		compatible = "arm,cortex-a73-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clk13m: fixed-factor-clock-13m {
		compatible = "fixed-factor-clock";
		#clock-cells = <0>;
		clocks = <&clk26m>;
		clock-div = <2>;
		clock-mult = <1>;
		clock-output-names = "clk13m";
	};

	clk26m: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		soc_data: efuse@8000000 {
			compatible = "mediatek,mt8183-efuse",
				     "mediatek,efuse";
			reg = <0 0x08000000 0 0x0010>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";
		};

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <4>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
			      <0 0x0c100000 0 0x200000>, /* GICR */
			      <0 0x0c400000 0 0x2000>,   /* GICC */
			      <0 0x0c410000 0 0x1000>,   /* GICH */
			      <0 0x0c420000 0 0x2000>;   /* GICV */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
			ppi-partitions {
				ppi_cluster0: interrupt-partition-0 {
					affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
				};
				ppi_cluster1: interrupt-partition-1 {
					affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
				};
			};
		};

		mcucfg: syscon@c530000 {
			compatible = "mediatek,mt8183-mcucfg", "syscon";
			reg = <0 0x0c530000 0 0x1000>;
			#clock-cells = <1>;
		};

		sysirq: interrupt-controller@c530a80 {
			compatible = "mediatek,mt8183-sysirq",
				     "mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x0c530a80 0 0x50>;
		};

		cpu_debug0: cpu-debug@d410000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd410000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu0>;
		};

		cpu_debug1: cpu-debug@d510000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd510000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu1>;
		};

		cpu_debug2: cpu-debug@d610000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd610000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu2>;
		};

		cpu_debug3: cpu-debug@d710000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd710000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu3>;
		};

		cpu_debug4: cpu-debug@d810000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd810000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu4>;
		};

		cpu_debug5: cpu-debug@d910000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xd910000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu5>;
		};

		cpu_debug6: cpu-debug@da10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xda10000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu6>;
		};

		cpu_debug7: cpu-debug@db10000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x0 0xdb10000 0x0 0x1000>;
			clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
			clock-names = "apb_pclk";
			cpu = <&cpu7>;
		};

		topckgen: syscon@10000000 {
			compatible = "mediatek,mt8183-topckgen", "syscon";
			reg = <0 0x10000000 0 0x1000>;
			#clock-cells = <1>;
		};

		infracfg: syscon@10001000 {
			compatible = "mediatek,mt8183-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		pericfg: syscon@10003000 {
			compatible = "mediatek,mt8183-pericfg", "syscon";
			reg = <0 0x10003000 0 0x1000>;
			#clock-cells = <1>;
		};

		pio: pinctrl@10005000 {
			compatible = "mediatek,mt8183-pinctrl";
			reg = <0 0x10005000 0 0x1000>,
			      <0 0x11f20000 0 0x1000>,
			      <0 0x11e80000 0 0x1000>,
			      <0 0x11e70000 0 0x1000>,
			      <0 0x11e90000 0 0x1000>,
			      <0 0x11d30000 0 0x1000>,
			      <0 0x11d20000 0 0x1000>,
			      <0 0x11c50000 0 0x1000>,
			      <0 0x11f30000 0 0x1000>,
			      <0 0x1000b000 0 0x1000>;
			reg-names = "iocfg0", "iocfg1", "iocfg2",
				    "iocfg3", "iocfg4", "iocfg5",
				    "iocfg6", "iocfg7", "iocfg8",
				    "eint";
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pio 0 0 192>;
			interrupt-controller;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <2>;
		};

		scpsys: syscon@10006000 {
			compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
			reg = <0 0x10006000 0 0x1000>;

			/* System Power Manager */
			spm: power-controller {
				compatible = "mediatek,mt8183-power-controller";
				#address-cells = <1>;
				#size-cells = <0>;
				#power-domain-cells = <1>;

				/* power domain of the SoC */
				power-domain@MT8183_POWER_DOMAIN_AUDIO {
					reg = <MT8183_POWER_DOMAIN_AUDIO>;
					clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
						 <&infracfg CLK_INFRA_AUDIO>,
						 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>;
					clock-names = "audio", "audio1", "audio2";
					#power-domain-cells = <0>;
				};

				power-domain@MT8183_POWER_DOMAIN_CONN {
					reg = <MT8183_POWER_DOMAIN_CONN>;
					mediatek,infracfg = <&infracfg>;
					#power-domain-cells = <0>;
				};

				mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
					reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					mfg: power-domain@MT8183_POWER_DOMAIN_MFG {
						reg = <MT8183_POWER_DOMAIN_MFG>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 {
							reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 {
							reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_MFG_2D {
							reg = <MT8183_POWER_DOMAIN_MFG_2D>;
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};
					};
				};

				power-domain@MT8183_POWER_DOMAIN_DISP {
					reg = <MT8183_POWER_DOMAIN_DISP>;
					clocks = <&topckgen CLK_TOP_MUX_MM>,
						 <&mmsys CLK_MM_SMI_COMMON>,
						 <&mmsys CLK_MM_SMI_LARB0>,
						 <&mmsys CLK_MM_SMI_LARB1>,
						 <&mmsys CLK_MM_GALS_COMM0>,
						 <&mmsys CLK_MM_GALS_COMM1>,
						 <&mmsys CLK_MM_GALS_CCU2MM>,
						 <&mmsys CLK_MM_GALS_IPU12MM>,
						 <&mmsys CLK_MM_GALS_IMG2MM>,
						 <&mmsys CLK_MM_GALS_CAM2MM>,
						 <&mmsys CLK_MM_GALS_IPU2MM>;
					clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3",
						      "mm-4", "mm-5", "mm-6", "mm-7",
						      "mm-8", "mm-9";
					mediatek,infracfg = <&infracfg>;
					mediatek,smi = <&smi_common>;
					#address-cells = <1>;
					#size-cells = <0>;
					#power-domain-cells = <1>;

					power-domain@MT8183_POWER_DOMAIN_CAM {
						reg = <MT8183_POWER_DOMAIN_CAM>;
						clocks = <&topckgen CLK_TOP_MUX_CAM>,
							 <&camsys CLK_CAM_LARB6>,
							 <&camsys CLK_CAM_LARB3>,
							 <&camsys CLK_CAM_SENINF>,
							 <&camsys CLK_CAM_CAMSV0>,
							 <&camsys CLK_CAM_CAMSV1>,
							 <&camsys CLK_CAM_CAMSV2>,
							 <&camsys CLK_CAM_CCU>;
						clock-names = "cam", "cam-0", "cam-1",
							      "cam-2", "cam-3", "cam-4",
							      "cam-5", "cam-6";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_ISP {
						reg = <MT8183_POWER_DOMAIN_ISP>;
						clocks = <&topckgen CLK_TOP_MUX_IMG>,
							 <&imgsys CLK_IMG_LARB5>,
							 <&imgsys CLK_IMG_LARB2>;
						clock-names = "isp", "isp-0", "isp-1";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VDEC {
						reg = <MT8183_POWER_DOMAIN_VDEC>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VENC {
						reg = <MT8183_POWER_DOMAIN_VENC>;
						mediatek,smi = <&smi_common>;
						#power-domain-cells = <0>;
					};

					power-domain@MT8183_POWER_DOMAIN_VPU_TOP {
						reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
						clocks = <&topckgen CLK_TOP_MUX_IPU_IF>,
							 <&topckgen CLK_TOP_MUX_DSP>,
							 <&ipu_conn CLK_IPU_CONN_IPU>,
							 <&ipu_conn CLK_IPU_CONN_AHB>,
							 <&ipu_conn CLK_IPU_CONN_AXI>,
							 <&ipu_conn CLK_IPU_CONN_ISP>,
							 <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
							 <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
						clock-names = "vpu", "vpu1", "vpu-0", "vpu-1",
							      "vpu-2", "vpu-3", "vpu-4", "vpu-5";
						mediatek,infracfg = <&infracfg>;
						mediatek,smi = <&smi_common>;
						#address-cells = <1>;
						#size-cells = <0>;
						#power-domain-cells = <1>;

						power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 {
							reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
							clocks = <&topckgen CLK_TOP_MUX_DSP1>;
							clock-names = "vpu2";
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};

						power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 {
							reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
							clocks = <&topckgen CLK_TOP_MUX_DSP2>;
							clock-names = "vpu3";
							mediatek,infracfg = <&infracfg>;
							#power-domain-cells = <0>;
						};
					};
				};
			};
		};

		watchdog: watchdog@10007000 {
			compatible = "mediatek,mt8183-wdt";
			reg = <0 0x10007000 0 0x100>;
			#reset-cells = <1>;
		};

		apmixedsys: syscon@1000c000 {
			compatible = "mediatek,mt8183-apmixedsys", "syscon";
			reg = <0 0x1000c000 0 0x1000>;
			#clock-cells = <1>;
		};

		pwrap: pwrap@1000d000 {
			compatible = "mediatek,mt8183-pwrap";
			reg = <0 0x1000d000 0 0x1000>;
			reg-names = "pwrap";
			interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
				 <&infracfg CLK_INFRA_PMIC_AP>;
			clock-names = "spi", "wrap";
		};

		keyboard: keyboard@10010000 {
			compatible = "mediatek,mt8183-keypad",
				     "mediatek,mt6779-keypad";
			reg = <0 0x10010000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>;
			clocks = <&clk26m>;
			clock-names = "kpd";
			status = "disabled";
		};

		scp: scp@10500000 {
			compatible = "mediatek,mt8183-scp";
			reg = <0 0x10500000 0 0x80000>,
			      <0 0x105c0000 0 0x19080>;
			reg-names = "sram", "cfg";
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_SCPSYS>;
			clock-names = "main";
			memory-region = <&scp_mem_reserved>;
			status = "disabled";
		};

		systimer: timer@10017000 {
			compatible = "mediatek,mt8183-timer",
				     "mediatek,mt6765-timer";
			reg = <0 0x10017000 0 0x1000>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk13m>;
		};

		iommu: iommu@10205000 {
			compatible = "mediatek,mt8183-m4u";
			reg = <0 0x10205000 0 0x1000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
			mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>,
					 <&larb4>, <&larb5>, <&larb6>;
			#iommu-cells = <1>;
		};

		gce: mailbox@10238000 {
			compatible = "mediatek,mt8183-gce";
			reg = <0 0x10238000 0 0x4000>;
			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
			#mbox-cells = <2>;
			clocks = <&infracfg CLK_INFRA_GCE>;
			clock-names = "gce";
		};

		auxadc: auxadc@11001000 {
			compatible = "mediatek,mt8183-auxadc",
				     "mediatek,mt8173-auxadc";
			reg = <0 0x11001000 0 0x1000>;
			clocks = <&infracfg CLK_INFRA_AUXADC>;
			clock-names = "main";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8183-uart",
				     "mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
			clock-names = "baud", "bus";
			status = "disabled";
		};

		i2c6: i2c@11005000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11005000 0 0x1000>,
			      <0 0x11000600 0 0x80>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C6>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c0: i2c@11007000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11007000 0 0x1000>,
			      <0 0x11000080 0 0x80>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C0>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@11008000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11008000 0 0x1000>,
			      <0 0x11000100 0 0x80>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C1>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
			clock-names = "main", "dma","arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@11009000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11009000 0 0x1000>,
			      <0 0x11000280 0 0x80>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C2>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi0: spi@1100a000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x1100a000 0 0x1000>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI0>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		thermal: thermal-sensor@1100b000 {
			#thermal-sensor-cells = <1>;
			compatible = "mediatek,mt8183-thermal";
			reg = <0 0x1100b000 0 0xc00>;
			clocks = <&infracfg CLK_INFRA_THERM>,
				 <&infracfg CLK_INFRA_AUXADC>;
			clock-names = "therm", "auxadc";
			resets = <&infracfg  MT8183_INFRACFG_AO_THERM_SW_RST>;
			interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
			mediatek,auxadc = <&auxadc>;
			mediatek,apmixedsys = <&apmixedsys>;
			nvmem-cells = <&thermal_calibration>;
			nvmem-cell-names = "calibration-data";
		};

		svs: svs@1100bc00 {
			compatible = "mediatek,mt8183-svs";
			reg = <0 0x1100bc00 0 0x400>;
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_THERM>;
			clock-names = "main";
			nvmem-cells = <&svs_calibration>,
				      <&thermal_calibration>;
			nvmem-cell-names = "svs-calibration-data",
					   "t-calibration-data";
		};

		pwm0: pwm@1100e000 {
			compatible = "mediatek,mt8183-disp-pwm";
			reg = <0 0x1100e000 0 0x1000>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			#pwm-cells = <2>;
			clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>,
					<&infracfg CLK_INFRA_DISP_PWM>;
			clock-names = "main", "mm";
		};

		pwm1: pwm@11006000 {
			compatible = "mediatek,mt8183-pwm";
			reg = <0 0x11006000 0 0x1000>;
			#pwm-cells = <2>;
			clocks = <&infracfg CLK_INFRA_PWM>,
				 <&infracfg CLK_INFRA_PWM_HCLK>,
				 <&infracfg CLK_INFRA_PWM1>,
				 <&infracfg CLK_INFRA_PWM2>,
				 <&infracfg CLK_INFRA_PWM3>,
				 <&infracfg CLK_INFRA_PWM4>;
			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
				      "pwm4";
		};

		i2c3: i2c@1100f000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1100f000 0 0x1000>,
			      <0 0x11000400 0 0x80>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C3>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@11010000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11010000 0 0x1000>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI1>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c1: i2c@11011000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11011000 0 0x1000>,
			      <0 0x11000480 0 0x80>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C4>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@11012000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11012000 0 0x1000>;
			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI2>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi3: spi@11013000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11013000 0 0x1000>;
			interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI3>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c9: i2c@11014000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11014000 0 0x1000>,
			      <0 0x11000180 0 0x80>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C1_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c10: i2c@11015000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11015000 0 0x1000>,
			      <0 0x11000300 0 0x80>;
			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C2_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@11016000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11016000 0 0x1000>,
			      <0 0x11000500 0 0x80>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C5>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c11: i2c@11017000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x11017000 0 0x1000>,
			      <0 0x11000580 0 0x80>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
				 <&infracfg CLK_INFRA_AP_DMA>,
				 <&infracfg CLK_INFRA_I2C5_ARBITER>;
			clock-names = "main", "dma", "arb";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@11018000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11018000 0 0x1000>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI4>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		spi5: spi@11019000 {
			compatible = "mediatek,mt8183-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0 0x11019000 0 0x1000>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
				 <&topckgen CLK_TOP_MUX_SPI>,
				 <&infracfg CLK_INFRA_SPI5>;
			clock-names = "parent-clk", "sel-clk", "spi-clk";
			status = "disabled";
		};

		i2c7: i2c@1101a000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1101a000 0 0x1000>,
			      <0 0x11000680 0 0x80>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C7>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c8: i2c@1101b000 {
			compatible = "mediatek,mt8183-i2c";
			reg = <0 0x1101b000 0 0x1000>,
			      <0 0x11000700 0 0x80>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&infracfg CLK_INFRA_I2C8>,
				 <&infracfg CLK_INFRA_AP_DMA>;
			clock-names = "main", "dma";
			clock-div = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssusb: usb@11201000 {
			compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
			reg = <0 0x11201000 0 0x2e00>,
			      <0 0x11203e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
			phys = <&u2port0 PHY_TYPE_USB2>,
			       <&u3port0 PHY_TYPE_USB3>;
			clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
				 <&infracfg CLK_INFRA_USB>;
			clock-names = "sys_ck", "ref_ck";
			mediatek,syscon-wakeup = <&pericfg 0x420 101>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			status = "disabled";

			usb_host: usb@11200000 {
				compatible = "mediatek,mt8183-xhci",
					     "mediatek,mtk-xhci";
				reg = <0 0x11200000 0 0x1000>;
				reg-names = "mac";
				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
				clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
					 <&infracfg CLK_INFRA_USB>;
				clock-names = "sys_ck", "ref_ck";
				status = "disabled";
			};
		};

		audiosys: clock-controller@11220000 {
			compatible = "mediatek,mt8183-audiosys", "syscon";
			reg = <0 0x11220000 0 0x1000>;
			#clock-cells = <1>;
			afe: audio-controller {
				compatible = "mediatek,mt8183-audio";
				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
				resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>;
				reset-names = "audiosys";
				power-domains =
					<&spm MT8183_POWER_DOMAIN_AUDIO>;
				clocks = <&audiosys CLK_AUDIO_AFE>,
					 <&audiosys CLK_AUDIO_DAC>,
					 <&audiosys CLK_AUDIO_DAC_PREDIS>,
					 <&audiosys CLK_AUDIO_ADC>,
					 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>,
					 <&audiosys CLK_AUDIO_22M>,
					 <&audiosys CLK_AUDIO_24M>,
					 <&audiosys CLK_AUDIO_APLL_TUNER>,
					 <&audiosys CLK_AUDIO_APLL2_TUNER>,
					 <&audiosys CLK_AUDIO_I2S1>,
					 <&audiosys CLK_AUDIO_I2S2>,
					 <&audiosys CLK_AUDIO_I2S3>,
					 <&audiosys CLK_AUDIO_I2S4>,
					 <&audiosys CLK_AUDIO_TDM>,
					 <&audiosys CLK_AUDIO_TML>,
					 <&infracfg CLK_INFRA_AUDIO>,
					 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
					 <&topckgen CLK_TOP_MUX_AUDIO>,
					 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
					 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
					 <&topckgen CLK_TOP_MUX_AUD_1>,
					 <&topckgen CLK_TOP_APLL1_CK>,
					 <&topckgen CLK_TOP_MUX_AUD_2>,
					 <&topckgen CLK_TOP_APLL2_CK>,
					 <&topckgen CLK_TOP_MUX_AUD_ENG1>,
					 <&topckgen CLK_TOP_APLL1_D8>,
					 <&topckgen CLK_TOP_MUX_AUD_ENG2>,
					 <&topckgen CLK_TOP_APLL2_D8>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S0>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S1>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S2>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S3>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S4>,
					 <&topckgen CLK_TOP_MUX_APLL_I2S5>,
					 <&topckgen CLK_TOP_APLL12_DIV0>,
					 <&topckgen CLK_TOP_APLL12_DIV1>,
					 <&topckgen CLK_TOP_APLL12_DIV2>,
					 <&topckgen CLK_TOP_APLL12_DIV3>,
					 <&topckgen CLK_TOP_APLL12_DIV4>,
					 <&topckgen CLK_TOP_APLL12_DIVB>,
					 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/
					 <&clk26m>;
				clock-names = "aud_afe_clk",
						  "aud_dac_clk",
						  "aud_dac_predis_clk",
						  "aud_adc_clk",
						  "aud_adc_adda6_clk",
						  "aud_apll22m_clk",
						  "aud_apll24m_clk",
						  "aud_apll1_tuner_clk",
						  "aud_apll2_tuner_clk",
						  "aud_i2s1_bclk_sw",
						  "aud_i2s2_bclk_sw",
						  "aud_i2s3_bclk_sw",
						  "aud_i2s4_bclk_sw",
						  "aud_tdm_clk",
						  "aud_tml_clk",
						  "aud_infra_clk",
						  "mtkaif_26m_clk",
						  "top_mux_audio",
						  "top_mux_aud_intbus",
						  "top_syspll_d2_d4",
						  "top_mux_aud_1",
						  "top_apll1_ck",
						  "top_mux_aud_2",
						  "top_apll2_ck",
						  "top_mux_aud_eng1",
						  "top_apll1_d8",
						  "top_mux_aud_eng2",
						  "top_apll2_d8",
						  "top_i2s0_m_sel",
						  "top_i2s1_m_sel",
						  "top_i2s2_m_sel",
						  "top_i2s3_m_sel",
						  "top_i2s4_m_sel",
						  "top_i2s5_m_sel",
						  "top_apll12_div0",
						  "top_apll12_div1",
						  "top_apll12_div2",
						  "top_apll12_div3",
						  "top_apll12_div4",
						  "top_apll12_divb",
						  /*"top_apll12_div5",*/
						  "top_clk26m_clk";
			};
		};

		mmc0: mmc@11230000 {
			compatible = "mediatek,mt8183-mmc";
			reg = <0 0x11230000 0 0x1000>,
			      <0 0x11f50000 0 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>,
				 <&infracfg CLK_INFRA_MSDC0>,
				 <&infracfg CLK_INFRA_MSDC0_SCK>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mmc1: mmc@11240000 {
			compatible = "mediatek,mt8183-mmc";
			reg = <0 0x11240000 0 0x1000>,
			      <0 0x11e10000 0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>,
				 <&infracfg CLK_INFRA_MSDC1>,
				 <&infracfg CLK_INFRA_MSDC1_SCK>;
			clock-names = "source", "hclk", "source_cg";
			status = "disabled";
		};

		mipi_tx0: dsi-phy@11e50000 {
			compatible = "mediatek,mt8183-mipi-tx";
			reg = <0 0x11e50000 0 0x1000>;
			clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>;
			#clock-cells = <0>;
			#phy-cells = <0>;
			clock-output-names = "mipi_tx0_pll";
			nvmem-cells = <&mipi_tx_calibration>;
			nvmem-cell-names = "calibration-data";
		};

		efuse: efuse@11f10000 {
			compatible = "mediatek,mt8183-efuse",
				     "mediatek,efuse";
			reg = <0 0x11f10000 0 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;

			socinfo-data1@4c {
				reg = <0x04c 0x4>;
			};

			socinfo-data2@60 {
				reg = <0x060 0x4>;
			};

			thermal_calibration: calib@180 {
				reg = <0x180 0xc>;
			};

			mipi_tx_calibration: calib@190 {
				reg = <0x190 0xc>;
			};

			svs_calibration: calib@580 {
				reg = <0x580 0x64>;
			};
		};

		u3phy: t-phy@11f40000 {
			compatible = "mediatek,mt8183-tphy",
				     "mediatek,generic-tphy-v2";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0x11f40000 0x1000>;
			status = "okay";

			u2port0: usb-phy@0 {
				reg = <0x0 0x700>;
				clocks = <&clk26m>;
				clock-names = "ref";
				#phy-cells = <1>;
				mediatek,discth = <15>;
				status = "okay";
			};

			u3port0: usb-phy@700 {
				reg = <0x0700 0x900>;
				clocks = <&clk26m>;
				clock-names = "ref";
				#phy-cells = <1>;
				status = "okay";
			};
		};

		mfgcfg: syscon@13000000 {
			compatible = "mediatek,mt8183-mfgcfg", "syscon";
			reg = <0 0x13000000 0 0x1000>;
			#clock-cells = <1>;
			power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
		};

		gpu: gpu@13040000 {
			compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost";
			reg = <0 0x13040000 0 0x4000>;
			interrupts =
				<GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
				<GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
				<GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names = "job", "mmu", "gpu";

			clocks = <&mfgcfg CLK_MFG_BG3D>;

			power-domains =
				<&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
				<&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
				<&spm MT8183_POWER_DOMAIN_MFG_2D>;
			power-domain-names = "core0", "core1", "core2";

			operating-points-v2 = <&gpu_opp_table>;
		};

		mmsys: syscon@14000000 {
			compatible = "mediatek,mt8183-mmsys", "syscon";
			reg = <0 0x14000000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
				 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;

			port {
				#address-cells = <1>;
				#size-cells = <0>;

				mmsys_ep_main: endpoint@0 {
					reg = <0>;
					remote-endpoint = <&ovl0_in>;
				};

				mmsys_ep_ext: endpoint@1 {
					reg = <1>;
					remote-endpoint = <&ovl_2l1_in>;
				};
			};
		};

		dma-controller0@14001000 {
			compatible = "mediatek,mt8183-mdp3-rdma";
			reg = <0 0x14001000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
					      <CMDQ_EVENT_MDP_RDMA0_EOF>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
				 <&mmsys CLK_MM_MDP_RSZ1>;
			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
				 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
			#dma-cells = <1>;
		};

		mdp3-rsz0@14003000 {
			compatible = "mediatek,mt8183-mdp3-rsz";
			reg = <0 0x14003000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
					      <CMDQ_EVENT_MDP_RSZ0_EOF>;
			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
		};

		mdp3-rsz1@14004000 {
			compatible = "mediatek,mt8183-mdp3-rsz";
			reg = <0 0x14004000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
					      <CMDQ_EVENT_MDP_RSZ1_EOF>;
			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
		};

		dma-controller@14005000 {
			compatible = "mediatek,mt8183-mdp3-wrot";
			reg = <0 0x14005000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
					      <CMDQ_EVENT_MDP_WROT0_EOF>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_MDP_WROT0>;
			iommus = <&iommu M4U_PORT_MDP_WROT0>;
			#dma-cells = <1>;
		};

		mdp3-wdma@14006000 {
			compatible = "mediatek,mt8183-mdp3-wdma";
			reg = <0 0x14006000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
					      <CMDQ_EVENT_MDP_WDMA0_EOF>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
		};

		ovl0: ovl@14008000 {
			compatible = "mediatek,mt8183-disp-ovl";
			reg = <0 0x14008000 0 0x1000>;
			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL0>;
			iommus = <&iommu M4U_PORT_DISP_OVL0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					ovl0_in: endpoint {
						remote-endpoint = <&mmsys_ep_main>;
					};
				};

				port@1 {
					reg = <1>;
					ovl0_out: endpoint {
						remote-endpoint = <&ovl_2l0_in>;
					};
				};
			};
		};

		ovl_2l0: ovl@14009000 {
			compatible = "mediatek,mt8183-disp-ovl-2l";
			reg = <0 0x14009000 0 0x1000>;
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
			iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					ovl_2l0_in: endpoint {
						remote-endpoint = <&ovl0_out>;
					};
				};

				port@1 {
					reg = <1>;
					ovl_2l0_out: endpoint {
						remote-endpoint = <&rdma0_in>;
					};
				};
			};
		};

		ovl_2l1: ovl@1400a000 {
			compatible = "mediatek,mt8183-disp-ovl-2l";
			reg = <0 0x1400a000 0 0x1000>;
			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_OVL1_2L>;
			iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					ovl_2l1_in: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&mmsys_ep_ext>;
					};
				};

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					ovl_2l1_out: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&rdma1_in>;
					};
				};
			};
		};

		rdma0: rdma@1400b000 {
			compatible = "mediatek,mt8183-disp-rdma";
			reg = <0 0x1400b000 0 0x1000>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
			iommus = <&iommu M4U_PORT_DISP_RDMA0>;
			mediatek,rdma-fifo-size = <5120>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					rdma0_in: endpoint {
						remote-endpoint = <&ovl_2l0_out>;
					};
				};

				port@1 {
					reg = <1>;
					rdma0_out: endpoint {
						remote-endpoint = <&color0_in>;
					};
				};
			};
		};

		rdma1: rdma@1400c000 {
			compatible = "mediatek,mt8183-disp-rdma";
			reg = <0 0x1400c000 0 0x1000>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_RDMA1>;
			iommus = <&iommu M4U_PORT_DISP_RDMA1>;
			mediatek,rdma-fifo-size = <2048>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					rdma1_in: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&ovl_2l1_out>;
					};
				};

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					rdma1_out: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&dpi_in>;
					};
				};
			};
		};

		color0: color@1400e000 {
			compatible = "mediatek,mt8183-disp-color",
				     "mediatek,mt8173-disp-color";
			reg = <0 0x1400e000 0 0x1000>;
			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					color0_in: endpoint {
						remote-endpoint = <&rdma0_out>;
					};
				};

				port@1 {
					reg = <1>;
					color0_out: endpoint {
						remote-endpoint = <&ccorr0_in>;
					};
				};
			};
		};

		ccorr0: ccorr@1400f000 {
			compatible = "mediatek,mt8183-disp-ccorr";
			reg = <0 0x1400f000 0 0x1000>;
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					ccorr0_in: endpoint {
						remote-endpoint = <&color0_out>;
					};
				};

				port@1 {
					reg = <1>;
					ccorr0_out: endpoint {
						remote-endpoint = <&aal0_in>;
					};
				};
			};
		};

		aal0: aal@14010000 {
			compatible = "mediatek,mt8183-disp-aal";
			reg = <0 0x14010000 0 0x1000>;
			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_AAL0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					aal0_in: endpoint {
						remote-endpoint = <&ccorr0_out>;
					};
				};

				port@1 {
					reg = <1>;
					aal0_out: endpoint {
						remote-endpoint = <&gamma0_in>;
					};
				};
			};
		};

		gamma0: gamma@14011000 {
			compatible = "mediatek,mt8183-disp-gamma";
			reg = <0 0x14011000 0 0x1000>;
			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					gamma0_in: endpoint {
						remote-endpoint = <&aal0_out>;
					};
				};

				port@1 {
					reg = <1>;
					gamma0_out: endpoint {
						remote-endpoint = <&dither0_in>;
					};
				};
			};
		};

		dither0: dither@14012000 {
			compatible = "mediatek,mt8183-disp-dither";
			reg = <0 0x14012000 0 0x1000>;
			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					dither0_in: endpoint {
						remote-endpoint = <&gamma0_out>;
					};
				};

				port@1 {
					reg = <1>;
					dither0_out: endpoint {
						remote-endpoint = <&dsi_in>;
					};
				};
			};
		};

		dsi0: dsi@14014000 {
			compatible = "mediatek,mt8183-dsi";
			reg = <0 0x14014000 0 0x1000>;
			interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DSI0_MM>,
				 <&mmsys CLK_MM_DSI0_IF>,
				 <&mipi_tx0>;
			clock-names = "engine", "digital", "hs";
			resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
			phys = <&mipi_tx0>;
			phy-names = "dphy";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					dsi_in: endpoint {
						remote-endpoint = <&dither0_out>;
					};
				};

				port@1 {
					reg = <1>;
					dsi_out: endpoint { };
				};
			};
		};

		dpi0: dpi@14015000 {
			compatible = "mediatek,mt8183-dpi";
			reg = <0 0x14015000 0 0x1000>;
			interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clocks = <&mmsys CLK_MM_DPI_IF>,
				 <&mmsys CLK_MM_DPI_MM>,
				 <&apmixedsys CLK_APMIXED_TVDPLL>;
			clock-names = "pixel", "engine", "pll";
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <0>;

					dpi_in: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&rdma1_out>;
					};
				};

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;
					reg = <1>;

					dpi_out: endpoint@1  {
						reg = <1>;
					};
				};
			};
		};

		mutex: mutex@14016000 {
			compatible = "mediatek,mt8183-disp-mutex";
			reg = <0 0x14016000 0 0x1000>;
			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
		};

		larb0: larb@14017000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x14017000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&mmsys CLK_MM_SMI_LARB0>,
				 <&mmsys CLK_MM_SMI_LARB0>;
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
			clock-names = "apb", "smi";
		};

		smi_common: smi@14019000 {
			compatible = "mediatek,mt8183-smi-common";
			reg = <0 0x14019000 0 0x1000>;
			clocks = <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_SMI_COMMON>,
				 <&mmsys CLK_MM_GALS_COMM0>,
				 <&mmsys CLK_MM_GALS_COMM1>;
			clock-names = "apb", "smi", "gals0", "gals1";
			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
		};

		mdp3-ccorr@1401c000 {
			compatible = "mediatek,mt8183-mdp3-ccorr";
			reg = <0 0x1401c000 0 0x1000>;
			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
			mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
					      <CMDQ_EVENT_MDP_CCORR_EOF>;
			clocks = <&mmsys CLK_MM_MDP_CCORR>;
		};

		imgsys: syscon@15020000 {
			compatible = "mediatek,mt8183-imgsys", "syscon";
			reg = <0 0x15020000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb5: larb@15021000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x15021000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>,
				 <&mmsys CLK_MM_GALS_IMG2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
		};

		larb2: larb@1502f000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1502f000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>,
				 <&mmsys CLK_MM_GALS_IPU2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_ISP>;
		};

		vdecsys: syscon@16000000 {
			compatible = "mediatek,mt8183-vdecsys", "syscon";
			reg = <0 0x16000000 0 0x1000>;
			#clock-cells = <1>;
		};

		vcodec_dec: video-codec@16020000 {
			compatible = "mediatek,mt8183-vcodec-dec";
			reg = <0 0x16020000 0 0x1000>,		/* VDEC_MISC */
			      <0 0x16021000 0 0x800>,		/* VDEC_VLD */
			      <0 0x16021800 0 0x800>,		/* VDEC_TOP */
			      <0 0x16022000 0 0x1000>,		/* VDEC_MC */
			      <0 0x16023000 0 0x1000>,		/* VDEC_AVCVLD */
			      <0 0x16024000 0 0x1000>,		/* VDEC_AVCMV */
			      <0 0x16025000 0 0x1000>,		/* VDEC_PP */
			      <0 0x16026800 0 0x800>,		/* VP8_VD */
			      <0 0x16027000 0 0x800>,		/* VP6_VD */
			      <0 0x16027800 0 0x800>,		/* VP8_VL */
			      <0 0x16028400 0 0x400>;		/* VP9_VD */
			reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp",
				    "hwd", "hwq", "hwb", "hwg";
			interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
				 <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>;
			mediatek,scp = <&scp>;
			mediatek,vdecsys = <&vdecsys>;
			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
			clocks = <&vdecsys CLK_VDEC_VDEC>;
			clock-names = "vdec";
		};

		larb1: larb@16010000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x16010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>;
		};

		vencsys: syscon@17000000 {
			compatible = "mediatek,mt8183-vencsys", "syscon";
			reg = <0 0x17000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb4: larb@17010000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x17010000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&vencsys CLK_VENC_LARB>,
				 <&vencsys CLK_VENC_LARB>;
			clock-names = "apb", "smi";
			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
		};

		vcodec_enc: vcodec@17020000 {
			compatible = "mediatek,mt8183-vcodec-enc";
			reg = <0 0x17020000 0 0x1000>;
			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_VENC_REC>,
				 <&iommu M4U_PORT_VENC_BSDMA>,
				 <&iommu M4U_PORT_VENC_RD_COMV>,
				 <&iommu M4U_PORT_VENC_CUR_LUMA>,
				 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
				 <&iommu M4U_PORT_VENC_REF_LUMA>,
				 <&iommu M4U_PORT_VENC_REF_CHROMA>;
			mediatek,scp = <&scp>;
			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
			clocks = <&vencsys CLK_VENC_VENC>;
			clock-names = "venc_sel";
		};

		venc_jpg: jpeg-encoder@17030000 {
			compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
			reg = <0 0x17030000 0 0x1000>;
			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
			iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
				 <&iommu M4U_PORT_JPGENC_BSDMA>;
			power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
			clocks = <&vencsys CLK_VENC_JPGENC>;
			clock-names = "jpgenc";
		};

		ipu_conn: syscon@19000000 {
			compatible = "mediatek,mt8183-ipu_conn", "syscon";
			reg = <0 0x19000000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_adl: syscon@19010000 {
			compatible = "mediatek,mt8183-ipu_adl", "syscon";
			reg = <0 0x19010000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_core0: syscon@19180000 {
			compatible = "mediatek,mt8183-ipu_core0", "syscon";
			reg = <0 0x19180000 0 0x1000>;
			#clock-cells = <1>;
		};

		ipu_core1: syscon@19280000 {
			compatible = "mediatek,mt8183-ipu_core1", "syscon";
			reg = <0 0x19280000 0 0x1000>;
			#clock-cells = <1>;
		};

		camsys: syscon@1a000000 {
			compatible = "mediatek,mt8183-camsys", "syscon";
			reg = <0 0x1a000000 0 0x1000>;
			#clock-cells = <1>;
		};

		larb6: larb@1a001000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1a001000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>,
				 <&mmsys CLK_MM_GALS_CAM2MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
		};

		larb3: larb@1a002000 {
			compatible = "mediatek,mt8183-smi-larb";
			reg = <0 0x1a002000 0 0x1000>;
			mediatek,smi = <&smi_common>;
			clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>,
				 <&mmsys CLK_MM_GALS_IPU12MM>;
			clock-names = "apb", "smi", "gals";
			power-domains = <&spm MT8183_POWER_DOMAIN_CAM>;
		};
	};

	thermal_zones: thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <100>;
			polling-delay = <500>;
			thermal-sensors = <&thermal 0>;
			sustainable-power = <5000>;

			trips {
				threshold: trip-point0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point1 {
					temperature = <80000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu-crit {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu1
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu2
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu3
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
					contribution = <3072>;
				};
				map1 {
					trip = <&target>;
					cooling-device = <&cpu4
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu5
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu6
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>,
							 <&cpu7
						THERMAL_NO_LIMIT
						THERMAL_NO_LIMIT>;
					contribution = <1024>;
				};
			};
		};

		tzts1: soc-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 1>;
			sustainable-power = <5000>;
			trips {
				soc_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				soc_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		tzts2: gpu-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 2>;
			sustainable-power = <5000>;

			trips {
				gpu_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				gpu_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		tzts3: md1-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 3>;
			sustainable-power = <5000>;

			trips {
				md1_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				md1_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		tzts4: cpu-little-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 4>;
			sustainable-power = <5000>;

			trips {
				cpul_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpul_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		tzts5: cpu-big-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 5>;
			sustainable-power = <5000>;

			trips {
				cpub_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpub_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		tztsABB: tsabb-thermal {
			polling-delay = <1000>;
			polling-delay-passive = <250>;
			thermal-sensors = <&thermal 6>;
			sustainable-power = <5000>;

			trips {
				tsabb_alert: trip-alert {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				tsabb_crit: trip-crit {
					temperature = <100000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};
};