Kconfig.platforms 5.2 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menu "Platform selection"
  3. depends on MMU
  4. comment "CPU Core family selection"
  5. config ARCH_MULTI_V4
  6. bool "ARMv4 based platforms (FA526, StrongARM)"
  7. depends on !ARCH_MULTI_V6_V7
  8. # https://github.com/llvm/llvm-project/issues/50764
  9. depends on !LD_IS_LLD || LLD_VERSION >= 160000
  10. select ARCH_MULTI_V4_V5
  11. select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
  12. config ARCH_MULTI_V4T
  13. bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
  14. depends on !ARCH_MULTI_V6_V7
  15. # https://github.com/llvm/llvm-project/issues/50764
  16. depends on !LD_IS_LLD || LLD_VERSION >= 160000
  17. select ARCH_MULTI_V4_V5
  18. select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
  19. CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
  20. CPU_ARM925T || CPU_ARM940T)
  21. config ARCH_MULTI_V5
  22. bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
  23. depends on !ARCH_MULTI_V6_V7
  24. select ARCH_MULTI_V4_V5
  25. select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
  26. CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
  27. CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
  28. config ARCH_MULTI_V4_V5
  29. bool
  30. config ARCH_MULTI_V6
  31. bool "ARMv6 based platforms (ARM11)"
  32. select ARCH_MULTI_V6_V7
  33. select CPU_V6K
  34. config ARCH_MULTI_V7
  35. bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
  36. default y
  37. select ARCH_MULTI_V6_V7
  38. select CPU_V7
  39. select HAVE_SMP
  40. config ARCH_MULTI_V6_V7
  41. bool
  42. select MIGHT_HAVE_CACHE_L2X0
  43. config ARCH_MULTI_CPU_AUTO
  44. def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
  45. select ARCH_MULTI_V5
  46. endmenu
  47. config ARCH_VIRT
  48. bool "Dummy Virtual Machine"
  49. depends on ARCH_MULTI_V7
  50. select ARM_AMBA
  51. select ARM_GIC
  52. select ARM_GIC_V2M if PCI
  53. select ARM_GIC_V3
  54. select ARM_GIC_V3_ITS if PCI
  55. select ARM_PSCI
  56. select HAVE_ARM_ARCH_TIMER
  57. config ARCH_AIROHA
  58. bool "Airoha SoC Support"
  59. depends on ARCH_MULTI_V7
  60. select ARM_AMBA
  61. select ARM_GIC
  62. select ARM_GIC_V3
  63. select ARM_PSCI
  64. select HAVE_ARM_ARCH_TIMER
  65. help
  66. Support for Airoha EN7523 SoCs
  67. config MACH_ASM9260
  68. bool "Alphascale ASM9260"
  69. depends on ARCH_MULTI_V5
  70. depends on CPU_LITTLE_ENDIAN
  71. select CPU_ARM926T
  72. select ASM9260_TIMER
  73. help
  74. Support for Alphascale ASM9260 based platform.
  75. menuconfig ARCH_HPE
  76. bool "HPE SoC support"
  77. depends on ARCH_MULTI_V7
  78. help
  79. This enables support for HPE ARM based BMC chips.
  80. if ARCH_HPE
  81. config ARCH_HPE_GXP
  82. bool "HPE GXP SoC"
  83. depends on ARCH_MULTI_V7
  84. select ARM_VIC
  85. select GENERIC_IRQ_CHIP
  86. select CLKSRC_MMIO
  87. help
  88. HPE GXP is the name of the HPE Soc. This SoC is used to implement many
  89. BMC features at HPE. It supports ARMv7 architecture based on the Cortex
  90. A9 core. It is capable of using an AXI bus to which a memory controller
  91. is attached. It has multiple SPI interfaces to connect boot flash and
  92. BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It
  93. has multiple i2c engines to drive connectivity with a host
  94. infrastructure.
  95. endif
  96. menuconfig ARCH_MOXART
  97. bool "MOXA ART SoC"
  98. depends on ARCH_MULTI_V4
  99. depends on CPU_LITTLE_ENDIAN
  100. select CPU_FA526
  101. select ARM_DMA_MEM_BUFFERABLE
  102. select FARADAY_FTINTC010
  103. select FTTMR010_TIMER
  104. select GPIOLIB
  105. select PHYLIB if NETDEVICES
  106. help
  107. Say Y here if you want to run your kernel on hardware with a
  108. MOXA ART SoC.
  109. The MOXA ART SoC is based on a Faraday FA526 ARMv4 32-bit
  110. 192 MHz CPU with MMU and 16KB/8KB D/I-cache (UC-7112-LX).
  111. Used on models UC-7101, UC-7112/UC-7110, IA240/IA241, IA3341.
  112. if ARCH_MOXART
  113. config MACH_UC7112LX
  114. bool "MOXA UC-7112-LX"
  115. depends on ARCH_MOXART
  116. help
  117. Say Y here if you intend to run this kernel on a MOXA
  118. UC-7112-LX embedded computer.
  119. endif
  120. config ARCH_NSPIRE
  121. bool "TI-NSPIRE based"
  122. depends on ARCH_MULTI_V4T
  123. depends on CPU_LITTLE_ENDIAN
  124. select CPU_ARM926T
  125. select GENERIC_IRQ_CHIP
  126. select ARM_AMBA
  127. select ARM_VIC
  128. select ARM_TIMER_SP804
  129. select NSPIRE_TIMER
  130. select POWER_RESET
  131. select POWER_RESET_SYSCON
  132. help
  133. This enables support for systems using the TI-NSPIRE CPU
  134. config ARCH_RDA
  135. bool "RDA Micro SoCs"
  136. depends on ARCH_MULTI_V7
  137. select RDA_INTC
  138. select RDA_TIMER
  139. help
  140. This enables support for the RDA Micro 8810PL SoC family.
  141. menuconfig ARCH_SUNPLUS
  142. bool "Sunplus SoCs"
  143. depends on ARCH_MULTI_V7
  144. help
  145. Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems,
  146. such as the Banana Pi BPI-F2S development board (and derivatives).
  147. (<http://www.sinovoip.com.cn/ecp_view.asp?id=586>)
  148. (<https://tibbo.com/store/plus1.html>)
  149. if ARCH_SUNPLUS
  150. config SOC_SP7021
  151. bool "Sunplus SP7021 SoC support"
  152. default ARCH_SUNPLUS
  153. select HAVE_ARM_ARCH_TIMER
  154. select ARM_GIC
  155. select ARM_PSCI
  156. select PINCTRL
  157. select PINCTRL_SPPCTL
  158. select SERIAL_SUNPLUS if TTY
  159. select SERIAL_SUNPLUS_CONSOLE if TTY
  160. help
  161. Support for Sunplus SP7021 SoC. It is based on ARM 4-core
  162. Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
  163. Ethernet, etc.), FPGA interface, chip-to-chip bus.
  164. It is designed for industrial control.
  165. endif
  166. config ARCH_UNIPHIER
  167. bool "Socionext UniPhier SoCs"
  168. depends on ARCH_MULTI_V7
  169. select ARCH_HAS_RESET_CONTROLLER
  170. select ARM_AMBA
  171. select ARM_GLOBAL_TIMER
  172. select ARM_GIC
  173. select HAVE_ARM_SCU
  174. select HAVE_ARM_TWD if SMP
  175. select PINCTRL
  176. select RESET_CONTROLLER
  177. help
  178. Support for UniPhier SoC family developed by Socionext Inc.
  179. (formerly, System LSI Business Division of Panasonic Corporation)