intel-multi-link.rst 16 KB

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  1. .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
  2. .. include:: <isonum.txt>
  3. ================================================
  4. HDAudio multi-link extensions on Intel platforms
  5. ================================================
  6. :Copyright: |copy| 2023 Intel Corporation
  7. This file documents the 'multi-link structure' introduced in 2015 with
  8. the Skylake processor and recently extended in newer Intel platforms
  9. HDaudio existing link mapping (2015 addition in SkyLake)
  10. ========================================================
  11. External HDAudio codecs are handled with link #0, while iDISP codec
  12. for HDMI/DisplayPort is handled with link #1.
  13. The only change to the 2015 definitions is the declaration of the
  14. LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
  15. backwards-compatible change.
  16. LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They
  17. are only used in existing drivers when the SCF value needs to be
  18. corrected.
  19. Basic structure for HDaudio codecs
  20. ----------------------------------
  21. ::
  22. +-----------+
  23. | ML cap #0 |
  24. +-----------+
  25. | ML cap #1 |---+
  26. +-----------+ |
  27. |
  28. +--> 0x0 +---------------+ LCAP
  29. | ALT=0 |
  30. +---------------+
  31. | S192 |
  32. +---------------+
  33. | S96 |
  34. +---------------+
  35. | S48 |
  36. +---------------+
  37. | S24 |
  38. +---------------+
  39. | S12 |
  40. +---------------+
  41. | S6 |
  42. +---------------+
  43. 0x4 +---------------+ LCTL
  44. | INTSTS |
  45. +---------------+
  46. | CPA |
  47. +---------------+
  48. | SPA |
  49. +---------------+
  50. | SCF |
  51. +---------------+
  52. 0x8 +---------------+ LOSIDV
  53. | L1OSIVD15 |
  54. +---------------+
  55. | L1OSIDV.. |
  56. +---------------+
  57. | L1OSIDV1 |
  58. +---------------+
  59. 0xC +---------------+ LSDIID
  60. | SDIID14 |
  61. +---------------+
  62. | SDIID... |
  63. +---------------+
  64. | SDIID0 |
  65. +---------------+
  66. SoundWire HDaudio extended link mapping
  67. =======================================
  68. A SoundWire extended link is identified when LCAP.ALT=1 and
  69. LEPTR.ID=0.
  70. DMA control uses the existing LOSIDV register.
  71. Changes include additional descriptions for enumeration that were not
  72. present in earlier generations.
  73. - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
  74. - number of sublinks (manager IP) in LCAP.LSCOUNT
  75. - power management moved from SHIM to LCTL.SPA bits
  76. - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
  77. - mapping of SoundWire codecs to SDI ID bits
  78. - move of SHIM and Cadence registers to different offsets, with no
  79. change in functionality. The LEPTR.PTR value is an offset from the
  80. ML address, with a default value of 0x30000.
  81. Extended structure for SoundWire (assuming 4 Manager IP)
  82. --------------------------------------------------------
  83. ::
  84. +-----------+
  85. | ML cap #0 |
  86. +-----------+
  87. | ML cap #1 |
  88. +-----------+
  89. | ML cap #2 |---+
  90. +-----------+ |
  91. |
  92. +--> 0x0 +---------------+ LCAP
  93. | ALT=1 |
  94. +---------------+
  95. | INTC |
  96. +---------------+
  97. | OFLS |
  98. +---------------+
  99. | LSS |
  100. +---------------+
  101. | SLCOUNT=4 |-----------+
  102. +---------------+ |
  103. |
  104. 0x4 +---------------+ LCTL |
  105. | INTSTS | |
  106. +---------------+ |
  107. | CPA (x bits) | |
  108. +---------------+ |
  109. | SPA (x bits) | |
  110. +---------------+ for each sublink x
  111. | INTEN | |
  112. +---------------+ |
  113. | OFLEN | |
  114. +---------------+ |
  115. |
  116. 0x8 +---------------+ LOSIDV |
  117. | L1OSIVD15 | |
  118. +---------------+ |
  119. | L1OSIDV.. | |
  120. +---------------+ |
  121. | L1OSIDV1 | +---+----------------------------------------------------------+
  122. +---------------+ | |
  123. v |
  124. 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 |
  125. | SDIID14 | | | SoundWire SHIM | |
  126. +---------------+ | | generic | |
  127. | SDIID... | | +-----------------+ 0x00030100 |
  128. +---------------+ | | SoundWire IP | |
  129. | SDIID0 | | +-----------------+ 0x00036000 |
  130. +---------------+ | | SoundWire SHIM | |
  131. | | vendor-specific | |
  132. 0x1C +---------------+ LSYNC | +-----------------+ |
  133. | CMDSYNC | | v
  134. +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x
  135. | SYNCGO | | | SoundWire SHIM |
  136. +---------------+ | | generic |
  137. | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x
  138. +---------------+ | | SoundWire IP |
  139. | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x
  140. +---------------+ | | SoundWire SHIM |
  141. | | vendor-specific |
  142. 0x20 +---------------+ LEPTR | +-----------------+
  143. | ID = 0 | |
  144. +---------------+ |
  145. | VER | |
  146. +---------------+ |
  147. | PTR |------------+
  148. +---------------+
  149. DMIC HDaudio extended link mapping
  150. ==================================
  151. A DMIC extended link is identified when LCAP.ALT=1 and
  152. LEPTR.ID=0xC1 are set.
  153. DMA control uses the existing LOSIDV register
  154. Changes include additional descriptions for enumeration that were not
  155. present in earlier generations.
  156. - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
  157. - power management with LCTL.SPA bits
  158. - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
  159. - move of DMIC registers to different offsets, with no change in
  160. functionality. The LEPTR.PTR value is an offset from the ML
  161. address, with a default value of 0x10000.
  162. Extended structure for DMIC
  163. ---------------------------
  164. ::
  165. +-----------+
  166. | ML cap #0 |
  167. +-----------+
  168. | ML cap #1 |
  169. +-----------+
  170. | ML cap #2 |---+
  171. +-----------+ |
  172. |
  173. +--> 0x0 +---------------+ LCAP
  174. | ALT=1 |
  175. +---------------+
  176. | INTC |
  177. +---------------+
  178. | OFLS |
  179. +---------------+
  180. | SLCOUNT=1 |
  181. +---------------+
  182. 0x4 +---------------+ LCTL
  183. | INTSTS |
  184. +---------------+
  185. | CPA |
  186. +---------------+
  187. | SPA |
  188. +---------------+
  189. | INTEN |
  190. +---------------+
  191. | OFLEN |
  192. +---------------+ +---> 0x10000 +-----------------+ 0x00010000
  193. | | DMIC SHIM |
  194. 0x8 +---------------+ LOSIDV | | generic |
  195. | L1OSIVD15 | | +-----------------+ 0x00010100
  196. +---------------+ | | DMIC IP |
  197. | L1OSIDV.. | | +-----------------+ 0x00016000
  198. +---------------+ | | DMIC SHIM |
  199. | L1OSIDV1 | | | vendor-specific |
  200. +---------------+ | +-----------------+
  201. |
  202. 0x20 +---------------+ LEPTR |
  203. | ID = 0xC1 | |
  204. +---------------+ |
  205. | VER | |
  206. +---------------+ |
  207. | PTR |-----------+
  208. +---------------+
  209. SSP HDaudio extended link mapping
  210. =================================
  211. A DMIC extended link is identified when LCAP.ALT=1 and
  212. LEPTR.ID=0xC0 are set.
  213. DMA control uses the existing LOSIDV register
  214. Changes include additional descriptions for enumeration and control that were not
  215. present in earlier generations:
  216. - number of sublinks (SSP IP instances) in LCAP.LSCOUNT
  217. - power management moved from SHIM to LCTL.SPA bits
  218. - hand-over to the DSP for access to multi-link registers, SHIM/IP
  219. with LCTL.OFLEN
  220. - move of SHIM and SSP IP registers to different offsets, with no
  221. change in functionality. The LEPTR.PTR value is an offset from the ML
  222. address, with a default value of 0x28000.
  223. Extended structure for SSP (assuming 3 instances of the IP)
  224. -----------------------------------------------------------
  225. ::
  226. +-----------+
  227. | ML cap #0 |
  228. +-----------+
  229. | ML cap #1 |
  230. +-----------+
  231. | ML cap #2 |---+
  232. +-----------+ |
  233. |
  234. +--> 0x0 +---------------+ LCAP
  235. | ALT=1 |
  236. +---------------+
  237. | INTC |
  238. +---------------+
  239. | OFLS |
  240. +---------------+
  241. | SLCOUNT=3 |-------------------------for each sublink x -------------------------+
  242. +---------------+ |
  243. |
  244. 0x4 +---------------+ LCTL |
  245. | INTSTS | |
  246. +---------------+ |
  247. | CPA (x bits) | |
  248. +---------------+ |
  249. | SPA (x bits) | |
  250. +---------------+ |
  251. | INTEN | |
  252. +---------------+ |
  253. | OFLEN | |
  254. +---------------+ +---> 0x28000 +-----------------+ 0x00028000 |
  255. | | SSP SHIM | |
  256. 0x8 +---------------+ LOSIDV | | generic | |
  257. | L1OSIVD15 | | +-----------------+ 0x00028100 |
  258. +---------------+ | | SSP IP | |
  259. | L1OSIDV.. | | +-----------------+ 0x00028C00 |
  260. +---------------+ | | SSP SHIM | |
  261. | L1OSIDV1 | | | vendor-specific | |
  262. +---------------+ | +-----------------+ |
  263. | v
  264. 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x
  265. | ID = 0xC0 | | | SSP SHIM |
  266. +---------------+ | | generic |
  267. | VER | | +-----------------+ 0x00028100 + 0x1000 * x
  268. +---------------+ | | SSP IP |
  269. | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x
  270. +---------------+ | SSP SHIM |
  271. | vendor-specific |
  272. +-----------------+