i2c-address-translators.rst 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. .. SPDX-License-Identifier: GPL-2.0
  2. =======================
  3. I2C Address Translators
  4. =======================
  5. Author: Luca Ceresoli <luca@lucaceresoli.net>
  6. Author: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
  7. Description
  8. -----------
  9. An I2C Address Translator (ATR) is a device with an I2C slave parent
  10. ("upstream") port and N I2C master child ("downstream") ports, and
  11. forwards transactions from upstream to the appropriate downstream port
  12. with a modified slave address. The address used on the parent bus is
  13. called the "alias" and is (potentially) different from the physical
  14. slave address of the child bus. Address translation is done by the
  15. hardware.
  16. An ATR looks similar to an i2c-mux except:
  17. - the address on the parent and child busses can be different
  18. - there is normally no need to select the child port; the alias used on the
  19. parent bus implies it
  20. The ATR functionality can be provided by a chip with many other features.
  21. The kernel i2c-atr provides a helper to implement an ATR within a driver.
  22. The ATR creates a new I2C "child" adapter on each child bus. Adding
  23. devices on the child bus ends up in invoking the driver code to select
  24. an available alias. Maintaining an appropriate pool of available aliases
  25. and picking one for each new device is up to the driver implementer. The
  26. ATR maintains a table of currently assigned alias and uses it to modify
  27. all I2C transactions directed to devices on the child buses.
  28. A typical example follows.
  29. Topology::
  30. Slave X @ 0x10
  31. .-----. |
  32. .-----. | |---+---- B
  33. | CPU |--A--| ATR |
  34. `-----' | |---+---- C
  35. `-----' |
  36. Slave Y @ 0x10
  37. Alias table:
  38. A, B and C are three physical I2C busses, electrically independent from
  39. each other. The ATR receives the transactions initiated on bus A and
  40. propagates them on bus B or bus C or none depending on the device address
  41. in the transaction and based on the alias table.
  42. Alias table:
  43. .. table::
  44. =============== =====
  45. Client Alias
  46. =============== =====
  47. X (bus B, 0x10) 0x20
  48. Y (bus C, 0x10) 0x30
  49. =============== =====
  50. Transaction:
  51. - Slave X driver requests a transaction (on adapter B), slave address 0x10
  52. - ATR driver finds slave X is on bus B and has alias 0x20, rewrites
  53. messages with address 0x20, forwards to adapter A
  54. - Physical I2C transaction on bus A, slave address 0x20
  55. - ATR chip detects transaction on address 0x20, finds it in table,
  56. propagates transaction on bus B with address translated to 0x10,
  57. keeps clock stretched on bus A waiting for reply
  58. - Slave X chip (on bus B) detects transaction at its own physical
  59. address 0x10 and replies normally
  60. - ATR chip stops clock stretching and forwards reply on bus A,
  61. with address translated back to 0x20
  62. - ATR driver receives the reply, rewrites messages with address 0x10
  63. as they were initially
  64. - Slave X driver gets back the msgs[], with reply and address 0x10
  65. Usage:
  66. 1. In the driver (typically in the probe function) add an ATR by
  67. calling i2c_atr_new() passing attach/detach callbacks
  68. 2. When the attach callback is called pick an appropriate alias,
  69. configure it in the chip and return the chosen alias in the
  70. alias_id parameter
  71. 3. When the detach callback is called, deconfigure the alias from
  72. the chip and put the alias back in the pool for later usage
  73. I2C ATR functions and data structures
  74. -------------------------------------
  75. .. kernel-doc:: include/linux/i2c-atr.h