qcom-tsens.yaml 12 KB

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  1. # SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. # Copyright 2019 Linaro Ltd.
  3. %YAML 1.2
  4. ---
  5. $id: http://devicetree.org/schemas/thermal/qcom-tsens.yaml#
  6. $schema: http://devicetree.org/meta-schemas/core.yaml#
  7. title: QCOM SoC Temperature Sensor (TSENS)
  8. maintainers:
  9. - Amit Kucheria <amitk@kernel.org>
  10. description: |
  11. QCOM SoCs have TSENS IP to allow temperature measurement. There are currently
  12. three distinct major versions of the IP that is supported by a single driver.
  13. The IP versions are named v0.1, v1 and v2 in the driver, where v0.1 captures
  14. everything before v1 when there was no versioning information.
  15. properties:
  16. compatible:
  17. oneOf:
  18. - description: msm8960 TSENS based
  19. items:
  20. - enum:
  21. - qcom,ipq8064-tsens
  22. - qcom,msm8960-tsens
  23. - description: v0.1 of TSENS
  24. items:
  25. - enum:
  26. - qcom,mdm9607-tsens
  27. - qcom,msm8226-tsens
  28. - qcom,msm8909-tsens
  29. - qcom,msm8916-tsens
  30. - qcom,msm8939-tsens
  31. - qcom,msm8974-tsens
  32. - const: qcom,tsens-v0_1
  33. - description:
  34. v1 of TSENS without RPM which requires to be explicitly reset
  35. and enabled in the driver.
  36. enum:
  37. - qcom,ipq5018-tsens
  38. - description: v1 of TSENS
  39. items:
  40. - enum:
  41. - qcom,msm8937-tsens
  42. - qcom,msm8956-tsens
  43. - qcom,msm8976-tsens
  44. - qcom,qcs404-tsens
  45. - const: qcom,tsens-v1
  46. - description: v2 of TSENS
  47. items:
  48. - enum:
  49. - qcom,glymur-tsens
  50. - qcom,kaanapali-tsens
  51. - qcom,milos-tsens
  52. - qcom,msm8953-tsens
  53. - qcom,msm8996-tsens
  54. - qcom,msm8998-tsens
  55. - qcom,qcm2290-tsens
  56. - qcom,qcs8300-tsens
  57. - qcom,qcs615-tsens
  58. - qcom,sa8255p-tsens
  59. - qcom,sa8775p-tsens
  60. - qcom,sar2130p-tsens
  61. - qcom,sc7180-tsens
  62. - qcom,sc7280-tsens
  63. - qcom,sc8180x-tsens
  64. - qcom,sc8280xp-tsens
  65. - qcom,sdm630-tsens
  66. - qcom,sdm845-tsens
  67. - qcom,sm6115-tsens
  68. - qcom,sm6350-tsens
  69. - qcom,sm6375-tsens
  70. - qcom,sm8150-tsens
  71. - qcom,sm8250-tsens
  72. - qcom,sm8350-tsens
  73. - qcom,sm8450-tsens
  74. - qcom,sm8550-tsens
  75. - qcom,sm8650-tsens
  76. - qcom,x1e80100-tsens
  77. - const: qcom,tsens-v2
  78. - description: v2 of TSENS with combined interrupt
  79. enum:
  80. - qcom,ipq5332-tsens
  81. - qcom,ipq5424-tsens
  82. - qcom,ipq8074-tsens
  83. - description: v2 of TSENS with combined interrupt
  84. items:
  85. - enum:
  86. - qcom,ipq6018-tsens
  87. - qcom,ipq9574-tsens
  88. - const: qcom,ipq8074-tsens
  89. reg:
  90. items:
  91. - description: TM registers
  92. - description: SROT registers
  93. interrupts:
  94. minItems: 1
  95. maxItems: 2
  96. interrupt-names:
  97. minItems: 1
  98. maxItems: 2
  99. nvmem-cells:
  100. oneOf:
  101. - minItems: 1
  102. maxItems: 2
  103. description:
  104. Reference to an nvmem node for the calibration data
  105. - minItems: 5
  106. maxItems: 35
  107. description: |
  108. Reference to nvmem cells for the calibration mode, two calibration
  109. bases and two cells per each sensor
  110. # special case for msm8974 / apq8084
  111. - maxItems: 51
  112. description: |
  113. Reference to nvmem cells for the calibration mode, two calibration
  114. bases and two cells per each sensor, main and backup copies, plus use_backup cell
  115. nvmem-cell-names:
  116. oneOf:
  117. - minItems: 1
  118. items:
  119. - const: calib
  120. - enum:
  121. - calib_backup
  122. - calib_sel
  123. - minItems: 5
  124. items:
  125. - const: mode
  126. - const: base1
  127. - const: base2
  128. - pattern: '^s[0-9]+_p1$'
  129. - pattern: '^s[0-9]+_p2$'
  130. - pattern: '^s[0-9]+_p1$'
  131. - pattern: '^s[0-9]+_p2$'
  132. - pattern: '^s[0-9]+_p1$'
  133. - pattern: '^s[0-9]+_p2$'
  134. - pattern: '^s[0-9]+_p1$'
  135. - pattern: '^s[0-9]+_p2$'
  136. - pattern: '^s[0-9]+_p1$'
  137. - pattern: '^s[0-9]+_p2$'
  138. - pattern: '^s[0-9]+_p1$'
  139. - pattern: '^s[0-9]+_p2$'
  140. - pattern: '^s[0-9]+_p1$'
  141. - pattern: '^s[0-9]+_p2$'
  142. - pattern: '^s[0-9]+_p1$'
  143. - pattern: '^s[0-9]+_p2$'
  144. - pattern: '^s[0-9]+_p1$'
  145. - pattern: '^s[0-9]+_p2$'
  146. - pattern: '^s[0-9]+_p1$'
  147. - pattern: '^s[0-9]+_p2$'
  148. - pattern: '^s[0-9]+_p1$'
  149. - pattern: '^s[0-9]+_p2$'
  150. - pattern: '^s[0-9]+_p1$'
  151. - pattern: '^s[0-9]+_p2$'
  152. - pattern: '^s[0-9]+_p1$'
  153. - pattern: '^s[0-9]+_p2$'
  154. - pattern: '^s[0-9]+_p1$'
  155. - pattern: '^s[0-9]+_p2$'
  156. - pattern: '^s[0-9]+_p1$'
  157. - pattern: '^s[0-9]+_p2$'
  158. - pattern: '^s[0-9]+_p1$'
  159. - pattern: '^s[0-9]+_p2$'
  160. # special case for msm8974 / apq8084
  161. - items:
  162. - const: mode
  163. - const: base1
  164. - const: base2
  165. - const: use_backup
  166. - const: mode_backup
  167. - const: base1_backup
  168. - const: base2_backup
  169. - const: s0_p1
  170. - const: s0_p2
  171. - const: s1_p1
  172. - const: s1_p2
  173. - const: s2_p1
  174. - const: s2_p2
  175. - const: s3_p1
  176. - const: s3_p2
  177. - const: s4_p1
  178. - const: s4_p2
  179. - const: s5_p1
  180. - const: s5_p2
  181. - const: s6_p1
  182. - const: s6_p2
  183. - const: s7_p1
  184. - const: s7_p2
  185. - const: s8_p1
  186. - const: s8_p2
  187. - const: s9_p1
  188. - const: s9_p2
  189. - const: s10_p1
  190. - const: s10_p2
  191. - const: s0_p1_backup
  192. - const: s0_p2_backup
  193. - const: s1_p1_backup
  194. - const: s1_p2_backup
  195. - const: s2_p1_backup
  196. - const: s2_p2_backup
  197. - const: s3_p1_backup
  198. - const: s3_p2_backup
  199. - const: s4_p1_backup
  200. - const: s4_p2_backup
  201. - const: s5_p1_backup
  202. - const: s5_p2_backup
  203. - const: s6_p1_backup
  204. - const: s6_p2_backup
  205. - const: s7_p1_backup
  206. - const: s7_p2_backup
  207. - const: s8_p1_backup
  208. - const: s8_p2_backup
  209. - const: s9_p1_backup
  210. - const: s9_p2_backup
  211. - const: s10_p1_backup
  212. - const: s10_p2_backup
  213. - minItems: 8
  214. items:
  215. - const: mode
  216. - const: base0
  217. - const: base1
  218. - pattern: '^tsens_sens[0-9]+_off$'
  219. - pattern: '^tsens_sens[0-9]+_off$'
  220. - pattern: '^tsens_sens[0-9]+_off$'
  221. - pattern: '^tsens_sens[0-9]+_off$'
  222. - pattern: '^tsens_sens[0-9]+_off$'
  223. - pattern: '^tsens_sens[0-9]+_off$'
  224. - pattern: '^tsens_sens[0-9]+_off$'
  225. "#qcom,sensors":
  226. description:
  227. Number of sensors enabled on this platform
  228. $ref: /schemas/types.yaml#/definitions/uint32
  229. minimum: 1
  230. maximum: 16
  231. "#thermal-sensor-cells":
  232. const: 1
  233. required:
  234. - compatible
  235. - interrupts
  236. - interrupt-names
  237. - "#qcom,sensors"
  238. allOf:
  239. - $ref: thermal-sensor.yaml#
  240. - if:
  241. properties:
  242. compatible:
  243. contains:
  244. enum:
  245. - qcom,ipq5018-tsens
  246. - qcom,ipq8064-tsens
  247. - qcom,msm8960-tsens
  248. - qcom,tsens-v0_1
  249. - qcom,tsens-v1
  250. then:
  251. properties:
  252. interrupts:
  253. items:
  254. - description: Combined interrupt if upper or lower threshold crossed
  255. interrupt-names:
  256. items:
  257. - const: uplow
  258. - if:
  259. properties:
  260. compatible:
  261. contains:
  262. const: qcom,tsens-v2
  263. then:
  264. properties:
  265. interrupts:
  266. items:
  267. - description: Combined interrupt if upper or lower threshold crossed
  268. - description: Interrupt if critical threshold crossed
  269. interrupt-names:
  270. items:
  271. - const: uplow
  272. - const: critical
  273. - if:
  274. properties:
  275. compatible:
  276. contains:
  277. enum:
  278. - qcom,ipq5332-tsens
  279. - qcom,ipq5424-tsens
  280. - qcom,ipq8074-tsens
  281. then:
  282. properties:
  283. interrupts:
  284. items:
  285. - description: Combined interrupt if upper, lower or critical thresholds crossed
  286. interrupt-names:
  287. items:
  288. - const: combined
  289. - if:
  290. properties:
  291. compatible:
  292. contains:
  293. enum:
  294. - qcom,ipq5332-tsens
  295. - qcom,ipq5424-tsens
  296. - qcom,ipq8074-tsens
  297. - qcom,tsens-v0_1
  298. - qcom,tsens-v1
  299. - qcom,tsens-v2
  300. then:
  301. required:
  302. - reg
  303. unevaluatedProperties: false
  304. examples:
  305. - |
  306. #include <dt-bindings/interrupt-controller/arm-gic.h>
  307. thermal-sensor {
  308. compatible = "qcom,ipq8064-tsens";
  309. nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
  310. nvmem-cell-names = "calib", "calib_backup";
  311. interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
  312. interrupt-names = "uplow";
  313. #qcom,sensors = <11>;
  314. #thermal-sensor-cells = <1>;
  315. };
  316. - |
  317. #include <dt-bindings/interrupt-controller/arm-gic.h>
  318. // Example 1 (new calibration data: for pre v1 IP):
  319. thermal-sensor@4a9000 {
  320. compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
  321. reg = <0x4a9000 0x1000>, /* TM */
  322. <0x4a8000 0x1000>; /* SROT */
  323. nvmem-cells = <&tsens_mode>,
  324. <&tsens_base1>, <&tsens_base2>,
  325. <&tsens_s0_p1>, <&tsens_s0_p2>,
  326. <&tsens_s1_p1>, <&tsens_s1_p2>,
  327. <&tsens_s2_p1>, <&tsens_s2_p2>,
  328. <&tsens_s4_p1>, <&tsens_s4_p2>,
  329. <&tsens_s5_p1>, <&tsens_s5_p2>;
  330. nvmem-cell-names = "mode",
  331. "base1", "base2",
  332. "s0_p1", "s0_p2",
  333. "s1_p1", "s1_p2",
  334. "s2_p1", "s2_p2",
  335. "s4_p1", "s4_p2",
  336. "s5_p1", "s5_p2";
  337. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  338. interrupt-names = "uplow";
  339. #qcom,sensors = <5>;
  340. #thermal-sensor-cells = <1>;
  341. };
  342. - |
  343. #include <dt-bindings/interrupt-controller/arm-gic.h>
  344. // Example 1 (legacy: for pre v1 IP):
  345. tsens1: thermal-sensor@4a9000 {
  346. compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
  347. reg = <0x4a9000 0x1000>, /* TM */
  348. <0x4a8000 0x1000>; /* SROT */
  349. nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
  350. nvmem-cell-names = "calib", "calib_sel";
  351. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  352. interrupt-names = "uplow";
  353. #qcom,sensors = <5>;
  354. #thermal-sensor-cells = <1>;
  355. };
  356. - |
  357. #include <dt-bindings/interrupt-controller/arm-gic.h>
  358. // Example 2 (for any platform containing v1 of the TSENS IP):
  359. tsens2: thermal-sensor@4a9000 {
  360. compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
  361. reg = <0x004a9000 0x1000>, /* TM */
  362. <0x004a8000 0x1000>; /* SROT */
  363. nvmem-cells = <&tsens_caldata>;
  364. nvmem-cell-names = "calib";
  365. interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
  366. interrupt-names = "uplow";
  367. #qcom,sensors = <10>;
  368. #thermal-sensor-cells = <1>;
  369. };
  370. - |
  371. #include <dt-bindings/interrupt-controller/arm-gic.h>
  372. // Example 3 (for any platform containing v2 of the TSENS IP):
  373. tsens3: thermal-sensor@c263000 {
  374. compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
  375. reg = <0xc263000 0x1ff>,
  376. <0xc222000 0x1ff>;
  377. interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
  378. <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
  379. interrupt-names = "uplow", "critical";
  380. #qcom,sensors = <13>;
  381. #thermal-sensor-cells = <1>;
  382. };
  383. - |
  384. #include <dt-bindings/interrupt-controller/arm-gic.h>
  385. // Example 4 (for any IPQ8074 based SoC-s):
  386. tsens4: thermal-sensor@4a9000 {
  387. compatible = "qcom,ipq8074-tsens";
  388. reg = <0x4a9000 0x1000>,
  389. <0x4a8000 0x1000>;
  390. interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  391. interrupt-names = "combined";
  392. #qcom,sensors = <16>;
  393. #thermal-sensor-cells = <1>;
  394. };
  395. ...