qcom-lmh.yaml 2.1 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. # Copyright 2021 Linaro Ltd.
  3. %YAML 1.2
  4. ---
  5. $id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
  6. $schema: http://devicetree.org/meta-schemas/core.yaml#
  7. title: Qualcomm Limits Management Hardware(LMh)
  8. maintainers:
  9. - Thara Gopinath <thara.gopinath@gmail.com>
  10. description:
  11. Limits Management Hardware(LMh) is a hardware infrastructure on some
  12. Qualcomm SoCs that can enforce temperature and current limits as
  13. programmed by software for certain IPs like CPU.
  14. properties:
  15. compatible:
  16. oneOf:
  17. - enum:
  18. - qcom,sc8180x-lmh
  19. - qcom,sdm845-lmh
  20. - qcom,sm8150-lmh
  21. - items:
  22. - const: qcom,qcm2290-lmh
  23. - const: qcom,sm8150-lmh
  24. reg:
  25. items:
  26. - description: core registers
  27. interrupts:
  28. maxItems: 1
  29. '#interrupt-cells':
  30. const: 1
  31. interrupt-controller: true
  32. cpus:
  33. description:
  34. phandle of the first cpu in the LMh cluster
  35. maxItems: 1
  36. qcom,lmh-temp-arm-millicelsius:
  37. description:
  38. An integer expressing temperature threshold at which the LMh thermal
  39. FSM is engaged.
  40. qcom,lmh-temp-low-millicelsius:
  41. description:
  42. An integer expressing temperature threshold at which the state machine
  43. will attempt to remove frequency throttling.
  44. qcom,lmh-temp-high-millicelsius:
  45. description:
  46. An integer expressing temperature threshold at which the state machine
  47. will attempt to throttle the frequency.
  48. required:
  49. - compatible
  50. - reg
  51. - interrupts
  52. - '#interrupt-cells'
  53. - interrupt-controller
  54. - cpus
  55. - qcom,lmh-temp-arm-millicelsius
  56. - qcom,lmh-temp-low-millicelsius
  57. - qcom,lmh-temp-high-millicelsius
  58. additionalProperties: false
  59. examples:
  60. - |
  61. #include <dt-bindings/interrupt-controller/arm-gic.h>
  62. lmh@17d70800 {
  63. compatible = "qcom,sdm845-lmh";
  64. reg = <0x17d70800 0x400>;
  65. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  66. cpus = <&CPU4>;
  67. qcom,lmh-temp-arm-millicelsius = <65000>;
  68. qcom,lmh-temp-low-millicelsius = <94500>;
  69. qcom,lmh-temp-high-millicelsius = <95000>;
  70. interrupt-controller;
  71. #interrupt-cells = <1>;
  72. };