renesas,ether.yaml 3.5 KB

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  1. # SPDX-License-Identifier: GPL-2.0
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/net/renesas,ether.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: Renesas Electronics SH EtherMAC
  7. allOf:
  8. - $ref: ethernet-controller.yaml#
  9. maintainers:
  10. - Sergei Shtylyov <sergei.shtylyov@gmail.com>
  11. properties:
  12. compatible:
  13. oneOf:
  14. - items:
  15. - enum:
  16. - renesas,gether-r8a7740 # device is a part of R8A7740 SoC
  17. - renesas,gether-r8a77980 # device is a part of R8A77980 SoC
  18. - renesas,ether-r7s72100 # device is a part of R7S72100 SoC
  19. - renesas,ether-r7s9210 # device is a part of R7S9210 SoC
  20. - items:
  21. - enum:
  22. - renesas,ether-r8a7778 # device is a part of R8A7778 SoC
  23. - renesas,ether-r8a7779 # device is a part of R8A7779 SoC
  24. - enum:
  25. - renesas,rcar-gen1-ether # a generic R-Car Gen1 device
  26. - items:
  27. - enum:
  28. - renesas,ether-r8a7742 # device is a part of R8A7742 SoC
  29. - renesas,ether-r8a7743 # device is a part of R8A7743 SoC
  30. - renesas,ether-r8a7745 # device is a part of R8A7745 SoC
  31. - renesas,ether-r8a7790 # device is a part of R8A7790 SoC
  32. - renesas,ether-r8a7791 # device is a part of R8A7791 SoC
  33. - renesas,ether-r8a7793 # device is a part of R8A7793 SoC
  34. - renesas,ether-r8a7794 # device is a part of R8A7794 SoC
  35. - enum:
  36. - renesas,rcar-gen2-ether # a generic R-Car Gen2 or RZ/G1 device
  37. reg:
  38. items:
  39. - description: E-DMAC/feLic registers
  40. - description: TSU registers
  41. minItems: 1
  42. interrupts:
  43. maxItems: 1
  44. '#address-cells':
  45. description: number of address cells for the MDIO bus
  46. const: 1
  47. '#size-cells':
  48. description: number of size cells on the MDIO bus
  49. const: 0
  50. clocks:
  51. maxItems: 1
  52. iommus:
  53. maxItems: 1
  54. power-domains:
  55. maxItems: 1
  56. resets:
  57. maxItems: 1
  58. phy-mode: true
  59. phy-handle: true
  60. renesas,no-ether-link:
  61. type: boolean
  62. description:
  63. specify when a board does not provide a proper Ether LINK signal
  64. renesas,ether-link-active-low:
  65. type: boolean
  66. description:
  67. specify when the Ether LINK signal is active-low instead of normal
  68. active-high
  69. patternProperties:
  70. "@[0-9a-f]$":
  71. type: object
  72. required:
  73. - compatible
  74. - reg
  75. - interrupts
  76. - phy-mode
  77. - phy-handle
  78. - '#address-cells'
  79. - '#size-cells'
  80. - clocks
  81. additionalProperties: false
  82. examples:
  83. # Lager board
  84. - |
  85. #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
  86. #include <dt-bindings/interrupt-controller/arm-gic.h>
  87. #include <dt-bindings/power/r8a7790-sysc.h>
  88. #include <dt-bindings/gpio/gpio.h>
  89. ethernet@ee700000 {
  90. compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
  91. reg = <0xee700000 0x400>;
  92. interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  93. clocks = <&cpg CPG_MOD 813>;
  94. power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
  95. resets = <&cpg 813>;
  96. phy-mode = "rmii";
  97. phy-handle = <&phy1>;
  98. renesas,ether-link-active-low;
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. phy1: ethernet-phy@1 {
  102. compatible = "ethernet-phy-id0022.1537",
  103. "ethernet-phy-ieee802.3-c22";
  104. reg = <1>;
  105. interrupt-parent = <&irqc0>;
  106. interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  107. reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
  108. };
  109. };