qca,ar71xx.yaml 4.8 KB

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  1. # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. %YAML 1.2
  3. ---
  4. $id: http://devicetree.org/schemas/net/qca,ar71xx.yaml#
  5. $schema: http://devicetree.org/meta-schemas/core.yaml#
  6. title: QCA AR71XX MAC
  7. allOf:
  8. - $ref: ethernet-controller.yaml#
  9. maintainers:
  10. - Oleksij Rempel <o.rempel@pengutronix.de>
  11. properties:
  12. compatible:
  13. oneOf:
  14. - items:
  15. - enum:
  16. - qca,ar7100-eth # Atheros AR7100
  17. - qca,ar7240-eth # Atheros AR7240
  18. - qca,ar7241-eth # Atheros AR7241
  19. - qca,ar7242-eth # Atheros AR7242
  20. - qca,ar9130-eth # Atheros AR9130
  21. - qca,ar9330-eth # Atheros AR9330
  22. - qca,ar9340-eth # Atheros AR9340
  23. - qca,qca9530-eth # Qualcomm Atheros QCA9530
  24. - qca,qca9550-eth # Qualcomm Atheros QCA9550
  25. - qca,qca9560-eth # Qualcomm Atheros QCA9560
  26. reg:
  27. maxItems: 1
  28. interrupts:
  29. maxItems: 1
  30. clocks:
  31. items:
  32. - description: MAC main clock
  33. - description: MDIO clock
  34. clock-names:
  35. items:
  36. - const: eth
  37. - const: mdio
  38. resets:
  39. items:
  40. - description: MAC reset
  41. - description: MDIO reset
  42. reset-names:
  43. items:
  44. - const: mac
  45. - const: mdio
  46. mdio:
  47. $ref: mdio.yaml#
  48. unevaluatedProperties: false
  49. required:
  50. - compatible
  51. - reg
  52. - interrupts
  53. - phy-mode
  54. - clocks
  55. - clock-names
  56. - resets
  57. - reset-names
  58. unevaluatedProperties: false
  59. examples:
  60. # Lager board
  61. - |
  62. eth0: ethernet@19000000 {
  63. compatible = "qca,ar9330-eth";
  64. reg = <0x19000000 0x200>;
  65. interrupts = <4>;
  66. resets = <&rst 9>, <&rst 22>;
  67. reset-names = "mac", "mdio";
  68. clocks = <&pll 1>, <&pll 2>;
  69. clock-names = "eth", "mdio";
  70. phy-mode = "mii";
  71. phy-handle = <&phy_port4>;
  72. };
  73. eth1: ethernet@1a000000 {
  74. compatible = "qca,ar9330-eth";
  75. reg = <0x1a000000 0x200>;
  76. interrupts = <5>;
  77. resets = <&rst 13>, <&rst 23>;
  78. reset-names = "mac", "mdio";
  79. clocks = <&pll 1>, <&pll 2>;
  80. clock-names = "eth", "mdio";
  81. phy-mode = "gmii";
  82. fixed-link {
  83. speed = <1000>;
  84. full-duplex;
  85. };
  86. mdio {
  87. #address-cells = <1>;
  88. #size-cells = <0>;
  89. switch10: switch@10 {
  90. compatible = "qca,ar9331-switch";
  91. reg = <0x10>;
  92. resets = <&rst 8>;
  93. reset-names = "switch";
  94. interrupt-parent = <&miscintc>;
  95. interrupts = <12>;
  96. interrupt-controller;
  97. #interrupt-cells = <1>;
  98. ports {
  99. #address-cells = <1>;
  100. #size-cells = <0>;
  101. switch_port0: port@0 {
  102. reg = <0x0>;
  103. ethernet = <&eth1>;
  104. phy-mode = "gmii";
  105. fixed-link {
  106. speed = <1000>;
  107. full-duplex;
  108. };
  109. };
  110. switch_port1: port@1 {
  111. reg = <0x1>;
  112. phy-handle = <&phy_port0>;
  113. phy-mode = "internal";
  114. };
  115. switch_port2: port@2 {
  116. reg = <0x2>;
  117. phy-handle = <&phy_port1>;
  118. phy-mode = "internal";
  119. };
  120. switch_port3: port@3 {
  121. reg = <0x3>;
  122. phy-handle = <&phy_port2>;
  123. phy-mode = "internal";
  124. };
  125. switch_port4: port@4 {
  126. reg = <0x4>;
  127. phy-handle = <&phy_port3>;
  128. phy-mode = "internal";
  129. };
  130. };
  131. mdio {
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. interrupt-parent = <&switch10>;
  135. phy_port0: ethernet-phy@0 {
  136. reg = <0x0>;
  137. interrupts = <0>;
  138. };
  139. phy_port1: ethernet-phy@1 {
  140. reg = <0x1>;
  141. interrupts = <0>;
  142. };
  143. phy_port2: ethernet-phy@2 {
  144. reg = <0x2>;
  145. interrupts = <0>;
  146. };
  147. phy_port3: ethernet-phy@3 {
  148. reg = <0x3>;
  149. interrupts = <0>;
  150. };
  151. phy_port4: ethernet-phy@4 {
  152. reg = <0x4>;
  153. interrupts = <0>;
  154. };
  155. };
  156. };
  157. };
  158. };