ARK-OS/arkos/kernel/Documentation/devicetree/bindings/net/nxp,s32-dwmac.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2021-2024 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,s32-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP S32G2xx/S32G3xx/S32R45 GMAC ethernet controller

maintainers:
  - Jan Petrous (OSS) <jan.petrous@oss.nxp.com>

description:
  This device is a Synopsys DWC IP, integrated on NXP S32G/R SoCs.
  The SoC series S32G2xx and S32G3xx feature one DWMAC instance,
  the SoC S32R45 has two instances. The devices can use RGMII/RMII/MII
  interface over Pinctrl device or the output can be routed
  to the embedded SerDes for SGMII connectivity.

properties:
  compatible:
    oneOf:
      - const: nxp,s32g2-dwmac
      - items:
          - enum:
              - nxp,s32g3-dwmac
              - nxp,s32r45-dwmac
          - const: nxp,s32g2-dwmac

  reg:
    items:
      - description: Main GMAC registers
      - description: GMAC PHY mode control register

  nxp,phy-sel:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to the GPR syscon node
          - description: offset of PHY selection register
    description:
      This phandle points to the GMAC_0_CTRL_STS register which controls the
      GMAC_0 configuration options.  The register lets you select the PHY
      interface and the PHY mode.  It also controls if the FTM_0 or FTM_1
      FlexTimer Modules connect to GMAC_0.

  interrupts:
    maxItems: 1

  interrupt-names:
    const: macirq

  clocks:
    items:
      - description: Main GMAC clock
      - description: Transmit clock
      - description: Receive clock
      - description: PTP reference clock

  clock-names:
    items:
      - const: stmmaceth
      - const: tx
      - const: rx
      - const: ptp_ref

required:
  - clocks
  - clock-names

allOf:
  - $ref: snps,dwmac.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/phy/phy.h>
    bus {
      #address-cells = <2>;
      #size-cells = <2>;

      ethernet@4033c000 {
        compatible = "nxp,s32g2-dwmac";
        reg = <0x0 0x4033c000 0x0 0x2000>, /* gmac IP */
              <0x0 0x4007c004 0x0 0x4>;    /* GMAC_0_CTRL_STS */
        nxp,phy-sel = <&gpr 0x4>;
        interrupt-parent = <&gic>;
        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "macirq";
        snps,mtl-rx-config = <&mtl_rx_setup>;
        snps,mtl-tx-config = <&mtl_tx_setup>;
        clocks = <&clks 24>, <&clks 17>, <&clks 16>, <&clks 15>;
        clock-names = "stmmaceth", "tx", "rx", "ptp_ref";
        phy-mode = "rgmii-id";
        phy-handle = <&phy0>;

        mtl_rx_setup: rx-queues-config {
          snps,rx-queues-to-use = <5>;
        };

        mtl_tx_setup: tx-queues-config {
          snps,tx-queues-to-use = <5>;
        };

        mdio {
          #address-cells = <1>;
          #size-cells = <0>;
          compatible = "snps,dwmac-mdio";

          phy0: ethernet-phy@0 {
            reg = <0>;
          };
        };
      };
    };